High-Precision Mixed-Signal Microcontroller High-Performance, Low

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High-Precision Mixed-Signal Microcontroller High-Performance, Low

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8/05
High-Precision Mixed-Signal Microcontroller
High-Performance, Low-Power, 16-Bit RISC Core 8MHz Operation, Approaching 1MIPS 3.3V Core Instructions, Most Single-Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/ Decrement 16-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data 16-Bit, General-Purpose Working Registers Optimized C-Compiler (High-Speed/Density Code) Program Data Memory 16kWords Flash Memory 1,000,000 Flash Write/Erase Cycles Words Internal Data JTAG Bootloader Programming Dual, 16-Bit Sigma-Delta ADCs Differential Analog Input Channels Programmable Gain Integrated Sinc3 Filters Digital Phase Compensation Trimmable Bandgap Reference Peripheral Features General-Purpose Pins 112-Segment Driver Segments Static, 1/2, Bias Supported External Resistors Required Serial USARTs, with Infrared Support One-Cycle, Hardware Multiply/ Accumulate with 40-Bit Accumulator Three 16-Bit Programmable Timers/Counters, with Infrared Support 8-Bit, Subsecond, System Timer/Alarm Battery-Backed, 32-Bit with Time-of-Day Alarm Digital Trim Programmable Watchdog Timer Flexible Programming Interface Bootloader Simplifies Programming In-System Programming Through JTAG Supports In-Application Programming Flash Memory Power Consumption 28mA 8MHz, 3.3V Flash Operation 320µA Standby Current Sleep Mode Low-Power Divide-by-256 Mode
MAXQ3120
MAXQ3120 microcontroller high-performance, 16-bit microcontroller that incorporates dual, true-differential, 16-bit sigma-delta analog-to-digital converters (ADCs), liquid-crystal display (LCD) interface that drive segments, real-time clock (RTC) module with dedicated battery-backup supply. MAXQ3120 uniquely suited single-phase electricity metering market, used application that requires high-performance operation. device operate maximum 8MHz (DVDD 3.3V). MAXQ3120 16kWords flash memory, words RAM, three 16-bit timers, universal synchronous/asynchronous receiver/transmitters (USARTs). microcontroller core powered single 3.3V supply, additional battery supply keeps running during power outages.
Applications
Single-Phase Electricity Metering Battery-Powered Portable Devices Electrochemical Optical Sensors Industrial Control Data-Acquisition Systems Data Loggers Home Appliances Consumer Electronics Thermostats/Humidity Sensors Security Sensors Chemical Sensors HVAC Smart Transmitters
Ordering Information
PART MAXQ3120-FFN MAXQ3120-FFN+ TEMP RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE MQFP MQFP
+Denotes Pb-free/RoHS-compliant device. Selector Guide, Typical Operating Circuit, Configuration appear data sheet.
MAXQ trademark Maxim Integrated Products, Inc. Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, www.maxim-ic.com/errata.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
High-Precision Mixed-Signal Microcontroller MAXQ3120
ABSOLUTE MAXIMUM RATINGS
Voltage Range DVDD Relative DGND .-0.3V +4.0V Voltage Range AVDD Relative AGND.-0.3V +4.0V Voltage Range AGND Relative DGND .-0.3V +0.3V Voltage Range AVDD Relative DVDD .-0.3V +0.3V Voltage Range Relative DGND Except AN0+, AN0-, AN1+, AN1-.-0.3V (DVDD 0.5V) Voltage Range AN0+, AN0-, AN1+, AN1- Relative AGND .-4.0V +4.0V Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-65°C +150°C Soldering Temperature .See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(DVDD, AVDD VRST 3.6V, VREF 1.25V (external), fHFXIN 8MHz, -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Digital Supply Voltage Digital Supply Ramp Rate Digital Power-Fail Reset VRST IDD1 Active Current (Note IDD2 IDD3 IDD4 IDD5 Stop-Mode Current (DVDD plus AVDD) Battery Supply Voltage Battery Current Input High Voltage Input Voltage Input Hysteresis (Schmitt) Output High Voltage (All Ports) Output Voltage (All Ports, RESET) Input Current (All Ports) RESET Pullup Resistance Input Leakage (All Ports) ISTOP VBAT IBAT VIHYS RRST Weak pullup disabled +1.5mA +2.5mA sink current 3.65mA sink current 0.4V; weak pullup enabled DVDD DVDD RTCE DVDD VBAT 3.6V DVDD -0.3 mode mode mode mode mode SYMBOL DVDD controlled placing higher capacitor between DVDD ground CONDITIONS VRST DVDD DVDD 3.03 UNITS V/ms
High-Precision Mixed-Signal Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(DVDD, AVDD VRST 3.6V, VREF 1.25V (external), fHFXIN 8MHz, -40°C +85°C, unless otherwise noted.) (Note
PARAMETER Analog Supply Voltage Active Analog Supply Current Power-Down Analog Supply Current SYMBOL AVDD IAVDD AVDD DVDD Normal operation APD2:0 111b CONDITIONS 2.65 UNITS
MAXQ3120
ANALOG-TO-DIGITAL CONVERTER ACCURACY missing codes, with software lowpass Resolution filter (see Appendix Offset Error Gain Gain Error Gain-Error Drift Gain-Error Match Power-Supply Rejection PSRR AN0+, AN0- AGND; AVDD 3.0V 3.6V DVDD 3.3V, AVDD 3.3V, 25mV, peak-to-peak sine wave 65Hz, gain Signal-to-Noise Ratio With software lowpass filter, cutoff 21st harmonic (see Appendix With software lowpass filter, cutoff harmonic (see Appendix Total Harmonic Distortion DVDD 3.3V, AVDD 3.3V, 25mV, peak-to-peak sine wave 65Hz, gain 21st harmonic) ANALOG-TO-DIGITAL CONVERTER DYNAMIC SPECIFICATIONS Gain
±5.0 ±5.0 ±0.5
bits
ANALOG-TO-DIGITAL CONVERTER INPUTS Input-Voltage Range Input Sampling Capacitance (Note Input Sampling Rate Sample Output Rate Input Impedance AGND (Note Differential Input Impedance (Note Input Bandwidth (-3dB) Reference Input Voltage Reference Input Sampling Capacitance Reference Input Sampling Rate VREF Gain Gain Gain Gain AN0+, AN0-; AN1+, AN1- AGND Channel (Note Gain Gain 1.33 fHFXIN 1500 1.25 1.33 sample
High-Precision Mixed-Signal Microcontroller MAXQ3120
ELECTRICAL CHARACTERISTICS (continued)
(DVDD, AVDD VRST 3.6V, VREF 1.25V (external), fHFXIN 8MHz, -40°C +85°C, unless otherwise noted.) (Note
PARAMETER INTERNAL REFERENCE Reference Output Voltage Reference-Output Temperature Coefficient Load Regulation INTERFACE Reference Voltage Bias Voltage Bias Voltage Adjustment Voltage (Note Bias Resistor Adjust Resistor VLCD VLCD1 VLCD2 VADJ RLCD RLADJ LRA4:LRA0 Segment driven VLCD; VLCD ISEGxx -3µA, guaranteed design Segment driven VLCD1; VLCD1 ISEGxx -3µA, guaranteed design Segment driven VLCD2; VLCD2 ISEGxx -3µA, guaranteed design Segment driven VADJ; VADJ ISEGxx +3µA, guaranteed design CLOCK SOURCE External Crystal Frequency REAL-TIME CLOCK Input Frequency JTAG/FLASH PROGRAMMING JTAG Clock Rate Flash Erase Time Flash Programming Time Write/Erase Cycles Data Retention 1,000,000 fTCK Mass erase Page erase sysclk Cycles Years f32KIN 32kHz watch crystal 32.768 fHFXIN VLCD 0.02 VLCD1 0.02 VLCD2 0.02 VADJ Guaranteed design Guaranteed design Guaranteed design VADJ (VLCD VADJ) VADJ (VLCD VADJ) VLCD VLCD1 VLCD2 VLCD DVDD With VREF bandgap trimming (ATRM[4:0] 01111b) IREF ±2µA, 12pF 1.25 ±120 ±500 ppm/°C µV/µA SYMBOL CONDITIONS UNITS
Segment Voltage
VSEGxx
Note Specifications -40°C guaranteed design production tested. typical values guaranteed design characterization production tested. Note Tested with +25°C, DVDD 3.3V, peripherals inactive except port pins. Note These numbers guaranteed design tested. Note calculated (fHFXIN Note calculated (fHFXIN CIN). Note calculated (fHFXIN CIN). Note Assumes that external components connected VLCD, VLCD1, VLCD2, VADJ.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Typical Operating Characteristics
+25°C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT CLOCK FREQUENCY
MAXQ3120 toc01
PORT HIGH OUTPUT VOLTAGE SOURCE CURRENT
MAXQ3120 toc02
PORT LOW-OUTPUT VOLTAGE SINK CURRENT
+85°C DVDD 2.8V
MAXQ3120 toc03
DVDD +3.6V IDD1 (mA)
+85°C +25°C DVDD 2.8V
-40°C +25°C
+85°C
-40°C, +25°C -40°C
fHFXIN (MHz)
(mA)
(mA)
REFERENCE VOLTAGE OUTPUT LOAD CURRENT
MAXQ3120 toc04
SIGNAL-TO-NOISE RATIO INPUT FREQUENCY
MAXQ3120 toc05
1.29 AVDD 3.3V 1.28
+25°C, +85°C +85°C +25°C -40°C -100 IREF (µA) INPUT FREQUENCY (kHz) (dB) VREF +1.25V AVDD 3.3V VREF 1.27
1.26
1.25
1.24
High-Precision Mixed-Signal Microcontroller MAXQ3120
Description
NAME DVDD DGND AVDD AGND VLCD Digital Supply Voltage (+3.3V) Digital Ground Analog Supply Voltage Analog Ground Bias-Control Voltage. Highest drive voltage used bias modes. This must connected external supply when using display controller. Bias, Voltage Next highest drive voltage, used bias modes. internal resistor-divider sets voltage this pin. External resistors capacitors used change voltage drive capability this pin. This must shunted externally VLCD2 when using bias mode. Bias, Voltage Third highest drive voltage, used bias mode only. internal resistor-divider sets voltage this pin. External resistors capacitors used change voltage drive capability this pin. This must shunted externally VLCD1 when using bias mode. Adjustment Voltage. Lowest drive voltage, used bias modes. Connect DGND through external resistor provide external control contrast. Leave disconnected internal contrast adjustment. Digital, Active-Low, Reset Input/Output. held reset when this begins executing from reset vector when released. includes pullup current source should driven open-drain, external source capable sinking excess 2mA. This driven output when internal reset condition occurs. High-Frequency Crystal Input. Connect external crystal between HFXIN HFXOUT generate high-frequency system clock. HFXIN HFXOUT contain integral 16pF load capacitors, external capacitor required. High-Frequency Crystal Output. Connect external crystal between HFXIN HFXOUT generate high-frequency system clock. HFXIN HFXOUT contain integral 16pF load capacitors, external capacitor required. Digital Battery-Backup Supply. This supply provides optional battery backup when DVDD power removed. this supply provided, functions device operate normal, cleared upon power-on reset (POR). 32kHz Crystal Input. Connect external, 32kHz watch crystal between 32KIN 32KOUT generate 32kHz system clock. This clock required operate. 32kHz Crystal Output. Connect external, 32kHz watch crystal between 32KIN 32KOUT generate 32kHz system clock. This clock required operate. Voltage Reference Input/Output. Bias voltage (+1.25V) ADCs. external reference voltage connected this when extremely high accuracy required. Negative Input Sigma-Delta Channel Positive Input Sigma-Delta Channel Negative Input Sigma-Delta Channel Positive Input Sigma-Delta Channel FUNCTION
VLCD1
VLCD2
VADJ
RESET
HFXIN
HFXOUT
VBAT
32KIN 32KOUT VREF AN0AN0+ AN1AN1+
High-Precision Mixed-Signal Microcontroller
Description (continued)
NAME FUNCTION General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt. These port pins function bidirectional pins only. port pins default input mode with weak pullups enabled after reset. Port pins P0.3, P0.4, P0.5 configured external interrupt inputs. alternate functions must enabled from software. P0.0-P0.7/ SQW, RXD0, TXD0, INT0-INT2/ T2A, T2B/ T0G, PORT P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 ALTERNATE FUNCTIONS Square-Wave Output Serial Port Receive Serial Port Transmit Timer Gate Input Timer Input Timer Input/Output Timer Input/Output (T2P) Timer Input/Output (T2PB) INT0 INT1 INT2
MAXQ3120
64-71
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; Segment-Driver Output. These port pins function both bidirectional pins segment-drive outputs. port pins default input mode with weak pullups enabled after reset. Setting enable (PCFx) group four port pins enables function disables general-purpose function pins that group. PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SEGMENT SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 PCF0 ENABLE
76-80,
P1.0-P1.7/ SEG19- SEG12
PCF1
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; Segment-Driver Output. These port pins function both bidirectional pins segment-drive outputs. port pins default input mode with weak pullups enabled after reset. Setting enable (PCFx) group four port pins enables function disables general-purpose function pins that group. P2.0-P2.7/ SEG20- SEG27 PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SEGMENT SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 PCF3 PCF2 ENABLE
28-34,
High-Precision Mixed-Signal Microcontroller MAXQ3120
Description (continued)
NAME FUNCTION General-Purpose, 8-Bit, Digital, I/O, Type-C Port. These port pins function bidirectional pins only. port pins default input mode with weak pullups enabled after reset. JTAG functions enabled default following reset; other alternate functions must enabled from software. 54-58 P3.0-P3.7/ TDO, TDI, TMS, TCK, TXDI, RXDI SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 COM0 COM1 COM2 COM3 N.C. PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 ALTERNATE FUNCTION TDO-JTAG Data TDI-JTAG Data TMS-JTAG Mode Select TCK-JTAG Clock Serial Port Transmit Serial Port Receive
Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Segment Driver. Dedicated drive output. Common Driver. Dedicated common-voltage output. Common Driver. Dedicated common-voltage output. Common Driver. Dedicated common-voltage output. Common Driver. Dedicated common-voltage output. Connection
High-Precision Mixed-Signal Microcontroller
Functional Diagram
AVDD AN0+ ANALOG FRONT AN0AN1+ AN1AGND
MAXQ3120
CHANNEL OUTPUT
CHANNEL SINC3 FILTER
CHANNEL OUTPUT
MAXQ3120
FRONT
CHANNEL SINC3 FILTER
CHANNEL PHASE DELAY
CHANNEL MODULATOR
CHANNEL MODULATOR
VREF DVDD T0INT TIMER T1INT TIMER T2INT TIMER P0.3/INT0/T0G P0.4/INT1/T0 P0.5/INT2/T1 P0.6/T2A P0.7/T2B P0.0/SQW INFRARED CONTROL U0INT SERIAL USART RXD0 TXD0 RXD1 SERIAL USART TXD1 PORT DRIVERS P0.1/RXD0 P0.2/TXD0 P3.7/RXD1 P3.6/TXD1
INTERRUPT CONTROLLER
EXTINT
WATCHDOG TIMER
U1INT
REGISTER FILE DVDD DP[0] DP[1] P3.3/TCK P3.2/TMS P3.1/TDI P3.0/TDO JTAG BOOTLOAD DEBUG INTERFACE 16-BIT RISC CORE BP[Offs]
P3.4 P3.5 P1[7:0] SEG[12:19] P2[7:0] SEG[27:20] DGND
(32kB) FLASH
SEG[27:12]
VLCD RESET DGND TIME DAY, INTERVAL HFXIN HFXOUT SRAM VLCD1 MULTIPLY DRIVER DISPLAY DGND SEG[11:0] COM[3:0] VBAT 32kHz CLOCK VADJ
VLCD2
TIMER CLOCKS
32KIN 32KOUT
REAL-TIME CLOCK, ALARMS (BATTERY BACKED)
High-Precision Mixed-Signal Microcontroller MAXQ3120
Detailed Description
following introduction primary features microcontroller. More detailed descriptions device features found data sheets, errata sheets, user's guides described later Additional Documentation section. instruction. Bits instruction represent source transfer. Depending value format field, this either 8-bit immediate value source register. this field represents register, lower four bits contain module specifier upper four bits contain register index that module. Bits represent destination transfer. This value always represents destination register, with lower four bits containing module specifier upper three bits containing register subindex within that module. following types instructions require prefix register, PFX, supply additional data. Loading 16-bit immediate value (with nonzero high byte) into register Branching 16-bit absolute destination address (LJMP LCALL) Selecting upper registers system register module destination Selecting upper registers peripheral register module source Selecting upper registers peripheral register module destination these instruction types, prefix register used supply additional immediate value bits, source bits, destination bits needed. This prefix register write inserted automatically assembler requires only additional execution cycle these conditions.
MAXQ Core Architecture
MAXQ3120 low-cost, high-performance, CMOS, 16-bit RISC microcontroller with flash memory integrated 112-segment controller. structured highly advanced, accumulator-based, 16-bit RISC architecture. Fetch execution operations completed cycle without pipelining, because instruction contains both code data. result streamlined million instructionsper-second (MIPS) microcontroller. highly efficient core supported 16-level hardware stack, enabling fast subroutine calling task switching. Data quickly efficiently manipulated with three internal data pointers. Multiple data pointers allow more than function access data memory without having save restore data pointers each time. data pointers automatically increment decrement following operation, eliminating need software intervention. result, application speed greatly increased.
Instruction
instruction composed fixed-length, 16-bit instructions that operate registers memory locations. instruction highly orthogonal, allowing arithmetic logical operations register along with accumulator. System registers control functionality common MAXQ microcontrollers, while peripheral registers control peripherals functions specific MAXQ3120. registers subdivided into register modules. family architecture modular, that devices modules reuse code developed existing products. architecture transport-triggered. This means that writes reads from certain register locations also cause side effects occur. These side effects form basis higher-level codes defined assembler, such ADDC, JUMP, etc. codes actually implemented MOVE instructions between certain system register locations, while assembler handles encoding, which need concern programmer. 16-bit instruction word designed efficient execution. indicates format source field
Memory Organization
device incorporates several memory areas: 2kWords utility 16kWords flash memory program storage words SRAM storage temporary variables 16-level, 16-bit-wide stack memory storage program return addresses general-purpose memory arranged default Harvard architecture, with separate address spaces program data memory. configuration program data space depends current execution location. When executing code from flash memory, SRAM utility accessible data space. When executing code from SRAM, flash memory utility accessible data space. When executing code from utility ROM, flash memory SRAM accessible data space.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Refer user's guide supplement this device more details. cases, whichever memory segment currently being executed from cannot accessed data space. allow lookup tables similar constructs flash memory, utility contains lookup block copy routines (refer user's guide supplement this device more details). incorporation flash memory allows device reprogrammed, eliminating expense throwing away one-time programmable devices during development field upgrades. Flash memory password protected with 16-word key, denying access program memory unauthorized individuals. itly store retrieve data using PUSH, POP, POPI instructions. reset, stack pointer, initializes stack (0Fh). CALL, PUSH, interrupt-vectoring operations increment then store value stack location pointed RET, RETI, POP, POPI operations retrieve value stack location pointed then decrement
Utility
utility 2kWord block internal memory that defaults starting address 8000h. utility consists subroutines that called from application software. These include: In-system programming (bootloader) over JTAG interface In-circuit debug routines Test routines (internal memory tests, memory loader, etc.) User-callable routines in-application flash programming code space table lookup
DATA SPACE (BYTE MODE) DATA SPACE (WORD MODE)
Stack Memory
16-bit-wide internal stack provides storage program return addresses general-purpose use. stack used automatically processor when CALL, RET, RETI instructions executed interrupts serviced. stack also used explic-
SYSTEM REGISTERS
PROGRAM SPACE
A0FFh DATA SRAM A000h
PERIPHERAL REGISTERS PROGRAM FLASH MASKED x1Fh UTILITY
87FFh UTILITY 8000h 3FFFh
8FFFh UTILITY 8000h
87FFh
8000h
01FFh DATA SRAM 0000h 0000h DATA SRAM
00FFh
STACK
0000h
Figure Memory
High-Precision Mixed-Signal Microcontroller
Following reset, execution begins utility ROM. software determines whether program execution should immediately jump start user-application code (located address 0000h), special routines mentioned. Routines within utility user-accessible called subroutines application software. More information utility contents contained user's guide supplement this device. Some applications require protection against unauthorized viewing program code memory. these applications, access in-system programming, inapplication programming, in-circuit debugging functions prohibited until password been supplied. single password-lock (PWL) implemented register. When (power-on reset default), password required access utility ROM, including in-circuit debug in-system programming routines that allow reading writing internal memory. When cleared zero, these utilities fully accessible without password. password automatically ones following mass erase. Activating JTAG interface loading test access port (TAP) with system programming instruction invokes bootloader. Setting during reset through JTAG interface executes bootloader-mode program that resides utility ROM. When programming complete, bootloader clear reset device, allowing device bypass utility begin execution application software. following bootloader functions supported: Load Dump Verify Erase In-Application Programming in-application programming feature allows microcontroller modify flash program memory while simultaneously executing application software. This allows on-the-fly software updates mission-critical applications that cannot afford downtime. Alternatively, allows application develop custom loader software that operate under control application software. utility contains useraccessible flash programming functions that erase program flash memory. These functions described detail user's guide supplement this device.
MAXQ3120
Programming
flash memory microcontroller programmed different methods: in-system programming in-application programming. Both methods afford great flexibility system design well reduce life-cycle cost embedded system. These features password protected prevent unauthorized access code memory. In-System Programming internal bootstrap loader allows device reloaded over simple JTAG interface. result, system software upgraded in-system, eliminating need costly hardware retrofit when software updates required. Remote software uploads possible that enable physically inaccessible applications frequently updated. interface hardware JTAG connection another microcontroller, connection serial port using serial-to-JTAG converter such MAXQJTAG-001, available from Maxim Integrated Products/Dallas Semiconductor. insystem programmability required, commercial gang programmer used mass programming.
Register
Most functions device controlled sets registers. These registers provide working space memory operations well configuring addressing peripheral registers device. Registers divided into major types: system registers peripheral registers. common register set, also known system registers, includes ALU, accumulator registers, data pointers, interrupt vectors control, stack pointer. peripheral registers define additional functionality that included different products based MAXQ architecture. This functionality broken into discrete modules that only features required given product need included. Tables show MAXQ3120 register set.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table System Register
REGISTER INDEX (8h) CKCN WDCN (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] (Bh) (Ch) (Dh) LC[0] LC[1] (Eh) Offs GRXL BP[offs] (Fh) DP[0] DP[1]
Note: Names that appear italics indicate that bits register read-only. Names that appear bold indicate that register bits wide. Registers module addressable.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table System Register Functions
REGISTER CKCN WDCN A[0.15] LC[0] LC[1] Offs GRXL BP[offs] DP[0] DP[1] GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.0 bits) GR.7 GR.6 GR.5 GR.4 GR.3 GR.2 GR.1 GR.9 GR.9 GR.1 GR.0 GR.8 GR.8 GR.0 bits) GR.15 GR.14 GR.15 GR.14 GR.7 GR.6 BP[offs] bits) DP[0] bits) DP[1] bits) GR.13 GR.12 GR.11 GR.10 GR.13 GR.12 GR.11 GR.10 GR.5 GR.4 GR.3 GR.2 REGISTER A[n] bits) bits) bits) bits) LC[0] bits) LC[1] bits) Offs bits) WBS2 WBS1 WBS0 SDPS1 SDPS0 bits) EWDI CGDS GPF1 STOP GPF0 WDIF MOD2 PMME WTRF MOD1 MOD0 bits)
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table System Register Reset Values
REGISTER CKCN WDCN A[0.15] LC[0] LC[1] Offs GRXL BP[offs] DP[0] DP[1] REGISTER
Note: Bits marked with have indeterminate value upon reset. Bits marked with have special behavior upon reset. Refer user's guide supplement this device more details.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table Peripheral Register
REGISTER INDEX (0h) EIF0 EIE0 EIES0 RTRM RCNT RTSS RTSH RTSL RSSA RASH RASL (1h) T0CN SCON0 SBUF0 SCON1 SBUF1 SMD0 SMD1 ICDF (2h) T1CN T2CNA T2RH T2CH IRCN T1CL T1CH T1MD T2CNB T2CFG (3h) MCNT MC1R MC0R ADCN ATRM LCRA LCFG LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 (4h) (5h)
Note: Names that appear italics indicate that bits register read-only. Names that appear bold indicate that register bits wide. Registers module addressable.
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table Peripheral Register Functions
REGISTER EIF0 EIE0 EIES0 RTRM RCNT RTSH RTSL RSSA RASH RASL T0CN SCON0 SBUF0 SCON1 SBUF1 SMD0 SMD1 EPWM bits) bits) SMOD FEDE SM0/FE SM0/FE RASL bits) GATE ALSF ALDF TSGN RDYE REGISTER bits) bits) bits) bits)
bits) bits) bits) bits)
bits) bits) bits) bits) bits) BUSY RTCE
RTSH bits) RTSL bits) RSSA bits) RASH bits)
bits) bits)
SBUF0 bits)
SBUF1 bits) SMOD FEDE
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table Peripheral Register Functions (continued)
REGISTER ICDF T1CN T2CNA T2RH T2CH IRCN T1CL T1CH T1MD T2CNB T2CFG MCNT MC1R MC0R ADCN ATRM LCRA LCFG LCD[0.13] DUTY1 DUTY0 FRM3 FRM2 FRM1 APD2 APD1 bits) bits) FRM0 PCF3 LCCS PCF2 LRIG PCF1 PCF0 ABGT bits) LRA3 LRA2 LRA1 LRA0 bits) bits) MC1R bits) MC0R bits) APD0 EDBI FLU1 FLU0 bits) FOV1 FOV0 ABF1 ABF0 ET2L T2OE0 T2POL0 REGISTER EXF1 T1OE DCEN PSS1 EXEN1 PSS0 C/T1 CPRL1
bits) bits) TR2L CPRL2 G2EN
T2V[15:8] bits) T2R[15:8] bits) T2C[15:8] bits) IREN IRTX IRBB
T1CL bits) T1CH bits) TCC2 TF2L TC2L
T2OE1 T2POL1
bits) bits) bits) T2CI DIV2 DIV1 DIV0 T2MD OPCS CCF1 CCF0 C/T2
MSUB MMAC
bits) bits) bits)
LCD[n] bits)
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table Peripheral Register Reset Values
REGISTER EIF0 EIE0 EIES0 RTRM RCNT RTSS RTSH RTSL RSSA RASH RASL T0CN SCON0 SBUF0 SCON1 SBUF1 SMD0 SMD1 ICDF T1CN REGISTER
High-Precision Mixed-Signal Microcontroller MAXQ3120
Table Peripheral Register Reset Values (continued)
REGISTER T2CNA T2RH T2CH IRCN T1CL T1CH T1MD T2CNB T2CFG MCNT MC1R MC0R ADCN ATRM LCRA LCFG LCD[0.13] REGISTER
Note: Bits marked with have indeterminate value upon reset. Bits marked with have special behavior upon reset. Refer user's guide supplement this device more details.
High-Precision Mixed-Signal Microcontroller
System Timing
MAXQ3120 generates internal system clock from external high-frequency crystal. Because MAXQ3120 includes internal capacitors this purpose, external capacitors required high-frequency crystal. MAXQ3120 should driven directly external clock source. crystal warmup counter enhances operational reliability. Each time external crystal oscillation must restart, such after exiting stop mode, device initiates crystal warmup period 65,536 oscillations. This allows time crystal amplitude frequency stabilize before using clock source. activity. When more processing power required, microcontroller increase operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether system clock cycle oscillator cycles. performing this function software, lower power state entered without cost additional hardware. extremely power-sensitive applications, additional low-power modes available. Divide-by-256 power-management mode (PMM) (PMME CD1:0 00b) Stop mode (STOP PMM, system clock oscillator cycles, significantly reducing power consumption while microcontroller functions reduced speed. optional switchback feature allows enabled interrupt sources, such external interrupts USARTs, cause processor quickly exit mode return faster internal clock rate.
MAXQ3120
Power Management
Advanced power-management features minimize power consumption dynamically matching processing speed device required performance level. This means device operation slowed power consumption minimized during periods reduced
POWER-ON RESET STOP
XDOG COUNT RESET XDOG STARTUP TIMER INPUT CRYSTAL KILL CRYSTAL XDOG DONE RESET WATCHDOG TIMER
RESET WATCHDOG RESET WATCHDOG INTERRUPT
MAXQ3120
STOP ENABLE CLOCK GENERATION POWER-ON RESET SYSTEM CLOCK
32kHz CRYSTAL
REAL-TIME CLOCK CONTROLLER
GLITCH-FREE
CLOCK DIVIDER
INPUT CRYSTAL MONITOR ENABLE POWER MONITOR
SELECTOR DEFAULT
INTERRUPT/SERIAL PORT RESET STOP
Figure Clock Sources
High-Precision Mixed-Signal Microcontroller
Power consumption reaches minimum stop mode. this mode, external high-frequency oscillator, system clock, code execution halted. Stop mode exited when enabled external interrupt triggered, external reset signal applied RESET pin, time-of-day alarm activated. 32kHz clock continues running during stop mode, enabling following peripherals keep running during stop mode. always continues running during stop mode. controller continues running during stop mode running from 32kHz clock (LCCS
MAXQ3120
Serial Port Receive Transmit Interrupts Serial Port Receive Transmit Interrupts Timer Overflow Interrupt Timer Overflow External Trigger Interrupts Timer Compare, Overflow, Capture/ Compare, Overflow Interrupts
Reset Sources
Several reset sources provided microcontroller control. Although code execution halted reset state, high-frequency oscillator 32kHz oscillator continue oscillate. Internal resets such power-on watchdog resets assert RESET low.
Interrupts
Multiple reset sources available quick response internal external events. MAXQ architecture uses single interrupt vector (IV), single interrupt-service routine (ISR) design. maximum flexibility, interrupts enabled globally, individually, module. When interrupt condition occurs, individual flag set, even interrupt source disabled local, module, global level. Interrupt flags must cleared within user-interrupt routine avoid repeated interrupts from same source. Application software must ensure delay between write flag RETI instruction allow time interrupt hardware remove internal interrupt condition. Asynchronous interrupt flags require one-instruction delay synchronous interrupt flags require twoinstruction delay. When enabled interrupt detected, software jumps user-programmable interrupt vector location. register defaults 0000h reset power-up, changed different address, user program must determine whether jump 0000h came from reset interrupt source. Once software control been transferred ISR, interrupt identification register (IIR) determine system register peripheral register source interrupt. specified module then interrogated specific interrupt source software take appropriate action. Because interrupts evaluated user software, user define unique interrupt priority scheme each application. following interrupt sources available. Watchdog Interrupt External Interrupts Time-of-Day Subsecond Alarms
Power-On Reset
internal power-on reset circuit enhances system reliability. This circuit forces device perform power-on reset whenever rising voltage climbs above VRST level. this point, following events occur: registers circuits enter their reset state (except RTC, battery-backed) flag (WDCN.7) indicate source reset Code execution begins location 8000h
Watchdog Timer Reset
watchdog timer functions described MAXQ Family User's Guide. Execution resumes location 8000h following watchdog timer reset.
External System Reset
Asserting external RESET causes device enter reset state. external reset functions described MAXQ Family User's Guide. Execution resumes location 8000h after RESET released.
Ports
microcontroller uses Type Type bidirectional ports described MAXQ Family User's Guide. port types allows maximum flexibility when interfacing external peripherals. Each port eight independent, general-purpose pins three configure/control registers. Many pins support alternate functions such timers interrupts, which enabled, controlled, monitored dedicated peripheral registers. Using alternate function automatically converts that function.
High-Precision Mixed-Signal Microcontroller
Type port pins have Schmitt Trigger receivers full CMOS output drivers, support alternate functions. either tri-stated weak pullup when defined input, dependent state corresponding output register. Type port pins have Schmitt Trigger receivers full CMOS output drivers, support alternate functions. either tri-stated weak pullup when defined input, dependent state corresponding output register. Type pins also have interrupt capability. 16-bit parallel registers (MC2, MC1, MC0), status/control register (MCNT). Loading registers automatically initiate operation, saving time repetitive calculations. accumulate function hardware multiplier essential element digital filtering, signal processing, proportional/integral/ derivative (PID) algorithm-based control systems. hardware multiplier module supports following operations: Multiply unsigned bit) Multiply signed bit) Multiply-accumulate unsigned bit) Multiply-accumulate signed bit) Square unsigned bit) Square signed bit) Square-accumulate unsigned bit) Square-accumulate signed bit)
MAXQ3120
High-Speed Hardware Multiplier
hardware multiplier module performs high-speed multiply, square, accumulate operations, complete 16-bit 16-bit multiply-and-accumulate operation single cycle. hardware multiplier consists 16-bit parallel-load operand registers (MA, MB), 40-bit accumulator that formed three
VDDIO
WEAK
PD.x DIRECTION
VDDIO
ENABLE
PO.x OUTPUT
MAXQ3120
PORT
PI.x INPUT
FLAG
INTERRUPT FLAG
DETECT CIRCUIT
EIES.x TYPE PORT ONLY
Figure Type Port Schematic
High-Precision Mixed-Signal Microcontroller MAXQ3120
Real-Time Clock
binary real-time clock keeps time absolute seconds with 1/256-second resolution. 32-bit second counter count approximately years translated calendar format application software. time-of-day alarm independent subsecond alarm cause interrupt, wake device from stop mode. independent subsecond alarm runs from same RTC, allows application perform periodic interrupts seconds with granularity approximately 3.9ms. This creates additional timer that used measure long periods without performance degradations. Traditionally, long time periods have been measured using multiple interrupts from shorter programmable timers. Each timer interrupt required servicing, with each accompanying interruption slowing system operation. using subsecond timer long-period timer, only interrupt needed, eliminating performance associated with using shorter timer. internal crystal oscillator clocks using integrated load capacitors, gives best performance when mated with 32.768kHz crystal rated load. external load capacitors required. Higher accuracy obtained using digital trim function. frequency accuracy crystalbased oscillator circuit dependent upon crystal accuracy, match between crystal oscillator capacitor load, ambient temperature, etc.
Timer
timer peripheral includes following: 16-bit autoreload timer/counter 16-bit capture 16-bit counter Clock generation output
Timer
timer peripheral includes following: 16-bit autoreload timer/counter 16-bit capture 16-bit counter 8-bit capture 8-bit timer 8-bit counter 8-bit timer Infrared carrier generation support
Watchdog Timer
internal watchdog timer greatly increases system reliability. timer resets processor software execution disturbed. watchdog timer freerunning counter designed periodically reset application software. software operating correctly, counter periodically reset never reaches maximum count. However, software operation interrupted, timer does reset, triggering system reset optionally watchdog timer interrupt. This protects system against electrical noise electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. internal watchdog timer upgrade older designs with external watchdog devices, reducing system cost simultaneously increasing reliability. watchdog timer controlled through bits WDCN register. timeout period four programmable intervals ranging from system clocks default mode, allowing flexibility support different types applications. interrupt occurs system clocks before reset, allowing system execute interrupt place system known, safe state before device performs total system reset. 8MHz, watchdog timeout periods programmed from 512µs 61.7s, depending system clock mode.
Programmable Timers
MAXQ3120 incorporates instance each timer timer timer peripherals. These timers used functions, allowing precise control internal external events. Timer supports optional single-shot, external gating, polarity control options well carrier generation support infrared transmit/receive functions using serial port
Timer
timer peripheral includes following: 8-bit autoreload timer/counter 13-bit 16-bit timer/counter Dual 8-bit timer/counter External pulse counter
High-Precision Mixed-Signal Microcontroller
In-Circuit Debug
Embedded debugging capability available through JTAG-compatible TAP. Embedded debug hardware embedded firmware provide in-circuit debugging capability user application, eliminating need expensive in-circuit emulator. Figure shows block diagram in-circuit debugger. in-circuit debug features include: Hardware debug engine registers able breakpoints register, code, data accesses debug service routines stored utility embedded hardware debug engine independent hardware block microcontroller. debug engine monitor internal activities interact with selected internal registers while executing user code. Collectively, hardware software features allow basic modes in-circuit debugging: Background mode allows host configure in-circuit debugger while continues execute application software full speed. Debug mode invoked from background mode. Debug mode allows debug engine take control CPU, providing read/write access internal registers memory, single-step trace operation.
MAXQ3120
MAXQ3120
DEBUG SERVICE ROUTINES (UTILITY ROM)
DEBUG ENGINE CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
Figure In-Circuit Debugger
Serial Peripherals
MAXQ3120 incorporates 8051-style universal synchronous/asynchronous receiver/transmitters. USARTs allow device conveniently communicate with other RS-232 interface-enabled devices, well serial modems when paired with external RS-232 line driver/receiver. dual independent USARTs communicate simultaneously different baud rates with separate peripherals. USART detect framing errors indicate condition through user-accessible software bit.
MODE Mode Mode Mode Mode TYPE Synchronous Asynchronous Asynchronous Asynchronous START BITS
time base serial ports derived from either division system clock dedicated baud clock generator. following table summarizes operating characteristics well maximum baud rate each mode. Serial port contains additional functionality support low-speed infrared transmission combination with function timer When enabled this mode, serial port automatically outputs waveform generated combining normal serial port output waveform with carrier waveform output timer using logical logical function. output serial port this mode used drive infrared communicate using fixed-frequency carrier modulated signal. Depending drive strength required, output require buffer when used this purpose.
DATA BITS
STOP
BAUD RATE 8MHz 2Mbps 250kbps 250kbps 250kbps
High-Precision Mixed-Signal Microcontroller MAXQ3120
Driver
MAXQ3120 microcontroller incorporates driver that interfaces common low-voltage displays. incorporating driver into microcontroller, design requires only glass rather than considerably more expensive module. Every character glass composed more segments, each which activated selecting appropriate segment common signal. microcontroller drive glass segments multiplexing combinations segment (SEG0-SEG27) outputs four common-signal outputs (COM0-COM3). Eight segment outputs also used general-purpose port pins, they needed drive LCD. segments easily addressed writing dedicated display memory. Once driver settings display memory have been initialized, 14-byte display memory periodically scanned, segment common signals generated automatically selected display frequency. additional processor overhead required while driver running. Unused display memory used general-purpose storage. design further simplified cost-reduced inclusion software-adjustable internal voltagedividers control display contrast. desired, contrast also controlled external resistance. features driver include following: Automatic segment common-drive signal generation Four display modes supported: Static (COM0) duty multiplexed with bias voltages (COM0, COM1) duty multiplexed with bias voltages (COM0, COM1, COM2) duty multiplexed with bias voltages (COM0, COM1, COM2, COM3) segment outputs four common-signal outputs bytes (112 bits) display memory Adjustable frame frequency Internal voltage-divider resistors eliminate requirement external components Internal adjustable resistor allows contrast adjustment without external components Flexibility external resistors adjust drive voltages current capacity simple LCD-segmented glass interface example demonstrates minimal hardware required interface MAXQ3120 microcontroller. two-character controlled, with each character containing seven segments plus decimal point. driver configured duty cycle operation, meaning active segment controlled using combination segment signals, COM0 COM1 signals used select active display.
MAXQ3120
SEG0:7
SEG0
SEG4
SEG1
SEG5
SEG2 SEG3 COM0 COM1 CONNECTED DARK GREY SEGMENTS CONNECTED LIGHT GREY SEGMENTS
SEG6 SEG7
Figure Two-Character, Duty, Interface Example
High-Precision Mixed-Signal Microcontroller
Analog Front-End
MAXQ3120 microcontroller incorporates analog front-end dedicated analog-to-digital conversion. This peripheral converts digitally filters differential signal channels with overhead. conversion channels operate completely parallel, running same sample rate whether channel both channels enabled. both channels use, they powered down conserve supply current. input signals each channel form true differential pair. Each signals (AN0+ AN0- channel AN1+ AN1- channel vary across entire analog input range, without regard level other signal pair. initial stage each channel programmable gain function (1x, 16x) that software independently each channel. Next, second-order sigmadelta modulator samples each input signal. When using both channels measure same signal case when measuring voltage current power calculations), phase-correction buffer provided compensate phase shift between channels caused external circuitry. phasecorrection buffer operates digitally output stream channels delay either channel's stream with respect other channel's stream bits. Next, streams channels travel through digital sinc3 lowpass filters, which convert streams 16-bit values additional processing.
MAXQ3120
AN0+ AN0-
CHANNEL PROGRAMMABLE GAIN
CHANNEL SIGMA-DELTA MODULATOR
CHANNEL SINC3 FILTER
(1x, 16x)
PHASE CORRECTION
AN1+ AN0-
CHANNEL1 PROGRAMMABLE GAIN
CHANNEL SIGMA-DELTA MODULATOR
CHANNEL SINC3 FILTER
(1x, 16x)
Figure Analog Front-End Block Diagram
High-Precision Mixed-Signal Microcontroller MAXQ3120
Applications Information
low-power, high-performance RISC architecture MAXQ3120 makes excellent many portable battery-powered applications that require cost-effective computing. high-throughput core complemented dual-differential channel, 16-bit sigma-delta ADC, 16-bit hardware multiplier-accumulator, allowing implementation sophisticated computational algorithms. Applications benefit from wide range peripheral interfaces, allowing microcontroller communicate with many external devices. With integrated support segments 28), applications support complex user interfaces. Displays driven directly with additional external hardware required. Contrast adjusted using built-in, adjustable resistor. simplified architecture reduces component count board space, critical factors design portable systems. MAXQ3120 ideally suited single-phase electricity metering applications well other applications that require high-precision analog-to-digital conversion signal processing. MAXQ Family User's Guide: MAXQ3120 Supplement, which contains detailed information features specific MAXQ3120, available www.maxim-ic.com/MAXQ3120UG.
Development Technical Support
variety highly versatile, affordably priced development tools this microcontroller available from Maxim/Dallas Semiconductor third-party suppliers, including: Compilers In-circuit emulators Integrated development environments (IDEs) JTAG-to-serial converters programming debugging partial list development tool vendors found website Technical support available through email maxq.support@dalsemi.com.
Definitions
Offset Error
ideal converter, first transition occurs above zero. Offset error amount deviation between measured first transition point ideal point.
Additional Documentation
Designers must have four documents fully features this device. This data sheet contains descriptions, feature overviews, electrical specifications. Errata sheets contain deviations from published specifications. user's guides offer detailed information about programming, device features, operation. following documents downloaded from MAXQ3120 data sheet, which contains electrical/timing specifications descriptions, available www.maxim-ic.com/MAXQ3120. MAXQ3120 errata sheet, available www.maxim-ic.com/errata. MAXQ Family User's Guide, which contains detailed information core features operation, including programming, avaliable www.maximic.com/MAXQUG.
Gain Error
With full-scale analog voltage applied (resulting ones digital code), gain error defined amount deviation between ideal transfer function measured transfer function (with offset error removed). Gain error usually expressed percentage full-scale range (%FSR).
Power-Supply Rejection Ratio
Power-supply rejection ratio (PSRR) ratio changes power supply changes converter output (V). typically measured decibels.
High-Precision Mixed-Signal Microcontroller
Appendix Applying Lowpass Filter (LPF) ApplicationOptimized Performance
MAXQ3120 gives user application program direct access data stream right after sinc3 filters. This unique feature permits MAXQ3120 optimized target applications. With device's 8MIPS processing power 1-cycle MAC, linear filter easily computed user application program. This section provides simple filter improve performance MAXQ3120 power-metering application.
Filter Specifications Coefficients
Input signal frequency (fIN) 60Hz Sampling frequency (fS) 20833Hz Window hamming Cutoff frequency (attenuates after harmonic) 0.06 625Hz Cutoff frequency (for 21st harmonic) 0.18 1875Hz Transition width 0.35 3646Hz Filter length
MAXQ3120
coefficients 21st harmonic). Note that these coefficients have been converted 16-bit fixed-point numbers. shift places required after multiply-accumulate operation.
FILTER_COEFFICIENT_0 FILTER_COEFFICIENT_1 FILTER_COEFFICIENT_2 FILTER_COEFFICIENT_3 FILTER_COEFFICIENT_4 FILTER_COEFFICIENT_5 FILTER_COEFFICIENT_6 FILTER_COEFFICIENT_7 FILTER_COEFFICIENT_8 FILTER_COEFFICIENT_9 FILTER_COEFFICIENT_10 FILTER_COEFFICIENT_11 -288 -786 -1402 -1670 -876 1627 6018 11739 17547 21893 23506 FILTER_COEFFICIENT_12 FILTER_COEFFICIENT_13 FILTER_COEFFICIENT_14 FILTER_COEFFICIENT_15 FILTER_COEFFICIENT_16 FILTER_COEFFICIENT_17 FILTER_COEFFICIENT_18 FILTER_COEFFICIENT_19 FILTER_COEFFICIENT_20 FILTER_COEFFICIENT_21 FILTER_COEFFICIENT_22 21893 17547 11739 6018 1627 -876 -1670 -1402 -786 -288
coefficients harmonic). Note that these coefficients have been converted 16-bit fixed-point numbers. shift places required after multiply-accumulate operation.
FILTER_COEFFICIENT_0 FILTER_COEFFICIENT_1 FILTER_COEFFICIENT_2 FILTER_COEFFICIENT_3 FILTER_COEFFICIENT_4 FILTER_COEFFICIENT_5 FILTER_COEFFICIENT_6 FILTER_COEFFICIENT_7 FILTER_COEFFICIENT_8 FILTER_COEFFICIENT_9 FILTER_COEFFICIENT_10 FILTER_COEFFICIENT_11 1420 2553 4334 6754 9700 12966 16269 19291 21720 23295 23840 FILTER_COEFFICIENT_12 FILTER_COEFFICIENT_13 FILTER_COEFFICIENT_14 FILTER_COEFFICIENT_15 FILTER_COEFFICIENT_16 FILTER_COEFFICIENT_17 FILTER_COEFFICIENT_18 FILTER_COEFFICIENT_19 FILTER_COEFFICIENT_20 FILTER_COEFFICIENT_21 FILTER_COEFFICIENT_22 23295 21720 19291 16269 12966 9700 6754 4334 2553 1420
High-Precision Mixed-Signal Microcontroller MAXQ3120
Filter Results
Below summary values before after applying above LPFs, MAXQ3120 units. application engineer easily implement favorite lowpass filters optimize MAXQ3120 target applications. However, does need consider filter complexity processor resource requirement (CPU cycles storage space) strike optimal balance. above 23-tap takes bytes clock cycles MAXQ3120 complete. Note that number cycles varies from filter filter because number shifts required normalize multiply-accumulate result will vary.
CONDITION Before After LPF, 21st Harmonic After LPF, Harmonic
56.5 68.2 71.5 56.8 70.7 73.8 57.1 71.4 74.7 -84.5 -85.8 -88.9
-81.1 -83.1 -85.7 -77.3 -79.4 -82.0
Selector Guide
PART MAXQ3120-FFN MAXQ3120-FFN+ TEMP RANGE -40°C +85°C -40°C +85°C PROGRAM MEMORY 16kWord Flash 16kWord Flash DATA MEMORY Word SRAM Word SRAM SEGMENTS EXTERNAL INTERRUPTS USARTS PINPACKAGE MQFP MQFP
+Denotes Pb-free/RoHS-compliant device.
High-Precision Mixed-Signal Microcontroller
Configuration
P0.3/INT0/T0G P0.5/INT2/T1 P0.4/INT1/T0 P1.4/SEG15 P1.3/SEG16 P1.2/SEG17 P1.1/SEG18 P1.0/SEG19 P0.1/RXD0
MAXQ3120
DGND
DVDD
N.C.
P1.5/SEG14 P1.6/SEG13 P1.7/SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 VLCD VLCD1 VLCD2 VADJ SEG3 SEG2 SEG1 DGND HFXIN HFXOUT DVDD SEG0 COM3
N.C.
VIEW
P0.2/TXD0
P0.7/T2B
P0.6/T2A
P0.0/SQW RESET 32KOUT 32KIN DVDD DGND P3.7/RXD1 P3.6/TXD1 P3.5 P3.4 P3.3/TCK VBAT AGND VREF N.C. N.C. AN1+ AN1AN0+ AN0AVDD DGND P3.2/TMS P3.1/TDI
MAXQ3120
P2.0/SEG20
P2.1/SEG21
P2.2/SEG22
P2.3/SEG23
P2.4/SEG24
P2.5/SEG25
P2.6/SEG26
MQFP
P2.7/SEG27
P3.0/TDO
COM2
COM1
COM0
DGND
N.C.
N.C.
DVDD
High-Precision Mixed-Signal Microcontroller MAXQ3120
Typical Operating Circuit
DISPLAY INFRARED Tx/Rx
P0.3/INT0/T0G
P0.5/INT2/T1
P0.4/INT1/T0
P1.4/SEG15
P1.3/SEG16
P1.2/SEG17
P1.1/SEG18
P1.0/SEG19
N.C.
P0.2/TXD0
P0.1/RXD0
P0.7/T2B
P0.6/T2A
DGND
DVDD
N.C.
RS-485 Tx/Rx
P1.5/SEG14 P1.6/SEG13 P1.7/SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 VLCD VLCD1 VLCD2 VADJ SEG3 SEG2 SEG1 DGND HFXIN HFXOUT 8MHz DVDD SEG0 COM3
P0.0/SQW RESET 32KOUT 32KIN DVDD DGND P3.7/RXD1 P3.6/TXD1 P3.5 P3.4 P3.3/TCK VBAT AGND VREF N.C. N.C. AN1+ AN1AN0+ AN0AVDD DGND P3.2/TMS P3.1/TDI VOLTAGEDIVIDER 32.768kHz
MAXQ3120
P2.0/SEG20
P2.1/SEG21
P2.2/SEG22
P2.3/SEG23
P2.4/SEG24
P2.5/SEG25
P2.6/SEG26
P2.7/SEG27
P3.0/TDO
N.C.
N.C.
COM2
COM1
COM0
DGND
DVDD
SERIAL EEPROM
LINE CURRENT SHUNT NEUTRAL
LINE
NEUTRAL
High-Precision Mixed-Signal Microcontroller
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
MAXQ3120
Revision History
7/05: 8/05: Original release. Added clarification Resolution condition missing codes, with software lowpass filter, Appendix Deleted paragraph Integral Nonlinearity.
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2005 Maxim Integrated Products Printed registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.
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High-Precision Mixed-Signal Microcontroller High-Performance, Low

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