Low-Power Microcontroller High-Performance, Low-Power, 16-Bit RIS

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Low-Power Microcontroller High-Performance, Low-Power, 16-Bit RIS

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3/06
Low-Power Microcontroller
High-Performance, Low-Power, 16-Bit RISC Core 20MHz Operation, Approaching 1MIPS Dual 1.8V Core/3V Enables Power/Flexible Interfacing Instructions, Most Single Cycle Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement 16-Level Hardware Stack 16-Bit Instruction Word, 16-Bit Data 16-Bit, General-Purpose Working Registers Optimized C-Compiler (High-Speed/Density Code) Program Data Memory 32kWords Flash Memory, Mask HighVolume Applications 10,000 Flash Write/Erase Cycles 1kWord Internal Data JTAG/Serial Boot Loader Programming Peripheral Features General-Purpose Pins 100/132 Segment Driver Segments Static, 1/2, Bias Supported External Resistors Required SPIand 1-Wire® (-RAX/-RAX+ Only) Hardware Ports Serial UARTs One-Cycle, Hardware Multiply/Accumulate with 48-Bit Accumulator Three 16-Bit Programmable Timers/Counters 8-Bit, Subsecond, System Timer/Alarm 32-Bit, Binary Real-Time Clock with Time-of-Day Alarm Programmable Watchdog Timer Flexible Programming Interface Bootloader Simplifies Programming In-System Programming Through JTAG Supports In-Application Programming Flash Memory Ultra-Low-Power Consumption 190µA 8MHz Flash Operation, PMM1 2.2V 700nA Lowest Power Stop Mode Low-Power 32kHz Mode Divide-by-256 Mode
MAXQ2000
MAXQ2000 microcontroller low-power, 16-bit device that incorporates liquid-crystal display (LCD) interface that drive (-RBX/-RBX+) (-RAX/-RAX+) segments. MAXQ2000 uniquely suited blood-glucose monitoring market, used application that requires high performance low-power operation. device operate maximum either 14MHz 1.8V) 20MHz (VDD 2.25V). MAXQ2000 32kWords flash memory, 1kWord RAM, three 16-bit timers, universal synchronous/asynchronous receiver/transmitters (UARTs). Flash memory aids prototyping low-volume production. microcontroller core powered 1.8V supply, with separate supply optimum flexibility. ultra-lowpower sleep mode makes these parts ideal batterypowered, portable equipment.
Applications
Medical Instrumentation Battery-Powered Portable Devices Electrochemical Optical Sensors Industrial Control Data-Acquisition Systems Data Loggers Home Appliances Consumer Electronics Thermostats/Humidity Sensors Security Sensors Chemical Sensors HVAC Smart Transmitters
Typical Operating Circuit, Configurations, Ordering Information appear data sheet.
MAXQ registered trademark Maxim Integrated Products, Inc. trademark Motorola, Inc. 1-Wire registered trademark Dallas Semiconductor Corp. Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, www.maxim-ic.com/errata. Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Low-Power Microcontroller MAXQ2000
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground Except .-0.5V (VDDIO 0.5)V Voltage Range Relative Ground .-0.5V +2.75V Voltage Range VDDIO Relative Ground.-0.5V +3.6V Operating Temperature Range .-40°C +85°C Storage Temperature Range .-65°C +150°C Soldering Temperature .See IPC/JEDEC J-STD-020 .Specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD VDD(MIN) VDD(MAX), VDDIO 2.7V 3.6V, -40°C +85°C.) (Note
PARAMETER Core Supply Voltage Supply Voltage SYMBOL VDDIO IDD1 IDD2 Active Current, fHFIN 14MHz (Note IDD3 IDD4 IDD5 IDD6 IDD1 IDD2 Active Current, fHFIN 20MHz (Note IDD3 IDD4 IDD5 IDD6 mode mode mode mode PMM1 mode PMM2 mode; 32KIN 32.768kHz mode mode mode mode PMM1 mode PMM2 mode; 32KIN 32.768kHz Execution from flash memory, 20MHz, 2.2V, +25°C Execution from flash memory, 8MHz, mode, 2.2V, +25°C Active Current Execution from flash memory, 8MHz, PMM1 mode, 2.2V, +25°C Execution from RAM, 8MHz, mode, 2.2V, +25°C Execution from RAM, 1MHz, mode, 2.2V, +25°C Stop-Mode Current Digital Supply Current Input High Voltage: HFIN 32KIN ISTOP(VDD) IDDIO VIH1 -40°C +25°C +85°C enabled; HFIN 14MHz; disconnected VDDIO flash Flash programming CONDITIONS 2.25 0.85 0.19 0.30 0.14 VDDIO 2.75 2.75 10.4 UNITS
Low-Power Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(VDD VDD(MIN) VDD(MAX), VDDIO 2.7V 3.6V, -40°C +85°C.) (Note
PARAMETER Input High Voltage: P6.4-P6.5 P7.0-P7.1 Input High Voltage: Other Pins Input Voltage: HFIN 32KIN Input Voltage: Other Pins Output High Voltage: P6.4-P6.5 P7.0-P7.1 Output High Voltage: Other Pins Output Voltage Other Pins Output Voltage P6.4-P6.5 P7.0-P7.1 Input Leakage Current Input Pullup Current INTERFACE Reference Voltage Bias Voltage Bias Voltage Adjustment Voltage Bias Resistor Adjustment Resistor VLCD VLCD1 VLCD2 VADJ RLCD RLADJ LRA4:LRA0 When segment driven VLCD level; VLCD ISEGxx -3µA; guaranteed design When segment driven VLCD1 level; VLCD1 ISEGxx -3µA; guaranteed design Segment Voltage VSEGxx When segment driven VLCD2 level; VLCD2 ISEGxx -3µA; guaranteed design When segment driven VADJ level; VADJ ISEGxx 3µA; guaranteed design VLCD2 0.02 VLCD2 VLCD 0.02 bias bias Guaranteed design VLCD VADJ (VLCD VADJ) VADJ (VLCD VADJ) SYMBOL VIH2 VIH3 VIL1 VIL2 VOH1 VOH2 VOL1 VOL2 IOH(MAX) 0.75mA; VLCD 2.7V IOH(MAX) 0.75mA; VDDIO =1.8V 1.0mA; VDDIO 1.8V 1.4mA; VDDIO 2.7V Internal pullup disabled Internal pullup enabled CONDITIONS VLCD 3.3V VLCD VDDIO VLCD VDDIO -100 +100 VLCD VDDIO VDDIO VDDIO UNITS
MAXQ2000
VLCD1 0.02
VLCD1
VADJ
Low-Power Microcontroller MAXQ2000
ELECTRICAL CHARACTERISTICS (continued)
(VDD VDD(MIN) VDD(MAX), VDDIO 2.7V 3.6V, -40°C +85°C.) (Note
PARAMETER EXTERNAL CLOCK SOURCE External oscillator, 2.25V External oscillator, 2.25V External-Clock Frequency fHFIN External crystal, 2.25V External crystal, 2.25V Flash programming, 2.25V Flash programming, 2.25V External-Clock Period System-Clock Frequency System-Clock Period REAL-TIME CLOCK Input Frequency JTAG/FLASH PROGRAMMING Flash Erase Time Flash Programming Time Write/Erase Cycles Data Retention TIMING Master Operating Frequency Slave Operating Frequency SCLK Output Pulse-Width High/Low SCLK Input Pulse-Width High/Low MOSI Output Hold Time after SCLK Sample Edge MOSI Output Valid Sample Edge MISO Input Valid SCLK Sample Edge Rise/Fall Setup MISO Input SCLK Sample Edge Rise/Fall Hold 1/tMCK 1/tSCK tMCH, tMCL tSCH, tSCL tMOH tMOV 50pF tMCK tMCK tMCK tSCK +25°C +25°C Mass erase Page erase 10,000 cycles years f32KIN 32kHz watch crystal 32.768 tCLCL minimum duty cycle 2.25V 2.75V 1.8V 2.75V SYMBOL CONDITIONS UNITS
tMIS
tMIH
Low-Power Microcontroller
ELECTRICAL CHARACTERISTICS (continued)
(VDD VDD(MIN) VDD(MAX), VDDIO 2.7V 3.6V, -40°C +85°C.) (Note
PARAMETER SCLK Inactive MOSI Inactive MOSI Input SCLK Sample Edge Rise/Fall Setup MOSI Input from SCLK Sample Edge Transition Hold MISO Output Valid after SCLK Shift Edge Transition SSEL Inactive SCLK Inactive SSEL Rising MISO Output Disabled after Edge Rise SYMBOL tMLH CONDITIONS tMCK UNITS
MAXQ2000
tSIS
tSIH
tSOV tSSH tSLH
3tCK
2tCK
Note Specifications -40°C guaranteed design production tested. Note Measured with 2.75V reset.
Low-Power Microcontroller MAXQ2000
Master Timing
SHIFT SSEL SAMPLE SHIFT SAMPLE
SCLK CKPOL/CKPHA
tMCK
SCLK CKPOL/CKPHA
tMCH
tMCL
tMOH tMOV MOSI MSB-1 tMLH
tMIS MISO MSB-1
tMIH
Slave Timing
SHIFT tSSE SSEL SAMPLE SHIFT SAMPLE tSSH
SCLK CKPOL/CKPHA
tSCK
SCLK CKPOL/CKPHA
tSCH
tSCL
tSIS MOSI
tSIH MSB-1
tSOV MISO MSB-1
tSLH
Low-Power Microcontroller MAXQ2000
Typical Operating Characteristics
DIGITAL SUPPLY CURRENT CLOCK FREQUENCY
IDD1 (mA) 2.75V fHFIN (MHz) +25°C +85°C -40°C
MAXQ2000 toc01
Description
TQFN NAME VDDIO VLCD Digital Supply Voltage Supply Voltage Ground Bias-Control Voltage. Highest drive voltage used with static bias. Connected external source. Bias, Voltage drive voltage used with bias. internal resistordivider sets voltage. External resistors capacitors used change voltage drive capability this pin. Bias, Voltage drive voltage used with bias. internal resistor-divider sets voltage. External resistors capacitors used change voltage drive capability this pin. Adjustment Voltage. Connect external resistor provide external control contrast. Leave disconnected internal contrast adjustment. Digital, Active-Low, Reset Input/Output. held reset when this begins executing from reset vector when released. includes pullup current source should driven open-drain, external source capable sinking excess 2mA. This driven output when internal reset condition occurs. High-Frequency Crystal Input. Connect external crystal resonator between HFXIN HFXOUT high-frequency system clock. Alternatively, HFXIN input external, high-frequency clock source when HFXOUT floating. High-Frequency Crystal Output/Input. Connect external crystal resonator between HFXIN HFXOUT high-frequency system clock. Alternatively, float HFXOUT when external, high-frequency clock source connected HFXIN pin. FUNCTION
VLCD1
VLCD2
VADJ
RESET
HFXIN
HFXOUT
Low-Power Microcontroller MAXQ2000
Description (continued)
TQFN NAME FUNCTION 32kHz Crystal Input. Connect external, 32kHz watch crystal between 32KIN 32KOUT low-frequency system clock. Alternatively, 32KIN input external, 32kHz clock source when 32KOUT floating. 32kHz Crystal Output/Input. Connect external, 32kHz watch crystal between 32KIN 32KOUT low-frequency system clock. Alternatively, float 32KOUT when external, 32kHz clock source connected 32KIN pin. General-Purpose, 8-Bit, Digital, I/O, Type-C Port; Segment-Driver Output. These port pins function both bidirectional pins segment-drive outputs. port pins defaulted input with weak pullup after reset. Enabling pin's function disables generalpurpose pin. Setting PCF1 enables pins this port disables general-purpose function pins. 56-PIN 68-PIN PORT ALTERNATE FUNCTION P1.0-P1.7; SEG8- SEG15 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
32KIN
32KOUT
General-Purpose, 8-Bit, Digital, I/O, Type-C Port; Segment-Driver Output. These port pins function both bidirectional pins segment-drive outputs. port pins defaulted input with weak pullup after reset. Enabling pin's function disables generalpurpose pin. Setting PCF2 enables pins this port disables general-purpose function pins. ALTERNATE FUNCTIONS 56-PIN 68-PIN PORT 56-PIN 68-PIN 9-12 6-13 P2.0-P2.7; SEG16- SEG23 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 SEG16 SEG17 SEG18 SEG19 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
Low-Power Microcontroller
Description (continued)
TQFN NAME FUNCTION General-Purpose, Digital, I/O, Type-D Port; Segment-Driver Output; External EdgeSelectable Interrupt. This port functions both bidirectional pins segment-drive outputs. port pins defaulted inputs with weak pullups after reset. port pads configured external interrupt pins external interrupt enabled, function associated disabled. Setting PCF3 enables pins this port disables general-purpose function pins. possible interrupt functions same port. this, interrupt enable must established prior setting PCF0 bit. Care must taken enable external interrupt while normal operational mode, this could result potentially harmful contention between controller output external source connected P3.0-P3.7; interrupt input. SEGx; ALTERNATE FUNCTIONS INT4-INT7 56-PIN 68-PIN PORT 56-PIN 68-PIN P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 SEG20/INT4 SEG21/INT5 SEG22/INT6 SEG23/INT7 SEG24 SEG25 SEG26 SEG27 SEG28/INT4 SEG29/INT5 SEG30/INT6 SEG31/INT7
MAXQ2000
13-16
14-21
Segment-Driver Output; Common-Drive Output. selection function either segment alternative common-mode signal controlled choice duty cycle (DUTY1:0). 56-PIN 17-21 22-26 SEGx; COM3- COM0 68-PIN FUNCTION 56-PIN SEG24 SEG25 SEG26 SEG27 68-PIN SEG32 SEG33 SEG34 SEG35 COM0 ALTERNATE FUNCTIONS COM3 COM2 COM1
General-Purpose, Digital, I/O, Type-D Port; Debug Port Signal; External Edge-Selectable Interrupt. Pins default JTAG POR; other functions must enabled from software. 24-27 29-32 P4.0-P4.3; TCK/TDI/ TMS/TDO; INT8, INT9 56-PIN 68-PIN PORT P4.0 P4.1 P4.2 P4.3 ALTERNATE FUNCTIONS INT8 INT9
Low-Power Microcontroller MAXQ2000
Description (continued)
TQFN NAME P5.2/RX1/ INT10 P5.3/TX1/ INT11 P5.4/SS P5.5; MOSI P5.6; SCLK FUNCTION General-Purpose, Digital, I/O, Type-D Port; Serial Port Receive; External Edge-Selectable Interrupt General-Purpose, Digital, I/O, Type-D Port; Serial Port Transmit; External Edge-Selectable Interrupt General-Purpose, Digital, I/O, Type-C Port; Active-Low, SPI, Slave-Select Input. Becomes slave-select input mode. General-Purpose, Digital, I/O, Type-C Port; SPI, Master-Out Slave-In Output. Data clocked microcontroller SCLK's falling edge into slave device SCLK's rising edge. Becomes MOSI input mode. General-Purpose, Digital, I/O, Type-C Port; SPI, Clock Output. Becomes SCLK input slave mode limited SYSCLK
General-Purpose, Digital, I/O, Type-C Port; SPI, Master-In Slave-Out Input. Data clocked P5.7/MISO slave SCLK's falling edge into microcontroller SCLK's rising edge. Becomes MISO output slave mode. P6.0/T1B/ INT12 P6.1/T1/ INT13 P6.2/T2B/ OW_OUT P6.3/T2/ OW_IN P6.4/T0B/ WKOUT0 P6.5/T0/ WKOUT1 P7.0/TX0/ INT14 P7.1/RX0/ INT15 General-Purpose, Digital, I/O, Type-D Port; Timer Alternative Output (PWM); External EdgeSelectable Interrupt General-Purpose, Digital, Type-D Port; Timer Output (PWM); External Edge-Selectable Interrupt General-Purpose, Digital, I/O, Type-D Port; Timer Alternative Output (PWM); 1-Wire Data Output General-Purpose, Digital, I/O, Type-D Port; Timer Output (PWM); 1-Wire Data Input General-Purpose, Digital, I/O, Type-C Port; Timer Alternative Output (PWM); Wakeup Output General-Purpose, Digital, I/O, Type-C Port; Timer Output (PWM); Wakeup Output General-Purpose, Digital, I/O, Type-D Port; Serial Port Transmit; External, Edge-Selectable Interrupt General-Purpose, Digital, I/O, Type-D Port; Serial Port Receive; External Edge-Selectable Interrupt
Low-Power Microcontroller
Description (continued)
TQFN NAME FUNCTION General-Purpose, Digital, I/O, Type-D Port; Segment-Driver Output; External EdgeSelectable Interrupt. This port functions both bidirectional pins segment-drive outputs. port pins defaulted input with weak pullup after reset. port pads configured external interrupt pins external interrupt enabled, function associated disabled. Setting PCF0 enables pins this port disables general-purpose function pins. possible interrupt functions same port. this, interrupt enable must established prior setting PCF0 bit. Care must taken enable external interrupt while normal operational mode, this could result potentially P0.0-P0.7; harmful contention between controller output external source connected SEG0- interrupt input. SEG7; 56-PIN 68-PIN PORT ALTERNATE FUNCTIONS INT0-INT3 P0.0 SEG0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 INT0 INT1 INT2 INT3
MAXQ2000
49-56
58-65
Exposed Paddle. Exposed paddle under side package. should left unconnected.
Low-Power Microcontroller MAXQ2000
Block Diagram
VLCD SCLK 3/4-WIRE (SPI) INTERFACE MOSI MISO WKUP WK_OUT VDDIO P5.4/SS P5.5/MOSI P5.6/SCLK P5.7/MISO
3WINT
MAXQ2000
1WINT INTERRUPT CONTROLLER T0INT T0CLK T1INT WDCLK WATCHDOG TIMER SYS_AL DAY_AL WDINT T1CLK T2INT T2CLK IOINT U1INT TIMER0 TIMER1 TIMER2
WKOUT_EN 1-WIRE INTERFACE OWOUT OWIN DRIVERS P6.4/T0/WKOUT P6.5/T0B/WKOUT P6.1/T1/INT13 P6.0/T1B/INT12 P6.3/T2/OWIN P6.2/T2B/OWOUT
TXD0 SERIAL UART1 SERIAL UART2 REGISTER FILE DPTR0 DPTR1 DPTR2 RXD0 TXD1 RXD1
P7.0/TX0/INT14 P7.1/RX0/INT15 P5.3/TX1/INT11 P5.2/RX1/INT10 SEG[28:31]/P3[4:7]/INT[4:7]
U2INT
SEG[0]:SEG32
SEG[24:27]/P3[0:3] SEG[16:23]/P2[0:7] SEG[8:15]/P1[0:7] SEG[0:3]/P0[0:3]
P4.0/TCK/INT8 P4.1/TDI/INT9 P4.2/TMS P4.3/TDO
EMULATION/ DOWNLOAD
16-BIT RISC
(64kByte) FLASH MASK MULTIPLY DISPLAY CONTROLLER/ DRIVER
SEG[4:7]/P0[4:7]/INT[0:3] VDDIO BIAS CONTROL VLCD
RESET HFXIN HFXOUT 32KIN 32KOUT 32KCLK HFCLK
SCLKDIV
SYSCLK WDDIV WDCLK
TCLKDIV
MUXES
T0CLK T1CLK T2CLK ALARMS
VLCD1
SYS_AL DAY_AL
VLCD2
32KHz
SELECT
VADJ
GNDIO SEG[32]/INT16 COM[0] COM[3:1]/SEG[33:35]
Low-Power Microcontroller
Detailed Description
following introduction primary features microcontroller. More detailed descriptions device features found data sheets, errata sheets, user's guides described later Additional Documentation section. format field, this either immediate value source register. this field represents register, lower four bits contain module specifier upper four bits contain register index that module. Bits represent destination transfer. This value always represents destination register, with lower four bits containing module specifier upper three bits containing register subindex within that module. time that necessary directly select upper registers destination, prefix register, PFX, needed supply extra destination bits. This prefix register write inserted automatically assembler requires only additional execution cycle.
MAXQ2000
MAXQ Core Architecture
MAXQ2000 low-cost, high-performance, CMOS, fully static, 16-bit RISC microcontroller with flash memory integrated 100- 132-segment controller. structured highly advanced, accumulator-based, 16-bit RISC architecture. Fetch execution operations completed cycle without pipelining, because instruction contains both code data. result streamlined million instructions-per-second (MIPS) microcontroller. highly efficient core supported 16-level hardware stack, enabling fast subroutine calling task switching. Data quickly efficiently manipulated with three internal data pointers. Multiple data pointers allow more than function access data memory without having save restore data pointers each time. data pointers automatically increment decrement following operation, eliminating need software intervention. result, application speed greatly increased.
Memory Organization
device incorporates several memory areas: 4kWords utility ROM, 32kWords flash memory program storage, 1kWord SRAM storage temporary variables, 16-level stack memory storage program return addresses general-purpose use. memory arranged default Harvard architecture, with separate address spaces program data memory. special mode allows data memory mapped into program space, permitting code execution from data memory. addition, another mode allows program memory mapped into data space, permitting code constants accessed data memory. incorporation flash memory allows devices reprogrammed, eliminating expense throwing away one-time programmable devices during development field upgrades. Flash memory password protected with 16-word key, denying access program memory unauthorized individuals. pseudo-Von Neumann memory also enabled. This places utility ROM, code, data memory into single contiguous memory map. This useful applications that require dynamic program modification unique memory configurations.
Instruction
instruction composed fixed-length, 16-bit instructions that operate registers memory locations. instruction highly orthogonal, allowing arithmetic logical operations register along with accumulator. Special-function registers control peripherals subdivided into register modules. family architecture modular, that devices modules reuse code developed existing products. architecture transport-triggered. This means that writes reads from certain register locations also cause side effects occur. These side effects form basis higher-level codes defined assembler, such ADDC, JUMP, etc. codes actually implemented MOVE instructions between certain register locations, while assembler handles encoding, which need concern programmer. 16-bit instruction word designed efficient execution. indicates format source field instruction. Bits instruction represent source transfer. Depending value
Stack Memory
16-bit-wide internal stack provides storage program return addresses general-purpose use. stack used automatically processor when CALL, RET, RETI instructions executed interrupts serviced. stack also used explicitly store retrieve data using PUSH, POP, POPI instructions.
Low-Power Microcontroller MAXQ2000
PROGRAM MEMORY FFFFh FFFFh
DATA MEMORY
STACK 8FFFh UTILITY 7FFFh
REGISTERS
SPRs
FLASH MEMORY
SFRs
03FFh SRAM
0000h
0000h
Figure Memory
Low-Power Microcontroller
reset, stack pointer, initializes stack (0Fh). CALL, PUSH, interrupt-vectoring operations increment then store value location pointed RET, RETI, POP, POPI operations retrieve value then decrement Utility utility 4kWord block internal memory that defaults starting address 8000h. utility consists subroutines that called from application software. These include: In-system programming (bootstrap loader) over JTAG UART interfaces In-circuit debug routines Test routines (internal memory tests, memory loader, etc.) User-callable routines in-application flash programming fast table lookup Following reset, execution begins utility ROM. software determines whether program execution should immediately jump location 0000h, start user-application code, special routines mentioned. Routines within utility user-accessible called subroutines application software. More information utility contents contained MAXQ Family User's Guide: MAXQ2000 Supplement. Some applications require protection against unauthorized viewing program code memory. these applications, access in-system programming, inapplication programming, in-circuit debugging functions prohibited until password been supplied. password defined words physical program memory addresses x0010h x001Fh. single password lock (PWL) implemented register. When (power-on reset default), password required access utility ROM, including in-circuit debug in-system programming routines that allow reading writing internal memory. When cleared zero, these utilities fully accessible without password. password automatically ones following mass erase. methods afford great flexibility system design well reduce life-cycle cost embedded system. These features password protected prevent unauthorized access code memory. In-System Programming internal bootstrap loader allows device reloaded over simple JTAG interface. result, software upgraded in-system, eliminating need costly hardware retrofit when updates required. Remote software uploads possible that enable physically inaccessible applications frequently updated. interface hardware JTAG connection another microcontroller, connection serial port using serial-to-JTAG converter such MAXQJTAG-001, available from Maxim Integrated Products. in-system programmability required, commercial gang programmer used mass programming. Activating JTAG interface loading test access port (TAP) with system programming instruction invokes bootstrap loader. Setting during reset through JTAG interface executes bootstrap-loader-mode program that resides utility ROM. When programming complete, bootstrap loader clear reset device, allowing device bypass utility begin execution application software. following bootstrap loader functions supported: Load Dump Verify Erase Optionally, bootstrap loader invoked application code. this mode, application software would configure bits UART communication, then jump start utility ROM. this way, bootstrap loader accessed through another UART-enabled peripheral, serial port through RS-232 transceiver such MAX232. Because bootstrap loader defaults JTAG configuration reset, UART versus JTAG selection must made from application code. result, bootstrap loader access through UART possible unprogrammed device.
MAXQ2000
Programming
flash memory microcontroller programmed different methods: in-system programming in-application programming. Both
Low-Power Microcontroller
In-Application Programming in-application programming feature allows microcontroller modify flash program memory while simultaneously executing application software. This allows on-the-fly software updates missioncritical applications that cannot afford downtime. Alternatively, allows application develop custom loader software that operate under control application software. utility contains user-accessible flash programming functions that erase program flash memory. These functions described detail user's guide supplement this device.
MAXQ2000
Register
Most functions device controlled sets registers. These registers provide working space memory operations well configuring addressing peripheral registers device. Registers divided into major types: system registers peripheral registers. common register set, also known system registers, includes ALU, accumulator registers, data pointers, interrupt vectors control, stack pointer. peripheral registers define additional functionality that included different products based MAXQ architecture. This functionality broken into discrete modules that only features required given product need included. Tables show MAXQ2000 register set.
Table System Register
REGISTER INDEX MODULE NAME (BASE SPECIFIER) (8h) CKCN WDCN (9h) A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] (Bh) (Ch) (Dh) (Eh) Offs GRXL (Fh)
Note: Names that appear italics indicate that bits register read-only. Names that appear bold indicate that register bits wide. Registers module addressable.
Table System Register Functions
REGISTER A[n] bits) bits) bits) bits) LC[0] bits) LC[1] bits) Offs bits) GR.13 GR.7 bits) GR.5 GR.15 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 GR.7 bits) DP[0] bits) DP[1] bits) GR.4 GR.3 GR.2 GR.1 GR.0 GR.15 GR.14 GR.14 GR.6 GR.13 GR.13 GR.5 GR.12 GR.12 GR.4 GR.11 GR.11 GR.3 GR.10 GR.10 GR.2 GR.9 GR.9 GR.1 GR.8 GR.8 GR.0 GR.6 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.6 GR.5 GR.5 WBS2 GR.4 GR.4 WBS1 GR.3 GR.3 WBS0 GR.2 GR.2 SDPS1 GR.1 GR.1 SDPS0 GR.0 GR.0 bits) EWDI WDIF WTRF RGSL RGMD STOP PMME CDA0 CGDS GPF1 GPF0 MOD2 MOD1 MOD0 bits)
REGISTER
CKCN
WDCN
A[n] (0.15)
LC[0]
LC[1]
Offs
GR.15
GR.14
GR.7
GR.6
GRXL
GR.7
GR.7
DP[0]
MAXQ2000
DP[1]
Low-Power Microcontroller
Low-Power Microcontroller MAXQ2000
Table System Register Reset Values
REGISTER CKCN WDCN A[n] (0.15) LC[0] LC[1] Offs GRXL REGISTER
Low-Power Microcontroller
Table Peripheral Register
REGISTER INDEX 10xh 11xh 12xh 13xh 14xh 15xh 16xh 17xh 18xh 19xh 1Axh 1Bxh 1Cxh 1Dxh 1Exh 1Fxh MODULE NAME (BASE SPECIFIER) (x0h) EIF0 EIE0 EIES0 RCNT RTSS RTSH RTSL RSSA RASH RASL (x1h) EIF1 EIE1 EIES1 (x2h) MCNT SCON0 SBUF0 SMD0 MC1R MC0R LCRA LCFG LCD16 LCD0 LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 (x3h) T2CNA0 T2H0 T2RH0 T2CH0 SPIB SCON1 SBUF1 SMD1 T2CNB0 T2V0 T2R0 T2C0 T2CFG0 SPICN SPICF SPICK ICDT0 ICDT1 ICDC ICDF ICDB ICDA ICDD (x4h) T2CNA1 T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2 T2CNB1 T2V1 T2R1 T2C1 T2CNB2 T2V2 T2R2 T2C2 T2CFG1 T2CFG2 (x5h)
MAXQ2000
Note: Names that appear italics indicate that bits register read-only. Names that appear bold indicate that register bits wide.
MAXQ2000
REGISTER bits) bits) bits) bits) bits) bits) bits) bits) bits) bits) bits) bits) RTSH bits) RTSL bits) RSSA bits) RASH bits) RASL bits) bits) bits) IE15 EX15 IE14 EX14 IE13 EX13 bits) bits) IT15 IT14 IT13 bits) bits) IT12 IT11 IT10 bits) bits) IE12 EX12 IE11 EX11 IE10 EX10 bits) bits) bits) ALSF ALDF RDYE BUSY RTSS bits) RTCE
Low-Power Microcontroller
Table Peripheral Register Functions
REGISTER
EIF0
EIE0
EIES0
RCNT
X32D
RTSS
RTSH
RTSL
RSSA
RASH
RASL
EIF1
EIE1
EIES1
Table Peripheral Register Functions (continued)
REGISTER SV67 bits) bits) bits) bits) bits) SM0/FE SBUF0 bits) bits) MC1R bits) MC0R bits) PCF3 T2OE0 T2POL0 PCF2 PCF1 DUTY1 DUTY0 FRM3 FRM2 FRM1 FRM0 LCCS LRIG LRA4 PCF0 TR2L LRA3 LCD[0.15] bits) CPRL2 T2V0.9 T2R0.9 T2C0.9 bits) ET2L T2V0.8 T2R0.8 T2V0.7 T2R0.7 T2C0.7 T2CI STBY T2R0.9 T2OE1 T2V0.6 T2R0.6 T2C0.6 DIV2 SPIC T2POL1 T2V0.5 T2R0.5 T2C0.5 DIV1 ROVR TR2L T2V0.4 T2R0.4 T2C0.4 DIV0 WCOL T2V0.3 T2R0.3 T2C0.3 T2MD bits) MODF MODFE MSSPIEN TF2L T2V0.2 T2R0.2 T2C0.2 CCF1 TCC2 T2V0.1 T2R0.1 T2C0.1 CCF0 TC2L T2V0.0 T2R0.0 T2C0.0 C/T2 SBUF1 bits) ESI1 SMOD1 FEDE1 G2EN T2V0.8 T2R0.8 T2C0.8 T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10 T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 SPIB bits) SM0/FE LRA2 LRA1 LRA0 ESI0 SMOD0 FEDE0 OPCS MSUB MMAC WKE1 WKE0 SV66 SV65 SV64 SV71 SV70 bits)
REGISTER
MCNT
SCON0
SBUF0
SMD0
MC1R
MC0R
LCRA
LCFG
LCD[0.15]
T2CNA0
T2H0
T2RH0
T2CH0
SPIB
SCON1
SBUF1
SMD1
T2CNB0
T2V0
T2V0.15 T2V0.14 T2V0.13 T2V0.12 T2V0.11 T2V0.10 T2V0.9
T2R0
T2R0.15 T2R0.14 T2R0.13 T2R0.12 T2R0.11 T2R0.10
T2C0
T2C0.15 T2C0.14 T2C0.13 T2C0.12 T2C0.11 T2C0.10 T2C0.9 T2C0.8
T2CFG0
MAXQ2000
SPICN
Low-Power Microcontroller
MAXQ2000
REGISTER ESPI1 CKR7 ICDB bits) ICDA bits) ICDD bits) T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10 T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2OE0 T2POL0 TR2L CPRL2 T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10 T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 ET2L T2V1.8 T2R1.8 T2C1.7 ET2L T2V2.8 T2R2.8 T2C2.7 T2CI T2CI T2R2.7 T2V2.7 T2V2.6 T2R2.6 T2C2.6 DIV2 DIV2 T2R2.9 T2OE1 T2C1.6 T2R1.7 T2R1.6 T2R1.5 T2C1.5 T2POL1 T2V2.5 T2R2.5 T2C2.5 DIV1 DIV1 T2V1.7 T2V1.6 T2V1.5 T2R1.9 T2OE1 T2POL1 TR2L T2V1.4 T2R1.4 T2C1.4 TR2L T2V2.4 T2R2.4 T2C2.4 DIV0 DIV0 T2V1.3 T2R1.3 T2C1.3 T2V2.3 T2R2.3 T2C2.3 T2MD T2MD TF2L T2V1.2 T2R1.2 T2C1.2 TF2L T2V2.2 T2R2.2 T2C2.2 CCF1 CCF1 T2OE0 T2POL0 TR2L CPRL2 T2V1.9 T2R1.9 T2C1.9 T2V2.9 T2R2.9 T2C2.9 TCC2 T2V1.1 T2R1.1 T2C1.1 TCC2 T2V2.1 T2R2.1 T2C2.1 CCF0 CCF0 G2EN T2V1.8 T2R1.8 T2C1.8 G2EN T2V2.8 T2R2.8 T2C2.8 TC2L T2V1.0 T2R1.0 T2C1.0 TC2L T2V2.0 T2R2.0 T2C2.0 C/T2 C/T2 PSS1 PSS0 REGE CMD3 CMD2 CMD1 CMD0 CKR6 CKR5 CKR4 CKR3 CKR2 CKR1 CKR0 CKPHA CKPOL
Low-Power Microcontroller
Table Peripheral Register Functions (continued)
REGISTER
SPICF
SPICK
ICDC
ICDF
ICDB
ICDA
ICDD
T2CNA1
T2H1
T2RH1
T2CH1
T2CNA2
T2H2
T2RH2
T2CH2
T2CNB1
T2V1
T2V1.15 T2V1.14 T2V1.13 T2V1.12 T2V1.11 T2V1.10 T2V1.9
T2R1
T2R1.15 T2R1.14 T2R1.13 T2R1.12 T2R1.11 T2R1.10
T2C1
T2C1.15 T2C1.14 T2C1.13 T2C1.12 T2C1.11 T2C1.10 T2C1.9 T2C1.8
T2CNB2
T2V2
T2V2.15 T2V2.14 T2V2.13 T2V2.12 T2V2.11 T2V2.10 T2V2.9
T2R2
T2R2.15 T2R2.14 T2R2.13 T2R2.12 T2R2.11 T2R2.10
T2C2
T2C2.15 T2C2.14 T2C2.13 T2C2.12 T2C2.11 T2C2.10 T2C2.9 T2C2.8
T2CFG1
T2CFG2
Low-Power Microcontroller
Table Peripheral Register Reset Values
REGISTER EIF0 EIE0 EIES0 RCNT RTSS RTSH RTSL RSSA RASH RASL EIF1 EIE1 EIES1 REGISTER
MAXQ2000
Low-Power Microcontroller MAXQ2000
Table Peripheral Register Reset Values (continued)
REGISTER MCNT SCON0 SBUF0 SMD0 MC1R MC0R LCRA LCFG LCD[0.15] T2CNA0 T2H0 T2RH0 T2CH0 SPIB SCON1 SBUF1 SMD1 T2CNB0 T2V0 T2R0 T2C0 T2CFG0 SPICN SPICF SPICK ICDC ICDF ICDB ICDA ICDD T2CNA1 REGISTER
Low-Power Microcontroller
Table Peripheral Register Reset Values (continued)
REGISTER T2H1 T2RH1 T2CH1 T2CNA2 T2H2 T2RH2 T2CH2 T2CNB1 T2V1 T2R1 T2C1 T2CNB2 T2V2 T2R2 T2C2 T2CFG1 T2CFG2 REGISTER
MAXQ2000
Low-Power Microcontroller MAXQ2000
System Timing
maximum versatility, MAXQ2000 generates internal system clock from five possible sources: Internal ring oscillator External high-frequency crystal ceramic resonator, using internal oscillator External high-frequency clock source External 32kHz crystal ceramic resonator, using internal oscillator External 32kHz clock source crystal warmup counter enhances operational reliability. Each time external crystal oscillation must restart, such after exiting Stop mode, device initiates crystal warmup period 65,536 oscillations. This allows time crystal amplitude frequency stabilize before using clock source. While warmup mode, device begin operation from internal ring oscillator automatically switch back crystal soon ready.
POWER-ON RESET STOP
RESET XDOG STARTUP TIMER INPUT CRYSTAL CRYSTAL XDOG COUNT RESET WATCHDOG TIMER XDOG DONE RESET WATCHDOG RESET WATCHDOG INTERRUPT
MAXQ2000
STOP GLITCH-FREE POWER-ON RESET GLITCH-FREE CLOCK DIVIDER ENABLE CLOCK GENERATION SYSTEM CLOCK
RING ENABLE
32kHz
32kHz CRYSTAL
WAKE-UP ALARM TIMERS
SELECTOR DEFAULT RING SELECT
INTERRUPT/SERIAL PORT RESET STOP
INPUT CRYSTAL MONITOR ENABLE RGMD POWER-ON RESET XDOG DONE RGSL
Figure Clock Sources
Low-Power Microcontroller
Power Management
Advanced power-management features minimize power consumption dynamically matching processing speed device required performance level. This means device operation slowed power consumption minimized during periods reduced activity. When more processing power required, microcontroller increase operating frequency. Software-selectable clock-divide operations allow flexibility, selecting whether system clock cycle oscillator cycles. performing this function software, lower power state entered without cost additional hardware. extremely power-sensitive applications, three additional low-power modes available: PMM1: divide-by-256 power-management mode (PMME CD1:0 00b) PMM2: 32kHz power-management mode (PMME CD1:0 11b) Stop mode (STOP PMM1, system clock oscillator cycles, significantly reducing power consumption while microcontroller functions reduced speed. PMM2, device even slower using 32kHz oscillator clock source. optional switchback feature allows enabled interrupt sources including external interrupts, UARTs, module quickly exit power-management modes return faster internal clock rate. Power consumption reaches minimum Stop mode. this mode, external oscillator, system clock, processing activity halted. Stop mode exited when enabled external interrupt triggered, external reset signal applied RESET pin, timeof-day alarm activated. Upon exiting Stop mode, microcontroller choose wait external highfrequency crystal complete warmup period, start execution immediately from internal ring oscillator while warmup period completes. avoid repeated interrupts from same source. Application software must ensure delay between write flag RETI instruction allow time interrupt hardware remove internal interrupt condition. Asynchronous interrupt flags require one-instruction delay synchronous interrupt flags require two-instruction delay. When enabled interrupt detected, software jumps user-programmable interrupt vector location. register defaults 0000h reset power-up, changed different address, user program must determine whether jump 0000h came from reset interrupt source. Once software control been transferred ISR, interrupt identification register (IIR) used determine system register peripheral register source interrupt. specified module then interrogated specific interrupt source software take appropriate action. Because interrupts evaluated user software, user define unique interrupt priority scheme each application. following interrupt sources available. Sources marked with asterisk available 56-pin version. Watchdog Interrupt External Interrupts (INT10*, INT11*) Time-of-Day Subsecond Alarms Serial Port Receive Transmit Interrupts Serial Port Receive Transmit Interrupts* Mode Fault, Write Collision, Receive Overrun, Transfer Complete Interrupts Timer Compare, Overflow, Capture/Compare, Overflow Interrupts Timer Compare, Overflow, Capture/Compare, Overflow Interrupts Timer Compare, Overflow, Capture/Compare, Overflow Interrupts 1-Wire Presence Detect, Transmit Buffer Empty, Transmit Shift Register Empty, Receive Buffer Full, Shift Register Full, Short, Interrupts*
MAXQ2000
Interrupts
Multiple interrupt sources available quick response internal external events. MAXQ architecture uses single interrupt vector (IV), single interrupt-service routine (ISR) design. maximum flexibility, interrupts enabled globally, individually, module. When interrupt condition occurs, individual flag set, even interrupt source disabled local, module, global level. Interrupt flags must cleared within user-interrupt routine
Reset Sources
Several reset sources provided microcontroller control. Although code execution halted reset state, high-frequency oscillator ring oscillator continue oscillate. Internal resets such poweron watchdog resets assert RESET low.
Low-Power Microcontroller MAXQ2000
Power-On Reset
internal power-on reset circuit enhances system reliability. This circuit forces device perform power-on reset whenever rising voltage VDDIO climbs above approximately 1.8V. this point following events occur: registers circuits enter their reset state flag (WDCN.7) indicate source reset ring oscillator becomes clock source Code execution begins location 8000h
Ports
microcontroller uses type type bidirectional ports described MAXQ Family User's Guide. three port types allows maximum flexibility when interfacing external peripherals. Each port eight independent, general-purpose pins three configure/control registers. Many pins support alternate functions such timers interrupts, which enabled, controlled, monitored dedicated peripheral registers. Using alternate function automatically converts that function. Type-C port pins have Schmitt Trigger receivers full CMOS output drivers, support alternate functions. either tri-stated weak pullup when defined input, dependent state corresponding output register. Type-D port pins have Schmitt Trigger receivers full CMOS output drivers, support alternate functions. either tri-stated weak pullup when defined input, dependent state corresponding output register. type-D pins also have interrupt capability.
Watchdog Timer Reset
watchdog timer functions described MAXQ Family User's Guide. Execution resumes location 8000h following watchdog timer reset.
External System Reset
Asserting external RESET causes device enter reset state. external reset functions described MAXQ Family User's Guide. Execution resumes location 8000h after RESET released.
VDDIO
WEAK
PD.x DIRECTION
VDDIO
ENABLE
PO.x OUTPUT
MAXQ2000
PIN.x
PI.x INPUT
FLAG
INTERRUPT FLAG
DETECT CIRCUIT
EIES.x TYPE-D PORT ONLY
Figure Type-C/D Port Schematic
Low-Power Microcontroller
High-Speed Hardware Multiplier
hardware multiplier module performs high-speed multiply, square, accumulate operations, complete 16-bit 16-bit multiply-and-accumulate operation single cycle. hardware multiplier consists 16-bit parallel-load operand registers (MA, MB), accumulator that formed three 16-bit parallel registers (MC2, MC1, MC0), status/control register (MCNT). Loading registers automatically initiate operation, saving time repetitive calculations. accumulate function hardware multiplier essential element digital filtering, signal processing, control systems. hardware multiplier module supports following operations: Multiply unsigned bit) Multiply signed bit) Multiply-Accumulate unsigned bit) Multiply-Accumulate signed bit) Square unsigned bit) Square signed bit) Square-Accumulate unsigned bit) internal crystal oscillator clocks using integrated load capacitors, give best performance when mated with 32.768kHz crystal rated load. external load capacitors required. Higher accuracy obtained supplying external clock source RTC. frequency accuracy crystal-based oscillator circuit dependent upon crystal accuracy, match between crystal oscillator capacitor load, ambient temperature, etc. error 20ppm equivalent approximately minute month.
MAXQ2000
Programmable Timers
microcontroller incorporates three 16-bit programmable instances Timer peripheral, denoted TR2A, TR2B, TR2C. These timers used functions, allowing precise control internal external events. Timer supports optional single-shot, external gating, polarity control options.
Timer
Timer peripheral includes following: 16-bit autoreload timer/counter 16-bit capture 16-bit counter 8-bit capture 8-bit timer 8-bit counter 8-bit timer
Square-Accumulate signed bit)
Real-Time Clock
binary real-time clock keeps time absolute seconds with 1/256-second resolution. 32-bit second counter count approximately years translated calendar format application software. time-of-day alarm independent subsecond alarm cause interrupt, wake device from Stop mode. independent subsecond alarm runs from same RTC, allows application perform periodic interrupts ones with granularity approximately 3.9ms. This creates additional timer that used measure long periods without performance degradations. Traditionally, long time periods have been measured using multiple interrupts from shorter programmable timers. Each timer interrupt required servicing, with each accompanying interruption slowing system operation. using subsecond timer long-period timer, only interrupt needed, eliminating performance associated with using shorter timer.
Watchdog Timer
internal watchdog timer greatly increases system reliability. timer resets device software execution disturbed. watchdog timer free-running counter designed periodically reset application software. software operating correctly, counter will periodically reset never reach maximum count. However, software operation interrupted, timer does reset, triggering system reset optionally watchdog timer interrupt. This protects system against electrical noise electrostatic discharge (ESD) upsets that could cause uncontrolled processor operation. internal watchdog timer upgrade older designs with external watchdog devices, reducing system cost simultaneously increasing reliability.
Low-Power Microcontroller
watchdog timer controlled through bits WDCN register. timeout period four programmable intervals ranging from system clocks default mode, allowing flexibility support different types applications. interrupt occurs system clocks before reset, allowing system execute interrupt place system known, safe state before device performs total system reset. 16MHz, watchdog timeout periods programmed from 256µs 33.5s, depending system clock mode.
MAXQ2000
1-Wire Master
MAXQ2000-RAX/-RAX+ includes Dallas Semiconductor 1-Wire master, which communicates other 1-Wire peripherals, including iButton® products, through simple bidirectional signaling scheme over single electrical connection. master provides complete control 1-Wire transmit receive activities, generates timing control sequences 1-Wire bus. Communication between master achieved through read/write access 1-Wire master address (OWA) 1-Wire master data (OWD) peripheral registers. Detailed operation 1-Wire described Book iButton Standards (www.maxim-ic.com/ iButtonbook).
Serial Peripherals
microcontroller incorporates several common serial-peripheral interfaces interconnection with popular external devices. Multiple formats provide maximum flexibility lower cost when designing system.
Serial-Peripheral Interface (SPI) Module
port common, high-speed, synchronous peripheral interface that shifts stream variable length data rate between microcontroller other peripheral devices. used communicate with other microcontrollers, serial shift registers, display drivers. Multiple master slave modes permit communication with multiple devices same system. Programmable clock frequency, character lengths, polarity, error handling enhance usefulness peripheral. maximum baud rate interface system clock master mode operation system clock slave mode operation.
UARTs
Serial interfacing provided through (-RBX/-RBX+) (-RAX/-RAX+) 8051-style universal synchronous/asynchronous receiver/transmitters. UART allows device conveniently communicate with other RS-232 interface-enabled devices, well serial modems when paired with external RS232 line driver/receiver. dual independent UARTs communicate simultaneously different baud rates with separate peripherals. UART detect framing errors indicate condition through user-accessible software bit. time base serial ports derived from either division system clock dedicated baud clock generator. following table summarizes operating characteristics well maximum baud rate each mode:
MODE Mode Mode Mode Mode
TYPE Synchronous Asynchronous Asynchronous Asynchronous
START BITS
DATA BITS
STOP
BAUD RATE 16MHz 4Mbps 500kbps 500kbps 500kbps
iButton registered trademark Dallas Semiconductor Corp.
Low-Power Microcontroller
In-Circuit Debug
Embedded debugging capability available through JTAG-compatible Test Access Port. Embedded debug hardware embedded firmware provide in-circuit debugging capability user application, eliminating need expensive in-circuit emulator. Figure shows block diagram in-circuit debugger. in-circuit debug features include: hardware debug engine, registers able breakpoints register, code, data accesses, debug service routines stored utility ROM. embedded hardware debug engine independent hardware block microcontroller. debug engine monitor internal activities interact with selected internal registers while executing user code. Collectively, hardware software features allow basic modes in-circuit debugging: Background mode allows host configure in-circuit debugger while continues execute application software full speed. Debug mode invoked from background mode. Debug mode allows debug engine take control CPU, providing read/write access internal registers memory, single-step trace operation.
Controller
MAXQ2000 microcontroller incorporates controller that interfaces common low-voltage displays. incorporating controller into microcontroller, design requires only glass rather than considerably more expensive module. Every character glass composed more segments, each which activated selecting appropriate segment common signal. microcontroller multiplex combinations segment (SEG0-SEG32) outputs four common signal outputs (COM0-COM3). Unused segment outputs used general-purpose port pins. segments easily addressed writing dedicated display memory. Once controller settings display memory have been initialized, 17-byte display memory periodically scanned, segment common signals generated automatically selected display frequency. additional processor overhead required while controller running. Unused display memory used general-purpose storage. design further simplified cost-reduced inclusion software-adjustable internal voltage dividers control display contrast, using either VDDIO external voltage. desired, contrast also controlled with external resistance. features controller include following: Automatic segment common-drive signal generation Four display modes supported: Static (COM0) duty multiplexed with bias voltages (COM0, COM1) duty multiplexed with bias voltages (COM0, COM1, COM2) duty multiplexed with bias voltages (COM0, COM1, COM2, COM3) segment outputs four common-signal outputs bytes (136 bits) display memory Flexible clock source, selectable from 32kHz HFClk Adjustable frame frequency Internal voltage-divider resistors eliminate requirement external components Internal adjustable resistor allows contrast adjustment without external components
MAXQ2000
MAXQ2000
DEBUG SERVICE ROUTINES (UTILITY ROM)
DEBUG ENGINE CONTROLLER CONTROL BREAKPOINT ADDRESS DATA
Figure In-Circuit Debugger
Low-Power Microcontroller MAXQ2000
Flexibility external resistors adjust drive voltages current capacity simple LCD-segmented glass interface example demonstrates minimal hardware required interface MAXQ2000 microcontroller. two-character controlled, with each character containing seven segments plus decimal point. controller configured duty cycle operation, meaning active segment controlled using combination segment signals, COM0 COM1 signals used select active display. reduces component count board space, critical factors design portable systems. MAXQ2000 ideally suited applications such medical instrumentation, portable blood glucose equipment, data collection devices. blood glucose measurement, microcontroller integrates interface that directly connects with analog front ends measuring test strips.
Additional Documentation
Designers must have four documents fully features this device. This data sheet contains descriptions, feature overviews, electrical specifications. Errata sheets contain deviations from published specifications. user's guides offer detailed information about device features operation. following documents downloaded from MAXQ2000 errata sheet, available www.maxim-ic.com/errata. MAXQ Family User's Guide, which contains detailed information core features operation, including programming. MAXQ Family User's Guide: MAXQ2000 Supplement, which contains detailed information features specific MAXQ2000.
Applications
low-power, high-performance RISC architecture MAXQ2000 makes excellent many portable battery-powered applications that require cost-effective computing. high-throughput core complemented 16-bit hardware multiplier-accumulator, allowing implementation sophisticated computational algorithms. Applications benefit from wide range peripheral interfaces, allowing microcontroller communicate with many external devices. With integrated support segments, applications support complex user interfaces. Displays driven directly with additional external hardware required. Contrast adjusted using built-in, adjustable resistor. simplified architecture
MAXQ2000
SEG0:7
SEG0
SEG4
SEG1
SEG5
SEG2 SEG3 COM0 COM1 CONNECTED DARK GREY SEGMENTS CONNECTED LIGHT GREY SEGMENTS
SEG6 SEG7
Figure Two-Character, Duty, Interface Example
Low-Power Microcontroller
Development Technical Support
variety highly versatile, affordably priced development tools this microcontroller available from Maxim/ Dallas Semiconductor third-party suppliers, including: Compilers In-circuit emulators Integrated development environments (IDEs) JTAG-to-serial converters programming debugging partial list development tool vendors found website Technical support available through email maxq.support@dalsemi.com.
MAXQ2000
Configurations
SEG7/P0.7/INT3 SEG6/P0.6/INT2 SEG5/P0.5/INT1 SEG4/P0.4/INT0 P7.1/RX0/INT15 P7.0/TX0/INT14
SEG10/P1.2
VIEW
SEG9/P1.1
SEG8/P1.0
SEG3/P0.3
SEG2/P0.2
SEG1/P0.1
SEG0/P0.0
VLCD2
VLCD1
SEG11/P1.3 SEG12/P1.4 SEG13/P1.5 SEG14/P1.6 SEG15/P1.7 SEG16/P2.0 SEG17/P2.1 SEG18/P2.2 SEG19/P2.3 SEG20/P2.4 SEG21/P2.5 SEG22/P2.6 SEG23/P2.7 SEG24/P3.0 SEG25/P3.1 SEG26/P3.2 SEG27/P3.3
VLCD
VADJ
HFXIN HFXOUT P6.5/T0/WKOUT1 P6.4/T0B/WKOUT0 P6.3/T2/OW_IN P6.2/T2B/OW_OUT P6.1/T1/INT13 P6.0/T1B/INT12 P5.7/MISO P5.6/SCLK P5.5/MOSI P5.4/SS P5.3/TX1/INT11 P5.2/RX1/INT10 32KOUT
MAXQ2000
(132-SEGMENT LCD)
32KIN
SEG28/P3.4/INT4
SEG29/P3.5/INT5
SEG30/P3.6/INT6
SEG31/P3.7/INT7
P4.0/TCK/INT8
P4.1/TDI/INT9
SEG33/COM3
SEG34/COM2
SEG35/COM1
SEG32
P4.2/TMS
P4.3/TDO
RESET
COM0
VDDIO
Low-Power Microcontroller MAXQ2000
Configurations (continued)
P7.1/RXO/INT15
VIEW
SEG8/P1.0 SEG9/P1.1 SEG10/P1.2 SEG11/P1.3 SEG12/P1.4 SEG13/P1.5 SEG14/P1.6 SEG15/P1.7 SEG16/P2.4 SEG17/P2.5 SEG18/P2.6 SEG19/P2.7 SEG20/P3.4/INT4 SEG21/P3.5/INT5
VADJ
P7.0/TXO/INT14
SEG7/P0.7/INT3
SEG6/P0.6/INT2
SEG5/P0.5/INT1
SEG4/P0.4/INT0
SEG3/P0.3
SEG2/P0.2
SEG1/P0.1
SEG0/P0.0
VLCD2
VLCD1
VLCD
HFXIN HFXOUT P6.5/T0/WKOUT1 P6.4/T0B/WKOUT0 P6.1/T1/INT13 P6.0/T1B/INT12 P5.7/MISO P5.6/SCLK P5.5/MOSI P5.4/SS 32KOUT 32KIN
MAXQ2000
(100-SEGMENT LCD)
RESET
SEG22/P3.6/INT6
SEG23/P3.7/INT7
P4.0/TCK/INT8
P4.1/TDI/INT9
P4.2/TMS
SEG25/COM3
SEG26/COM2
SEG27/COM1
TQFN
P4.3/TDO
SEG24
COM0
VDDIO
Ordering Information
PART MAXQ2000-RAX MAXQ2000-RAX+ MAXQ2000-RBX MAXQ2000-RBX+ TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PROGRAM MEMORY 32kWord Flash 32kWord Flash 32kWord Flash 32kWord Flash DATA MEMORY 1kWord SRAM 1kWord SRAM 1kWord SRAM 1kWord SRAM EXTERNAL SEGMENTS INTERRUPTS UARTS PINPACKAGE TQFN TQFN
+Denotes Pb-free/RoHS-compliant package.
Low-Power Microcontroller
Typical Operating Circuit
MAXQ2000
GLUCOSE MICROCONTROLLER RS-232 SERIAL PORT PC_RX +3.3V +3.3V RS-232 PC_TX CHIP INTERFACE CABLE SERIAL DATA DOWNLOAD CONNECTOR VLCD (+3.3V) P7.1RX0/INT15 P7.0TX0/INT14 1-WIRE INTERFACE VLCD (+3.3V) JTAG DOWNLOAD/ DEBUG CONNECTOR P4.3/TDO P4.2/TMS P4.1/TDI/INT9 P4.0/TCK/INT8 GNDIO VDDIO P6.1/T1/INT13 PIEZO BUZZER P6.0/T1B/INT12 GNDIO VDDIO VDDIO 200k 200k STRIP INSERTED SEG31/P3.7/INT7 SEG29/P3.5/INT5 GNDIO VLCD (+3.3V) VLCD GNDIO P6.5/T0/WKOUT TIMER 32KCLK VDDIO DIFFERENTIALLY DRIVEN ±6.6V -2kHz 10kHz 1678 VBATT AVDD LITHIUM COIN CELL (+1.8V +3.6V) DVDD JTAG 4-WIRE INTERFACE VDDIO P5.5/MOSI P5.7/MISO P5.6/SCLK P5.4/SS GNDIO DOUT SCLK UPIO2 UPIO3 UPIO4 UART1 VDDIO P6.2/T2B/OW_OUT P6.3/T2/OW_IN CPOUT 1-WIRE EEPROM DATA PORT CONNECTOR 1-WIRE EPROM DATA METER PARAMETERS PATIENT DATA STORAGE TEST STRIP PARAMETERS
MAXQ2000
MAX1358 MAX1359 MAX1360
OUTA TEST STRIP PORT CONNECTOR DACA OUTB TEST STRIP
AGND DGND
UPI01
WAKEUP
REGULATED +3.3V
CPOUT
DACB SNO1
VLCD1
CHARGEPUMP DOUBLER
SCM1 SNC1 OUT1 INM1 LINEAR INP1
SEGMENT GLASS
SEG[28:5] SEG[0:3] SEG[32] COM[3:1]/SEG[35:33] COM[0]
VLCD2 DRIVERS
CFREG
STRIP INSERTED
VADJ DVDD
NOTE THAT SEGMENTS DRIVEN OTHER MUXED FUNCTIONS USED 32/64kB FLASH/ MASK SYSTEM TIMERS/ ALARMS
SNO2 GNDIO 32KIN 32.768kHz WATCH XTAL 1-5MHz AIN1 AIN2 SCM2 SNC2 REMOTE TEMPERATURE MEASUREMENT DIODE
32KOUT 32KIN HFXIN VDDIO 16-BIT RISC MICRO GNDIO 200k 200k 200k HFXOUT
32KOUT
32kHz MICRO CLOCK (OPTIONAL) CLK32K HIGH-FREQUENCY MICRO CLOCK
RESET SEG4/P0.4/INTO MAX1358/9/60 INTERRUPT RESET
SEG30/ P3.6/INT6 P5.3/ TX1/INT11 P5.2/ DOWN RX1/INT10
WATCHDOG TIMER
GLUCOSE METER CIRCUIT BOARD
Low-Power Microcontroller MAXQ2000
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
PACKAGE OUTLINE, QFN, 10x10x0.9 21-0122
QFN.EPS
Low-Power Microcontroller
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
MAXQ2000
PACKAGE OUTLINE, QFN, 10x10x0.9 21-0122
Low-Power Microcontroller MAXQ2000
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
PACKAGE OUTLINE THIN QFN, 8x8x0.8mm
21-0135
THIN QFN.EPS
Low-Power Microcontroller
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information,
MAXQ2000
PACKAGE OUTLINE THIN QFN, 8x8x0.8mm
21-0135
Low-Power Microcontroller MAXQ2000
Revision History
10/04: 10/04: 12/04: product release (QFN package variant). product release (TQFN package variant). Under Peripheral Features, corrected accumulator show bits (not bits); table, added Active Current line 2.2V, 20MHz flash operation; Package Information, replaced package drawing 56-pin package; VIH2(MIN) changed from 0.75; updated VIH, VIL, VOH, data match GBD/FTEC data. Added lead-free part numbers Ordering Information table. table under Segment Voltage, clarified wording VADJ spec VADJ(MIN) VADJ VADJ(MIN) 0.1V; changed ISEGxx 3µA. Clarified that flash memory write/erase cycles data retention specifications +25°C. Clarified VIH1/VIH3 specifications, matching presented values test program values (0.8 VDDIO); clarified VIH2 specification, matching presented values test program values (0.8 VLCD); clarified VIL2 specification, matching presented values test program values (0.2 VDDIO). These changes affect testing operation device. Corrected typo (Pin Configuration) from P4/SS P5.4/SS. 3/06: Corrected Pb-free package number denotations. Should MAXQ2000-RAX+ MAXQ2000-RBX+.
6/05:
10/05: 1/06:
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2006 Maxim Integrated Products Printed registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.

Low-Power Microcontroller High-Performance, Low-Power, 16-Bit RIS

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