IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density CM

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IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density CM

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COM'L: -7.5/10/12/15/20
IND: -10/12/14/18/24
MACH211SP-7/10/12/15/20
High-Density CMOS Programmable Logic
DISTINCTIVE CHARACTERISTICS
JTAG-Compatible, in-system programming Pins Macrocells Commercial Industrial fCNT Bus-FriendlyInputs I/Os Peripheral Component Interconnect (PCI) compliant (-7/-10) Programmable power-down mode Outputs Flip-flops; clock choices "PAL26V16" blocks with buried macrocells Improved routing over MACH210
IN-SYSTEM PROGRAMMING
In-system programming allows MACH211SP programmed while soldered onto system board. Programming MACH211SP in-system yields numerous benefits stages development: prototyping, manufacturing, field. Since insertion into programmer isn't needed, multiple handling steps resulting bent leads eliminated. design modified in-system design changes debugging while prototyping, programming boards production, field upgrades. MACH211SP offers advantages available other CPLD architectures with in-system programming. MACH devices have extensive routing resources pin-out retention; design changes resulting pin-out changes other CPLDs cancel advantages in-system programming. MACH211SP employed JTAG (IEEE 1149.1) compliant chain.
GENERAL DESCRIPTION
MACH211SP member AMD's CMOS Performance Plus MACH® device family. This device approximately times logic macrocell capability popular PAL22V10 without loss speed. MACH211SP consists four PAL® blocks interconnected programmable switch matrix. four blocks essentially "PAL26V16" structures complete with product-term arrays programmable macrocells, which programmed high speed power, buried macrocells. switch matrix connects blocks each other input pins, providing high degree connectivity between fully-connected blocks. This allows designs placed routed efficiently. MACH211SP kinds macrocell: output buried. MACH211SP output macrocell provides registered, latched, combinatorial outputs with programmable polarity. registered configuration chosen, register configured D-type T-type help reduce number product terms. register type decision made designer software. output macrocells connected cell. buried macrocell desired, internal feedback path from macrocell used, which frees input. MACH211SP dedicated buried macrocells which, addition capabilities output macrocell, also provide input registers latches synchronizing signals reducing setup time requirements. MACH211SP enhanced version MACH211, adding JTAG-compatible in-system programming feature.
Publication# 20405 Rev: Amendment/0 Issue Date: February 1996
BLOCK DIAGRAM
I/O0-I/O7 Cells Macrocells Macrocells Cells Macrocells I/O8-I/O15 Macrocells
Logic Array Logic Allocator Switch Matrix Logic Array Logic Allocator Macrocells Cells Macrocells
Logic Array Logic Allocator
Logic Array Logic Allocator Macrocells Cells Macrocells
I/O24-I/O31
I/O16-I/O23
CLK0/I0 CLK1/I1
20405B-1
MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP View 44-Pin PLCC
I/O31
I/O30
I/O29
I/O5 I/O6 I/O7 CLK0/I0 I/O8 I/O9 I/O10 I/O11
I/O27 I/O26 I/O25 I/O24 CLK1/I1 I/O23 I/O22 I/O21
I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20
I/O28
I/O4
I/O3
I/O2
I/O1
I/O0
20405B-2
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Test Data Test Clock Test Mode Select Test Data
Supply Voltage
MACH211SP-7/10/12/15/20
CONNECTION DIAGRAM MACH211SP View 44-Pin TQFP
I/O5 I/O6 I/O7 CLK0/I0 I/O8 I/O9 I/O10 I/O11
I/O4 I/O3 I/O2 I/O1 I/O0 I/O31 I/O30 I/O29 I/O28
I/O27 I/O26 I/O25 I/O24 CLK1/I1 I/O23 I/O22 I/O21
I/O12 I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 I/O19 I/O20
20405B-3
DESIGNATIONS
CLK/I Clock Input Ground Input Input/Output Supply Voltage Test Data Test Clock Test Mode Select Test Data
MACH211SP-7/10/12/15/20
ORDERING INFORMATION Commercial Products
programmable logic products commercial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing
DEVICE NUMBER Macrocells, Pins, Power-Down mode, Bus-Friendly Inputs I/Os PRODUCT DESIGNATION In-system Programmable
OPERATING CONDITIONS Commercial (0°C +70°C)
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044) 44-Pin Thin Quad Flat Pack (PQT044) SPEED
Valid Combinations MACH211SP-7 MACH211SP-10 MACH211SP-12 MACH211SP-15 MACH211SP-20
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH211SP-7/10/12/15/20 (Com'l)
ORDERING INFORMATION Industrial Products
programmable logic products industrial applications available with several ordering options. order number (Valid Combination) formed combination
MACH
FAMILY TYPE MACH Macro Array CMOS High-Speed
OPTIONAL PROCESSING Blank Standard Processing
DEVICE NUMBER Macrocells, Pins, Power-Down mode, Bus-Friendly Inputs I/Os PRODUCT DESIGNATION In-system Programmable
OPERATING CONDITIONS Industrial (-40°C +85°C)
PACKAGE TYPE 44-Pin Plastic Leaded Chip Carrier 044)
SPEED 14.5
Valid Combinations MACH211SP-10 MACH211SP-12 MACH211SP-14 MACH211SP-18 MACH211SP-24
Valid Combinations Valid Combinations table lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
MACH211SP-10/12/14/18/24 (Ind)
FUNCTIONAL DESCRIPTION
MACH211SP consists four blocks connected switch matrix. There pins feeding switch matrix. These signals distributed four blocks efficient design implementation. There clock pins that also used dedicated inputs.
Output
Table
Macrocell Buried
Logic Allocation
Available Clusters
C10, C10, C11, C10, C11, C12, C11, C12, C13, C12, C13, C14, C13, C14, C14,
Blocks
Each block MACH211SP (Figure contains 64-product-term logic array, logic allocator, output macrocells, buried macrocells, cells. switch matrix feeds each block with inputs. This makes block look effectively like independent "PAL26V16" with buried macrocells. addition logic product terms, output enable product terms, asynchronous reset product term, asynchronous preset product term provided. output enable product terms chosen within each cell block. flip-flops within block initialized together.
Switch Matrix
MACH211SP switch matrix inputs feedback signals from blocks. Each block provides internal feedback signals feedback signals. switch matrix distributes these signals back blocks efficient manner that also provides high performance. design software automatically configures switch matrix when fitting design into device.
feedback whether configured with without flip-flop. registers configured D-type T-type, allowing product-term optimization. flip-flops individually select clock/ gate pins, which also available data inputs. registers clocked LOW-to-HIGH transition clock signal. latch holds data when gate input HIGH, transparent when gate input LOW. flip-flops also asynchronously initialized with common asynchronous reset preset product terms. buried macrocells same output macrocells they used generating logic. that case, only thing that distinguishes them from output macrocells fact that there cell connection, signal only used internally. buried macrocell also configured input register latch.
Product-term Array
MACH211SP product-term array consists product terms logic use, special-purpose product terms. special-purpose product terms provide programmable output enable; provides asynchronous reset, provides asynchronous preset.
Logic Allocator
logic allocator MACH211SP takes logic product terms allocates them macrocells needed. Each macrocell driven product terms. design software automatically configures logic allocator when fitting design into device. Table illustrates which product term clusters available each macrocell within block. Refer Figure cluster macrocell numbers.
Cell
cell MACH211SP consists three-state output buffer. three-state buffer configured three ways: always enabled, always disabled, controlled product term. product term control chosen, product terms used provide control. product terms that available common cells block.
Macrocell
MACH211SP types macrocell: output buried. output macrocells configured either registered, latched, combinatorial, with programmable polarity. macrocell provides internal
MACH211SP-7/10/12/15/20
These choices make possible macrocell output, input, bidirectional pin, three-state output driving bus.
should programmed. configuration file discussed detail MACHPRO software manual. MACH211SP devices tristate outputs during programming. They have security which inhibits program verify. This allows user protect proprietary patterns designs. Program verification MACH device involves reading back programmed pattern comparing with original JEDEC file. method program verification performed MACH devices permits verification device time.
Power-Down Mode
MACH211SP features programmable low-power mode which individual signal paths programmed power. These low-power speed paths will slightly slower than non-low-power paths. This feature allows speed critical paths maximum frequency while rest paths operate low-power mode, resulting power savings 75%. signals block low-power, then total power reduced further.
In-System Programming
Programming process where MACH devices loaded with pattern defined JEDEC file obtained from MACHXL software third-party software. Programming accomplished through four JTAG pins: Test Mode Select (TMS), Test Clock (TCK), Test Data (TDI), Test Data (TDO). MACH211SP employed JTAG (IEEE 1149.1) compliant chain. While MACH211SP fully JTAG compatible, supports BYPASS instruction, EXTEST SAMPLE/PRELOAD instructions. MACH211SP programmed across commercial temperature range. Programming MACH device after been placed circuit board easily accomplished. Programming initiated placing device into programming mode, using MACHPRO programming software provided AMD. device bulk erased JEDEC file then loaded. After data transferred into device, PROGRAM instruction loaded. Further programming details found application note, "Advanced In-circuit Programming Guidelines."
Accidental Programming Erasure Protection
virtually impossible program erase MACH device inadvertently. following conditions must before programming actually takes place: device must password-protected program mode programming bulk erase instruction must instruction register above conditions met, programming circuitry cannot activated. ensure that year device data retention guarantee applies, program/erase cycle limit should exceeded.
Bus-Friendly Inputs I/Os
MACH211SP inputs I/Os include inverters series which loop back input. This double inversion reinforces state input pulls voltage away from input threshold voltage. illustration this configuration, please turn Input/Output Equivalent Schematics section.
On-Board Programming Options
Since MACHPRO software performs these steps automatically, following programming options published reference. configuration file, which also known chain file, defines MACH device JTAG chain. file contains information concerning which JEDEC file placed into which device, state which outputs should placed, whether security fuses
Compliance
MACH211SP-7/10 fully compliant with Local Specification published Special Interest Group. MACH211SP-7/10's predictable timing ensures compliance with specifications independent design. other hand, CPLD FPGA architectures without predictable timing, compliance dependent upon routing product term distribution.
MACH211SP-7/10/12/15/20
Output Enable Output Enable Asynchronous Reset Asynchronous Preset
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Logic Allocator
Cell
Output Macro Cell
Buried Macro Cell
Cell
Output Macro Cell
Switch Matrix
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Output Macro Cell
Cell
Buried Macro Cell
Cell
Output Macro Cell
Buried Macro Cell
20405B-4
Figure
MACH211SP Block
MACH211SP-7/10/12/15/20
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage with Respect Ground. -0.5 +7.0 Input Voltage .-0.5 Output Voltage .-0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free Air. .0°C +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH211SP-7/10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock (Note Register Data Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL tSLL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate 1/(tWL tWH) T-type 166.7 D-type Input Register Clock Output Register Setup T-type Input Register Clock Width HIGH 166.7 D-type T-type Unit
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output
MACH211SP-7/10 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tIGS tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Parameter Description Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note 12.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH211SP-7/10 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage with Respect Ground. -0.5 +7.0 Input Voltage .-0.5 Output Voltage .-0.5 Static Discharge Voltage 2001 Latchup Current 70°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free Air. .0°C +70°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Current Input Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH211SP-12/15/20 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time 1/(tWL tWH) T-type 66.7 62.5 83.3 76.9 83.3 83.3 83.3 62.5 47.6 66.6 62.5 83.3 38.5 47.6 62.5 D-type T-type Unit
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register D-type Setup T-type Input Register Clock Width HIGH 1/(tWICL tWICH)
MACH211SP-12/15/20 (Com'l)
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note (continued)
Parameter Symbol tIGO tIGOL tSLL tIGS tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Parameter Description Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH211SP-12/15/20 (Com'l)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage with Respect Ground. -0.5 +7.0 Input Voltage .-0.5 Output Voltage .-0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C).
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Temperature (TA) Operating Free Air. .-40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH211SP-10/12 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) Parameter Description Input, I/O, Feedback Combinatorial Output (Note D-type Setup Time from Input, I/O, Feedback Clock T-type Register Data Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO tIGOL Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output Input Latch Gate Output Through Transparent Output Latch 1/(tWL tWH) T-type D-type Input Register Clock Output Register Setup T-type Input Register Clock Width HIGH 1/(tWICL tWICH) 19.5 14.5 72.5 Unit
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output
MACH211SP-10/12 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note (continued)
Parameter Symbol tSLL tIGS tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Parameter Description Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note 10.5 13.5 19.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH211SP-10/12 (Ind)
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied. -55°C +125°C Supply Voltage with Respect Ground. -0.5 +7.0 Input Voltage .-0.5 Output Voltage .-0.5 Static Discharge Voltage 2001 Latchup Current -40°C 85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability. Programming conditions differ.
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) Operating Free Air. .-40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current (Static) Supply Current (Active) Test Conditions -3.2 Min, Min, Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note 5.25 (Note (Note VOUT 5.25 (Note VOUT (Note VOUT (Notes 25°C, (Note 25°C, (Note -160 Unit
Notes: These absolute values with respect device ground overshoots system and/or tester noise included. leakage worst case IOZL IOZH). more than output should shorted time. Duration short-circuit should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter measured low-power mode with 16-bit up/down counter pattern. This pattern programmed each block capable being loaded, enabled reset. This parameter 100% tested, evaluated initial characterization time design modified where capacitance affected.
MACH211SP-14/18/24 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance VOUT Test Conditions 25°C Unit
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol External Feedback fMAX Maximum Frequency (Note 1/(tS tCO) Parameter Description Input, I/O, Feedback Combinatorial Output (Note Setup Time from Input, I/O, Feedback Clock Register Data Hold Time Clock Output (Note Clock Width HIGH D-type T-type D-type Internal Feedback (fCNT) Feedback tGWL tPDL tSIR tHIR tICO tICS tWICL tWICH fMAXIR tSIL tHIL tIGO Maximum Input Register Frequency Input Latch Setup Time Input Latch Hold Time Input Latch Gate Combinatorial Output 1/(tWL tWH) T-type 61.5 66.5 14.5 66.5 20.5 19.5 66.5 25.5 20.5 66.5 13.5 26.5 30.5 34.5 14.5 D-type T-type 14.5 13.5 14.5 Unit
Setup Time from Input, I/O, Feedback Gate Latch Data Hold Time Gate Output Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latch Input Register Setup Time Input Register Hold Time Input Register Clock Combinatorial Output Input Register Clock Output Register D-type Setup T-type Input Register Clock Width HIGH 1/(tWICL tWICH)
MACH211SP-14/18/24 (Ind)
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note (continued)
Parameter Symbol tIGOL tSLL tIGS tWIGL tPDLL tARW tARR tAPW tAPR tLPS tLPCO tLPEA Parameter Description Input Latch Gate Output Through Transparent Output Latch Setup Time from Input, I/O, Feedback Through Transparent Input Latch Output Latch Gate Input Latch Gate Output Latch Setup Input Latch Gate Width Input, I/O, Feedback Output Through Transparent Input Output Latches Asynchronous Reset Registered Latched Output Asynchronous Reset Width (Note Asynchronous Reset Recovery Time (Note Asynchronous Preset Registered Latched Output Asynchronous Preset Width (Note Asynchronous Preset Recovery Time (Note Input, I/O, Feedback Output Enable (Note Input, I/O, Feedback Output Disable (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note Increase Powered-down Macrocell (Note 14.5 14.5 14.5 14.5 19.5 19.5 19.5 14.5 19.5 26.5 25.5 32.5 Unit
Notes: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected. Switching Test Circuit test conditions. signal powered-down, this parameter must added respective high-speed parameter.
MACH211SP-14/18/24 (Ind)
TYPICAL CHARACTERISTICS 25°C
High Speed
(mA)
Power
Frequency (MHz)
20405B-5
selected "typical" pattern 16-bit up/down counter. This pattern programmed each block capable being loaded, enabled, reset. Maximum frequency shown uses internal feedback D-type register.
MACH211SP-7/10/12/15/20
TYPICAL THERMAL CHARACTERISTICS
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient lfpm Thermal impedance, junction ambient with flow lfpm lfpm lfpm TQFP 11.3 33.7 32.6 PLCC 30.4 18.5 15.9 13.5 12.8 Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations
data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment. TQFP thermal measurements taken with components six-layer printed circuit board.
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
Input, I/O, Feedback Combinatorial Output
20405B-6
Combinatorial Output
Input, I/O, Feedback Clock Registered Output
Input, I/O, Feedback Gate tPDL Latched
20405B-7
20405B-8
Registered Output
Latched Output
Clock
20405B-9
Gate tGWL
20405B-10
Clock Width
Gate Width
Registered Input tSIR Input Register Clock Combinatorial Output tICO
tHIR
Registered Input Input Register Clock Output Register Clock
tICS
20405B-11
20405B-12
Registered Input
Input Register Output Register Setup
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
Latched tSIL Gate
tHIL tIGO
Combinatorial Output
20405B-13
Latched Input
tPDLL Latched Latched Input Latch Gate tIGOL tSLL
tIGS Output Latch Gate
20405B-14
Latched Input Output
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
tWICH Clock tWICL Input Latch Gate tWIGL
20405B-15
20405B-16
Input Register Clock Width
Input Latch Gate Width
tARW Input, I/O, Feedback Registered Output Latched Output Clock Input Latch Gate Registered Output Latched Output tARR Clock Input Latch Gate Input, I/O, Feedback
tAPW tAPR
20405B-17
20405B-18
Asynchronous Reset
Asynchronous Preset
Input, I/O, Feedback Outputs
20405B-19
Output Disable/Enable
Notes: Input pulse amplitude Input rise fall times ns-4 typical.
MACH211SP-7/10/12/15/20
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
20405B-20
Commercial Specification tPD, Closed Open Closed Open Closed Measured Output Value
Switching several outputs simultaneously should avoided accurate measurement.
MACH211SP-7/10/12/15/20
FMAX PARAMETERS
parameter fMAX maximum clock rate which device guaranteed operate. Because flexibility inherent programmable logic devices offers choice clocked flip-flop designs, fMAX specified three types synchronous designs. first type design state machine with feedback signals sent off-chip. This external feedback could back device inputs, second device multi-chip state machine. slowest path defining period clock-to-output time input setup time external signals tCO). reciprocal, fMAX, maximum frequency with external feedback conjunction with equivalent speed device. This fMAX designated "fMAX external." second type design single-chip state machine with internal feedback only. this case, flip-flop inputs defined device inputs flip-flop outputs. Under these conditions, period limited internal delay from flip-flop outputs through internal feedback logic flip-flop inputs. This fMAX designated "fMAX internal". simple internal counter good example this type design; therefore, this parameter sometimes called "fCNT."
third type design simple data path application. this case, input data presented flip-flop clocked through; feedback employed. Under these conditions, period limited data setup time data hold time tH). However, lower limit period each fMAX type minimum clock period (tWH tWL). Usually, this minimum clock period determines period third fMAX, designated "fMAX feedback." devices with input registers, additional fMAX parameter specified: fMAXIR. Because this involves feedback, calculated same fMAX feedback. minimum period will limited either setup hold times (tSIR tHIR) clock widths (tWICL WICH clock widths normally limiting parameters, that fMAXIR specified 1/(tWICL tWICH). Note that both input output registers same path, overall frequency will limited tICS. frequencies except fMAX internal calculated from other measured parameters. fMAX internal measured directly.
(SECOND CHIP) LOGIC REGISTER LOGIC REGISTER
fMAX External; 1/(tS tCO)
fMAX Internal (fCNT)
LOGIC
REGISTER
REGISTER
LOGIC
fMAX Feedback; 1/(tS 1/(tWH tWL)
tSIR
tHIR
fMAXIR; 1/(tSIR tHIR) 1/(tWICL tWICH)
20405B-21
MACH211SP-7/10/12/15/20
ENDURANCE CHARACTERISTICS
MACH families manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed, feature which allows 100% testing factory.
Endurance Characteristics
Parameter Symbol Parameter Description Pattern Data Retention Time Reprogramming Cycles Years Cycles Operating Temperature Normal Programming Conditions Units Years Test Conditions Storage Temperature
MACH211SP-7/10/12/15/20
INPUT/OUTPUT EQUIVALENT SCHEMATICS
Protection
Input
Preload Circuitry
Feedback Input
20405B-22
MACH211SP-7/10/12/15/20
POWER-UP RESET
MACH devices have been designed with capability reset during system power-up. Following power-up, flip-flops will reset LOW. output state will depend logic polarity. This feature provides extra flexibility designer especially valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up
Parameter Symbol Parameter Descriptions Power-Up Reset Time Input Feedback Setup Time Switching Characteristics Clock Width
reset wide range ways rise steady state, conditions required insure valid power-up reset. These conditions are: rise must monotonic. Following reset, clock input must driven from HIGH until applicable input feedback setup times met.
Unit
Power Registered Output Clock
20405B-23
Power-Up Reset Waveform
MACH211SP-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Advanced Micro Devices, Inc. P.O. 3453, 1028 Sunnyvale, 94088-3543 (800) 222-9323 (408) 732-2400 Cadence Design Systems River Oaks Pkwy Jose, 95134 (408) 943-1234 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 Mentor Graphics Corp. 8005 S.W. Boeckman Wilsonville, 97070-7777 (800) 547-3000 (503) 685-7000 MicroSim Corp. Fairbanks Irvine, 92718 (714) 770-3022 MINC Incorporated 6755 Earl Drive, Suite Colorado Springs, 80918 (800) 755-FPGA (719) 590-1155 SUSIE-CAD 10000 Nevada Highway, Suite Boulder City, 89005 (702) 293-2271 Synopsys Logic Modeling 19500 Gibbs P.O. Beaverton, 97075 (503) 690-6900 Teradyne Harrison Ave. Boston, 02118 (800) 777-2432 (617) 422-2793 SOFTWARE DEVELOPMENT SYSTEMS MACHXL® Software Ver.
Design Center/AMD Software
AMD-ABEL Software Data MACH Fitters
PROdeveloper/AMD Software PROsynthesis/AMD Software PLDDesigner Verilog, LeapFrog, RapidSim Simulators Ver. 9504
ABELSoftware SynarioSoftware
PLDSynthesisII QuickSim Simulator
Design Center Software
PLDesignerTM-XL Software
SUSIESimulator
SmartModel® Library
MultiSIM Interactive Simulator LASAR
MACH211SP-7/10/12/15/20
DEVELOPMENT SYSTEMS (subject change) (continued)
MANUFACTURER Viewlogic Systems, Inc. Boston Post Road West Marlboro, 01752 (800) 442-4660 (508) 480-0881 MANUFACTURER Acugen Software, Inc. 427-3 Amherst St., Suite Nashua, 03063 (603) 891-1995 GmbH Busenstrasse D-8033 Martinsried, Munich, Germany (87) 857-6667 SOFTWARE DEVELOPMENT SYSTEMS ViewPLD PROPLD (Requires PROSim Simulator MACH Fitter) ViewSim Simulator TEST GENERATION SYSTEM
ATGENTest Generation Software
PLDCheck
Advanced Micro Devices responsible information relating products third parties. inclusion such information representation endorsement these products.
MACH211SP-7/10/12/15/20
APPROVED PROGRAMMERS (subject change)
more information products listed below, please consult FusionPLD Catalog.
MANUFACTURER Advin Systems, Inc. 1050-L East Duane Ave. Sunnyvale, 94086 (408) 243-7000 Microsystems Post Houston, 77055-7237 (800) 225-2102 (713) 688-4600 Data Corporation 10525 Willows Road N.E. P.O. 97046 Redmond, 98073-9746 (800) 332-8246 (206) 881-6444 Hi/Lo Sec. Ming Shoh Taipei, Taiwan Logical Devices Inc./Digelec Military Trail Deerfield Beach, 33442 (800) 331-7766 (305) 428-6868 North America, Inc. 16522 135th Place Redmond, 98052 (800) 722-4122 Grund D-7988 Vangen Allgau, Germany 07522-5018 Stag Microsystems Inc. 1600 Wyatt Suite Santa Clara, 95054 (408) 988-1118 Stag House Martinfield, Welwyn Garden City Herfordshire 707-332148 System General Park Victoria Milpitas, 95035 (408) 263-6667 Alley Lane Shing Rd., Shin Diau Taipei, Taiwan 2-917-3005 PROGRAMMER CONFIGURATION
Pilot
BP1148
BP1200
BP2100
UniSite
Model 2900
Model 3900
AutoSite
ALL-07
FLEX-700
ALLPROTM-88
Sprint
Expert
Multisite
Stag Quazar Stag Eclipse
Turpro-1
MACH211SP-7/10/12/15/20
APPROVED ON-BOARD PROGRAMMERS
MANUFACTURER Corelis, Inc. 12607 Hidden Creek Way, Suite Cerritos, California 70703 (310) 926-6727 Advanced Micro Devices P.O. 3453, MS-1028 Sunnyvale, 94088-3453 (800) 222-9323 PROGRAMMER CONFIGURATION
JTAG PROG
MACHpro
PROGRAMMER SOCKET ADAPTERS (subject change)
MANUFACTURER California Integration Technologies Main Street Placerville, 95667 (916) 626-6168 Corporation P.O. Patterson, 95363 (209) 892-3270 Emulation Technology 2344 Walsh Ave., Bldg. Santa Clara, 95051 (408) 982-0660 Logical Systems Corp. P.O. 6184 Syracuse, 13217-6184 (315) 478-0722 Procon Technologies, Inc. 1333 Lawrence Expwy, Suite Santa Clara, 95051 (408) 246-4456 PART NUMBER
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
Contact Manufacturer
MACH211SP-7/10/12/15/20
PHYSICAL DIMENSIONS* 44-Pin Plastic Leaded Chip Carrier (measured inches)
.062 .083
.685 .695
.650 .656
.042 .056
I.D. .685 .695 .650 .656 .500 .590 .630
.013 .021
.026 .032
.050
.009 .015
.090 .120 .165 .180
SEATING PLANE
VIEW
SIDE VIEW
16-038-SQ DA78 6-28-94
reference only. ANSI standard Basic Space Centering.
MACH211SP-7/10/12/15/20
PHYSICAL DIMENSIONS PQT044 44-Pin Thin Quad Flat Pack (measured millimeters)
11.80 12.20 9.80 10.20
9.80 10.20 11.80 12.20
0.95 1.05 1.20
16-038-PQT-2 7-11-95
1.00 REF.
0.30 0.45
0.80
Trademarks Copyright 1996 Advanced Micro Devices, Inc. rights reserved. AMD, logo, MACH, registered trademarks Advanced Micro Devices, Inc. Bus-Friendly trademark Advanced Micro Devices, Inc. Product names used this publication identification purposes only trademarks their respective companies.
MACH211SP-7/10/12/15/20

IND: -10/12/14/18/24 MACH211SP-7/10/12/15/20 High-Density CM

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