I2C-Compatible Real-Time Clocks with Supervisor Controller MAX690

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I2C-Compatible Real-Time Clocks with Supervisor Controller MAX690

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19-3322; 8/04
I2C-Compatible Real-Time Clocks with Supervisor Controller
MAX6909/MAX6910 real-time clocks (RTCs) with microprocessor supervisor, optional trickle charger (MAX6910 only), backup power source, controller. MAX6909/ MAX6910 provide alarm outputs indicate crystal failure, switchover battery power, time date indication. bytes static that available scratchpad storage. MAX6909/ MAX6910 controlled through 2-wire serial bus. real-time clock/calendar provides seconds, minutes, hours, day, date, month, year information. date automatically adjusted months with fewer than days, including corrections leap year year 2100. clock operates either 24-hour 12-hour format with AM/PM indicator. time/date-programmable ALARM output completes features list real-time clock section MAX6909/MAX6910. alarm function also used polled mode periodically reading alarm status minutes register. crystal fail output, FAIL, indicates loss accurate timekeeping crystal problems. built-in supervisor with open-drain reset ensures powers known state. reset threshold available 3.3V supplies. piezo transducer output, PZT, register selectable four frequencies, turned through register bit, selected when ALM, alarm output, goes active. MAX6909/MAX6910 available 20-pin QSOP package operate over -40°C +85°C temperature range. I2CTM-compatible
Features
Counts Seconds, Minutes, Hours, Date Month, Month, Week, Year, with Leap Year Compensation Valid 2100 Bytes Scratchpad Data Storage Uses Standard 32.768kHz, Load, Watch Crystal Programmable Time/Date, Open-Drain ALARM Output (Status also Polled) Chip Enable Gating (Control with Reset Power Valid) SRAM Power Reset Output Watchdog Input Manual Reset Input with Push-Button Switch Debounce Independent Power-Fail Reset Comparators 400kHz 2-Wire Interface Single-Byte Multiple-Byte (Burst Mode) Data Transfer Read Write Clock Registers Timeout Prevent Lockup Malfunctioning Interface Dual Power-Supply Pins Primary Backup Power Programmable Trickle Charger (MAX6910) Uses Less than Timekeeping Current 3.0V Operating Voltages 3.3V
MAX6909/MAX6910
Applications
Point-of-Sale Equipment Programmable Logic Controller Handheld Instruments Medical Instrumentation
PART MAX6909EO30 MAX6909EO33 MAX6910EO30 MAX6910EO33
Ordering Information
TEMP RANGE -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C PIN-PACKAGE QSOP QSOP QSOP QSOP
Configuration/Selector Guide/Typical Operating Circuit appear data sheet.
trademark Philips Corp. Purchase components Maxim Integrated Products, Inc., sublicensed Associated Companies, conveys license under Philips Patent rights these components system provided that system conforms Standard Specification defined Philips. Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
ABSOLUTE MAXIMUM RATINGS
Voltages (with respect GND) BATT .-0.3V +6.0V OUT, ALM, SCL, SDA, FAIL, PFO, RESET.-0.3V +6.0V Other Pins .-0.3V (VSUP 0.3V) (where VSUP greater VBATT VCC) Input Current .500mA BATT .100mA .20mA Output Current Continuous.450mA Other Outputs .20mA Continuous Power Dissipation +70°C) 20-Pin QSOP (derate 9.1mW/°C above +70°C).727mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range -65°C +150°C Lead Temperature (soldering, 10s) +300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Notes
PARAMETER Operating Voltage Range Operating Voltage Range BATT SYMBOL VBATT CONDITIONS MAX69_EO30 (Note MAX69_EO33 (Note MAX69_EO30 (Note MAX69_EO33 (Note Crystal failcircuit disabled VBATT VBATT VBATT 3.6V, Timekeeping Current (Note IBATT Crystal failcircuit enabled disabled, crystal-disabled disabled, crystal-disabled Crystal failcircuit enabled VBATT VBATT VBATT 3.6V, Active Supply Current (Note Standby Current (Note Standby Current (Note Trickle-Charge Diode Voltage Drop (Two Diodes) Trickle Charge Resistors Battery-Backup Mode (Note VBATT 3.0V, IOUT 20mA VOUT VBATT 2.0V, IOUT 10mA VBATT 0.15 VBATT VBATT VBATT 0.05 ICCA ICCS ICCS 3.3V, VBATT 3.6V, VBATT 3.3V, VBATT 3.6V, VBATT 3.3V, VBATT 3.6V, VBATT 0.75 0.95 0.14 0.15 UNITS
BATT Current (Note
IBATT
I2C-Compatible Real-Time Clocks with Supervisor Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Notes
PARAMETER SYMBOL CONDITIONS 3.0V, VBATT IOUT 100mA Mode (Note VOUT 2.7V, VBATT IOUT 50mA VBATT Switchover Threshold VBATT Switchover Threshold Leakage Current Resistance Disabled, VRST, VCC(min), 0.9VCC, 0.1VCC source impedance driver, CLOAD 10pF, VCC(MIN), 0.9VCC, (Note measured from point point tRCE high, VCC(MIN) VCC(MAX) VTRU VTRD Power-up (VCC VRST) switch from VBATT (Note Power-down (VCC VRST) switch from VBATT (Note 0.15 0.05 VBATT 0.05 VBATT 0.05 UNITS
MAX6909/MAX6910
Propagation Delay
RESET RESET) Active disabled pulled VOUT Delay Enabled Connected After VRST High (RESET RESET Active) MANUAL RESET INPUT
IOUT -100µA, VBATT
0.95 VOUT
Input Threshold Internal Pullup Resistance Minimum Pulse Width Glitch Immunity Reset Delay Input Threshold VPFT (Note (Note VCC(MIN) 1.19 1.27
1.31
POWER-FAIL INPUT POWER-FAIL OUTPUT
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
ELECTRICAL CHARACTERISTICS (continued)
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Notes
PARAMETER Input Current Delay Hysteresis Output Voltage High Output Voltage WATCHDOG INPUT Watchdog Timeout Period Initial Watchdog Timeout Period Minimum Input Pulse Width tWDS tWDI Input Threshold Input Current OUTPUT Output Short-Circuit Current (VCC Must VRST Active) Frequency Frequency Frequency Frequency Off-Leakage Current CRYSTAL-FAIL OUTPUT FAIL Output Voltage FAIL Off-Leakage Current ALARM OUTPUT Output Voltage Off-Leakage Current IOLKG 3mA, VBATT 2.0V, 5mA, 2.7V, VBATT 0.25 IOLKG VBATT 2.0V, 2.7V, 5mA, VBATT 0.25 MAX69_ _EO30 IPZT MAX69_ _EO33 PZTf1 PZTf2 PZTf3 PZTf4 IOLKG Sink current Source current Sink current Source current 1024 2048 4096 8192 VWDI -100 +100 Before first edge, after reset timeout Register select-long Register select-short 1.00 1.00 2.25 2.25 VPFH (Note rising ISOURCE 200µA, VCC(MIN) ISINK 1.2mA, VBATT rising falling SYMBOL CONDITIONS -100 0.06 +100 UNITS
I2C-Compatible Real-Time Clocks with Supervisor Controller
ELECTRICAL CHARACTERISTICS (continued)
(VCC VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted. Typical values +25°C.) (Notes
PARAMETER BATTERY OUTPUT BATT Output Voltage BATT Off-Leakage Current RESET FUNCTION Reset Threshold VRST Hysteresis Falling Reset Delay Reset Active Timeout Period RESET Output Voltage RESET Off-Leakage Current ILKG 50µA, 1.0V, VBATT 1mA, VBATT VCC(MIN), 1.6mA 0.05 (Note 4mA, VCC(MIN) Reset asserted 1.6mA, VBATT 2.0V, 0.032 VRST VHYST falling from VRST(MAX) VRST(MIN) 10V/ms, measured from beginning falling RESET asserting high MAX69_ _EO33 MAX69_ _EO30 2.80 2.50 2.93 2.63 3.00 2.70 IOLKG VBATT 2.0V, 3mA, VBATT 2.7V, 5mA, 0.25 SYMBOL CONDITIONS UNITS
MAX6909/MAX6910
RESET Output High Voltage
Reset asserted
RESET Output Voltage
2-WIRE DIGITAL INPUTS (SCL, SDA) (VCC(MIN) VCC(MAX)) Input High Voltage Input Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Voltage VHYS
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
ELECTRICAL CHARACTERISTICS
(VCC(MIN) VCC(MAX), -40°C +85°C, unless otherwise noted.) (Note
PARAMETER 2-WIRE TIMING Clock Frequency Timeout Free Time Between STOP START Condition Hold Time After (Repeated) START Condition; After This Period, First Clock Generated Repeated START Condition Setup Time STOP Condition Setup Time Data Hold Time Data Setup Time Data Valid Period High Period SCL/SDA Rise Time SCL/SDA Fall Time (Receiving) SCL/SDA Fall Time (Transmitting) Pulse Width Spike Suppressed Capacitive Load Each Line fSCL tTIMEOUT tBUF (Note 0.32 400.00 SYMBOL CONDITIONS UNITS
tHD:STA
tSU:STA tSU:STO tHD:DAT tSU:DAT tVD:DAT tLOW tHIGH (Note (Notes (Notes (Note (Note (Notes
Note Note Note Note Note Note Note Note Note Note Note Note Note
VRST reset threshold VCC. Ordering Information. parameters 100% tested +85°C. Limits over temperature guaranteed design production tested. 2-wire serial interface operational VRST. Detailed Description section (BATT function). IBATT ICCS specified with SCLK pulled high, floating, floating. 2-wire serial interface operating 400kHz, pulled high. switch over BATT, must fall below VRST VBATT. switchover VCC, must above VRST above VBATT. Guaranteed design. production tested. 2-wire timeout feature, there minimum specification clock frequency based 31-byte burst-mode transaction RAM. Timeout Feature section. device must internally provide hold time least 300ns signal (referred signal) order bridge undefined region falling edge SCL. maximum tHD:DAT only device does stretch period (tLOW) signal. total capacitance line maximum lines specified 300ns. maximum fall time output stage specified 250ns. This allows series protection resistors connected between SDA/SCL pins SDA/SCL lines without exceeding maximum specified
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Typical Operating Characteristics
(VCC 3.3V, VBATT +25°C, unless otherwise noted.)
VOLTAGE TEMPERATURE
MAX6909/10 toc01
BATT-TO-OUT VOLTAGE TEMPERATURE
MAX6909/10 toc02
BATT TIMEKEEPING CURRENT TEMPERATURE
VBATT CRYSTAL FAIL-DETECTION DISABLED
MAX6909/10 toc03
VBATT IOUT 50mA
BATT TIMEKEEPING CURRENT (nA)
VBATT IOUT 100mA
BATT-TO-OUT VOLTAGE (mV)
VOLTAGE (mV)
3.3V VBATT IOUT 100mA
VBATT 3.0V IOUT 50mA
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
RESET TIMEOUT PERIOD TEMPERATURE
MAX6909/10 toc04
RESET COMPARATOR DELAY FALLING
MAX6909/10 toc05
RESET COMPARATOR DELAY TEMPERATURE
RESET DELAY (µs) FALLING 10V/ms
MAX6909/10 toc06
TIMEOUT PERIOD (ms) TEMPERATURE (°C)
1000
RESET DELAY (µs)
FALLING (V/ms) 1000 TEMPERATURE (°C)
RESET THRESHOLD TEMPERATURE
MAX6909/10 toc07
THRESHOLD TEMPERATURE
1.243 1.242 THRESHOLD 1.241 1.240 1.239 1.238 1.237 1.236 1.235 1.234
MAX6909/10 toc08
PFI-TO-PFO DELAY FALLING
MAX6909/10 toc09
3.100 3.095 3.090 RESET THRESHOLD 3.085 3.080 3.075 3.070 3.065 3.060 3.055 3.050 TEMPERATURE (°C)
1.244
DELAY (µs)
1000
TEMPERATURE (°C)
FALLING (V/ms)
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Typical Operating Characteristics (continued)
(VCC 3.3V, VBATT +25°C, unless otherwise noted.)
WATCHDOG TIMEOUT PERIOD TEMPERATURE
MAX6909/10 toc10 MAX6909/10 toc11
PFI-TO-PFO DELAY TEMPERATURE
13.0 12.5 DELAY (µs) 12.0 11.5 11.0 10.5 10.0 TEMPERATURE (°C) 1.700 WATCHDOG TIMEOUT PERIOD (ms) 1.695 1.690 1.685 1.680 1.675 1.670 1.665 1.660 FALLING 10V/ms
CE_IN CE_OUT ON-RESISTANCE
CE_IN CE_OUT ON-RESISTANCE VCE_IN
MAX6909/10 toc12
VOLTAGE
TEMPERATURE (°C)
CE_IN CE_OUT ON-RESISTANCE TEMPERATURE
MAX6909/10 toc13
OUTPUT RESISTANCE
OUTPUT RESISTANCE (VBATT/ISINK VCC/ISOURCE)
MAX6909/10 toc14
CE_IN CE_OUT ON-RESISTANCE VCE_IN VRST 0.1V 3.03V VRST 0.1V 2.73V
OUTPUT RESISTANCE
TEMPERATURE (°C)
VOLTAGE
OUTPUT RESISTANCE TEMPERATURE
MAX6909/10 toc15
MAXIMUM TRANSIENT DURATION RESET COMPARATOR OVERDRIVE
MAXIMUM TRANSIENT DURATION (µs) OVERDRIVE (mV) RESET ASSERTS ABOVE THIS LINE
MAX6909/10 toc16
OUTPUT RESISTANCE
3.3V
TEMPERATURE (°C)
I2C-Compatible Real-Time Clocks with Supervisor Controller
Description
NAME BATT BATT FAIL RESET RESET FUNCTION Backup Battery Input. When falls below reset threshold VBATT, connects BATT. Connect BATT backup battery supply used. Supply Output CMOS Other Requiring Backup Battery Power. Bypass with least 0.1µF capacitor. Logic Output Open Drain. BATT when MAX6909/MAX6910 powered from BATT. Chip-Enable Input. Input chip-enable switch used external RAM. Connect unused. Power-Fail Comparator Input. monitoring external power supplies. Manual Reset Input. active-low input internal pullup resistor. Internal debouncing circuitry ensures noise immunity. Leave open unused. Watchdog Input Ground 32.768kHz Crystal Pin; Oscillator Input 32.768kHz Crystal Pin; Oscillator Output Crystal Fail Output. Open drain, active low. Serial Data Line. Data input/output connection 2-wire serial interface. Serial Clock Line. Clock input connection 2-wire serial interface. Alarm Output. Open drain, active low. Piezo Transducer Output. Push-pull Piezo transducer output. Power-Fail Comparator Output. Push-pull active low. Chip-Enable Output. controlling external RAM. Open-Drain, Active-Low Reset Output Push-Pull, Active-High Reset Output. Complement RESET. Main Supply Input. Bypass with least 0.01µF capacitor.
MAX6909/MAX6910
Detailed Description
MAX6909/MAX6910 contain eight 8-bit timekeeping registers, burst address registers, trickle charge register, control register, configuration register, alarm configuration register, seven alarm threshold registers, controlled through 2-wire serial interface. Figure MAX6909/MAX6910 block diagram. supplies voltage CMOS other requiring backup battery power. When rises above reset threshold (VRST) above VBATT, connected VCC. When falls below VRST VBATT, BATT connected OUT. enabled, on-board trickle charger charges BATT from VCC. BATT backup supply from either battery SuperCapTM. When operating from BATT, batteryon output (BATT pulled used indicator operation battery backup mode.
SuperCap trademark Baknor Industries.
There reset outputs, RESET RESET. They become active while below reset threshold (VRST) while manual reset (MR) held low, after goes high, rises above reset threshold, pulse received when watchdog function enabled. Reset thresholds available 3.3V applications. Ordering Information specifics. internally pulled high contains debounce circuitry accommodate manual pushbutton reset switch. WDI, when enabled, keeps RESET RESET from becoming active strobed once every tWDS tWD. watchdog timeout selectable configuration register. Other features include internal chip-enable gating logic, which accepts valid from microprocessor only gates through valid when MAX6909/MAX6910 reset state. This used disabling CMOS limit current consumption when switched BATT.
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
OSCILLATOR 32.768kHz DIVIDERS FREQUENCY SELECT
CX_FAIL
CRYSTALFAIL DETECT WATCHDOG TIMER DEBOUNCE CIRCUIT
SOURCE SELECT
RESET RESET LOGIC RESET
1.2V
CE_IN
CONTROL
CE_OUT
SECONDS MINUTES HOURS DATE MONTH
BATT BATT_ON POWER CONTROL CONTROL LOGIC
YEAR CONTROL TRICKLE CHARGER CENTURY
INPUT SHIFT REGISTERS
ADDRESS REGISTER
ALARM CONFIG TEST CONFIG
STATUS CONFIG ALARM THRESHOLDS BURST
ALARM CONTROL LOGIC
BURST
Figure MAX6909/MAX6910 Block Diagram
I2C-Compatible Real-Time Clocks with Supervisor Controller
power-fail comparator available monitor other system voltages through report status through PFO. MAX6909/MAX6910 reset, low; otherwise, high long greater than 1.27V (typ). piezo transducer drive output (PZT) registerselectable frequencies 1.024kHz, 2.048kHz, 4.096kHz, 8.192kHz. This output selected become active when alarm triggered independently controlled through configuration register. When activated, outputs frequency with attention-getting duty cycle off. on-chip crystal oscillator maintaining circuit, with 32.768kHz crystal, provides clock timekeeping functions. crystal fail output FAIL) alerts user when 32.768kHz crystal oscillator failed cycles (typ), resulting conditions that produce invalid timekeeping data. crystal fail function also polled reading status status register. itance (CL) where capacitive load included MAX6909/MAX6910. When designing board, keep crystal close pins possible. Keep trace lengths short small place guard ring around crystal connect ring reduce capacitive loading prevent unwanted noise pickup. Keep signals from beneath crystal pins prevent noise coupling. Finally, additional local ground plane adjacent board layer added under crystal shield from unwanted pickup from traces other layers board. This plane should isolated from regular board ground plane, should larger than perimeter guard ring, connected MAX6909/MAX6910. Ensure that this ground plane does contribute significant capacitance between signal line ground connections that from crystal. Figure shows recommended crystal layout. Some crystal manufacturers part numbers their SMT, 32.768kHz watch crystals that require loads listed Table addition, these manufacturers offer other package options depending upon specific application considerations.
MAX6909/MAX6910
Crystal Selection
32.768kHz crystal connected MAX6909/ MAX6910 through pins X2). crystal selected should have specified load capac-
GROUND PLANE CONNECTION MAX6909/MAX6910 GUARD RING
WATCH CRYSTAL
GROUND PLANE CONNECTION *LAYER TRACE **LAYER LOCAL GROUND PLANE CONNECT ONLY GROUND PLANE CONNECTION
Figure Recommended Crystal Layout
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Table Crystal Manufacturers Part Numbers
MANUFACTURER Caliber Electronics International Electronics M-tron Raltron PART AWS2A-32.768KHz, AWS2B-32.768KHz ECS-.327-6.0-17 FSM327 SX2010/ SX2020 RSE-32.768-6-C-T TEMP RANGE (°C) (pF) +25°C FREQUENCY TOLERANCE (ppm)
Timekeeping accuracy MAX6909/MAX6910 dependent frequency stability external crystal. determine frequency stability, parabolic curve Figure following equations: where: change frequency from +25°C (Hz) nominal crystal frequency (Hz) parabolic curvature constant (-0.035 ±0.005ppm/°C2 32.768kHz watch crystals) turnover temperature (+25°C ±5°C 32.768kHz watch crystals) temperature interest (°C) example: What worst-case change oscillator frequency from +25°C ambient +45°C ambient?
fdrift 32,768Hz (-0.04ppm/°C)2 (20°C 45°C)2 -0.8192Hz What worst-case timekeeping error second? Error temperature drift: tdrift fdrift) 32,768]] tdrift [(32,768Hz 0.8192Hz) 32,768]] 0.000025s Error +25°C initial crystal tolerance ±20ppm: finitial 32,768Hz (-20ppm) -0.65536Hz tinitial finitial) 32,768]] tinitial [32,768 0.65536 32,768]] 0.000020s Total timekeeping error second: ttotal tdrift tinitial
ttotal 0.000025s 0.000020s 0.000045
TYPICAL TEMPERATURE CHARACTERISTICS -0.035ppm/°C2; +25°C)
MAX6909
(ppm)
-100
-150
12pF
12pF
-200
-250 -50-40-30-20-10 TEMPERATURE (°C)
EXTERNAL CRYSTAL
Figure Frequency Stability Temperature
Figure Oscillator Functional Schematic
I2C-Compatible Real-Time Clocks with Supervisor Controller
Table Acceptable Quartz Crystal Parameters
PARAMETER Frequency Equivalent series resistance (ESR) Parallel load capacitance factor SYMBOL 40,000 32.768 UNITS
MAX6909/MAX6910
After month that translates (31day)
static bytes addressed consecutively address space. Even address/commands (C0h-FCh) used writes, address/commands (C1h-FDh) used reads. contents static remain valid VOUT down 1.5V (typ).
(0.000045s 120.158s
Total worst-case timekeeping error month +45°C approximately 120s 2min (assumes negligible parasitic layout capacitance). Figure shows register address definition. Table register address/description.
Burst
Addressing burst register specifies burst mode operation. this mode, registers consecutively read written starting with address write read. When writing burst mode, necessary write bytes data transfer. Each byte that written transferred regardless whether bytes written.
Control Register (Write Protect Bit)
control register write protect bit. lower bits (bits 0-6) forced zero always read zero when read. Before write operation clock RAM, must zero. When high, write protect prevents write operation other register.
Trickle Charge Register (MAX6910)
trickle charge register controls trickle charger characteristics MAX6910. trickle charger functional schematic (Figure shows basic components trickle charger. Table details settings trickle charger control. Trickle charge selection (TCS) bits D7-D4 control selection trickle charger. order prevent accidental enabling, only pattern 1010 enables trickle charger. other patterns disable trickle charger. MAX6910 powers with trickle charger disabled. diode select (DS) bits (D3-D2) select whether diodes diodes connected between BATT. diode selected; diodes selected. trickle charger disabled independent state bits. bits (D1-D0) select resistor that connected between BATT. both bits zero, trickle charger disabled, regardless other states trickle charger register. bits select 1.7K, selects 2.9K, select
Hours Register (AM-PM/12-24 Mode)
hours register defined 12-hour 24-hour mode select bit. When high, 12-hour mode selected. 12-hour mode, AM/PM with logic high being 24-hour mode, second 10-hour (20h-23h).
Clock Burst
Addressing clock burst register specifies burst mode operation. this mode, first seven clock/calendar registers control register consecutively read written starting with address write read. write protect high when write clock/calendar burst mode specified, data transfer occurs seven clock/calendar registers control register. When writing clock registers burst mode, eight registers must written order data transferred. addition, control register must zero prior clock burst write.
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
REGISTER ADDRESS FUNCTION *POR STATE 00-23 12/24 01-12 *POR STATE DATE 01-28/29 01-30 01-31 *POR STATE MONTH YEAR CONTROL TRICKLE CHARGER ALARM CONFIG *POR STATE 00-99 *POR STATE FAIL *POR STATE 01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE VALUE 00-59 *POR STATE 00-59 REGISTER DEFINITION
DATE
DATE
MONTH WEEKDAY
YEAR
YEAR
CENTURY
1000 YEAR MONTH
YEAR
HOUR
YEAR
DATE
TEST CONFIG
*POR STATE
*POR STATE
NOTE: *POR STATE DEFINES POWER-ON RESET STATE REGISTER CONTENTS. TEST CONFIG REGISTER READ-ONLY REGISTER.
Figure Register Address Definition (Sheet
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
REGISTER ADDRESS FUNCTION STATUS *POR STATE CONFIG *POR STATE ALARM THRESHOLDS: VALUE REGISTER DEFINITION FAIL TIME
CNTL REFQ FREQ
00-59 *POR STATE 00-59 *POR STATE
00-23 12/24 01-12 *POR STATE
DATE
01-28/29 01-30 01-31 *POR STATE
DATE
DATE
MONTH
01-12 *POR STATE 01-07 *POR STATE 00-99 *POR STATE
MONTH WEEKDAY
YEAR
YEAR
YEAR
CLOCK BURST
DATA
DATA
BURST
NOTE: *POR STATE DEFINES POWER-ON RESET STATE REGISTER CONTENTS.
Figure Register Address Definition (Sheet
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Table Register Address/Description
WRITE (HEX) READ (HEX) Seconds Minutes Hours Date Month Year Control Trickle charger Century Alarm configuration Test configuration* status Configuration Seconds alarm threshold Minutes alarm threshold Hours alarm threshold Date alarm threshold Month alarm threshold alarm threshold Year alarm threshold Clock burst DESCRIPTION CONTENTS (HEX) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate CONTENTS (BCD) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
*This read-only register.
I2C-Compatible Real-Time Clocks with Supervisor Controller
Table Register Address/Description (continued)
WRITE (HEX) READ (HEX) Burst DESCRIPTION CONTENTS (HEX) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate CONTENTS (BCD) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate
MAX6909/MAX6910
Diode resistor selection determined user, according maximum current desired battery SuperCap charging. maximum charging current calculated shown following example. Assume that system power supply applied SuperCap connected BATT. Also assume that trickle charger been enabled with diode resistor between BATT. maximum current IMAX would therefore calculated follows: IMAX 3.0V 3.0V 1.76mA 1.7k
SuperCap charges, voltage difference between VBATT decreases, therefore charge current decreases. MAX6909 does feature trickle charger.
Power Control, Trickle Charger, Battery Switchover
BATT provides power battery backup. provides primary power dual-supply systems where BATT connected backup source maintain timekeeping function register contents. When rises above reset threshold, VRST, powers MAX6909/MAX6910. When falls below reset
threshold, VRST, less than VTPD, BATT powers MAX6909/MAX6910. falls below reset threshold, more than powers MAX6909/MAX6910. When RESET RESET active, inputs (MR, WDI, 2-wire interface) disabled. addition, when operating from BATT, outputs RESET, RESET, remain active state, high impedance pulled OUT. timekeeping function remains active, together with alarm function crystal fail function enabled. minimize power consumption when operating from BATT, some functions disabled; Table MAX6909/ MAX6910 functional blocks remain active when powered from BATT. battery connected prior application with current being drawn from battery MAX6909/MAX6910 remaining inactive. This freshness seal mode operation. very first application MAX6909/MAX6910, must rise above reset threshold. battery should only changed with applied order maintain timekeeping functions. trickle charger enabled disabled through software control automatically disabled whenever falls below VBATT.
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Table Trickle-Charger Register Control
Trickle charger disabled Trickle charger disabled Trickle charger disabled diode selected; 1.7K selected diode selected; 2.9K selected diode selected; selected diodes selected; 1.7K selected diodes selected; 2.9K selected diodes selected; selected ACTION
1.7k 2.9k BATT
SELECT (NOTE: ONLY 1010 CODE ENABLES CHARGER)
SELECT
SELECT TRICKLE CHARGER SELECT DIODE SELECT RESISTOR SELECT
TRICKLE CHARGE
REGISTER
Figure Trickle-Charger Functional Schematic
Function
output supply voltage external devices. When rises above reset threshold greater than VBATT, connects VCC. When falls below VRST VBATT, connects BATT. There typical VTRU VTRD hysteresis associated with switching between BATT BATT VRST typically VHYST hysteresis BATT VRST. Connect least 0.1µF capacitor from ground (GND). Switching from BATT uses break-before-make switch; capacitor from prevents loss power needed clock data during switchover.
Oscillator Start Time
MAX6909/MAX6910 oscillator typically takes 100ms settle optimum operating power level after startup. ensure oscillator operating, system software should validate this reading seconds register. reading with more than from value validation that oscillator operating.
Power-On Reset (POR)
MAX6909/MAX6910 contain integral circuit that ensures registers reset known state power-up. initial power-up, once VOUT rises above 0.75V (typ), circuit releases registers normal operation. Should VOUT less than 1.5V (typ), contents MAX6909/MAX6910 registers longer guaranteed.
I2C-Compatible Real-Time Clocks with Supervisor Controller
Table MAX6910 Sections Powered from BATT
DESCRIPTION Crystal Oscillator Crystal Oscillator Backup Power-Supply Input BATT VRESET) Manual Reset Input Battery-On Output Watchdog Input Chip-Enable Input Power-Fail Input Ground Active Low, Open-Drain Reset Output (-OD) Active High, Push/Pull Reset Output Chip-Enable Output Power-Fail Output Alarm Output Piezo Output Crystal-Fail Output 2-Wire Data 2-Wire Clock Main Power-Supply Input Trickle Charge FEATURES Crystal Oscillator Timekeeping Registers Control Registers Crystal Fail Detect Alarm Registers Power-Fail Comparator RESET Comparator Watchdog Timer Internal Reference Power Switchover Circuitry Piezo Dividers/Select Register Trickle Charge Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Disabled Enabled Enabled Disabled Enabled Disabled Disabled BATT Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply Supply NAME BATT BATT RESET RESET FAIL POWER Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled VRST Enabled Enabled Disabled Enabled Disabled Disabled Disabled Enabled Enabled Disabled Enabled Enabled Disabled Enabled Disabled Disabled Disabled Power High impedance Pulled Pulled Pulled Pulled Input ignored Input ignored Input ignored Power Input ignored Power Power output VRST COMMENTS COMMENTS
MAX6909/MAX6910
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Alarm Generation Registers
alarm function generates ALARM when contents SEC, MIN, DATE, MONTH, DAY, YEAR registers match respective alarm threshold registers. Also, generation ALARM programmable through alarm configuration register. alarm configuration register written with address read with address 95H. alarm configuration register definition shown Figure (register address definition). Placing appropriate enables alarm status when selected alarm threshold register contents match respective timekeeping register contents. example, writing 0000 0001 alarm configuration register causes alarm triggered every minute (each time contents seconds timekeeping register match contents seconds alarm threshold register). Writing 0000 0010 causes alarm every hour (each time contents minutes timekeeping register match contents minutes alarm threshold register). Writing 0100 1111 alarm configuration register, therefore, causes alarm triggered specific second, specific minute, specific hour, specific date, specific year. alarm output stays until "cleared" reading writing alarm configuration register reading writing alarm threshold registers.
VRST RESET
Figure Manual Reset Timing
Reset Outputs
µP's reset input starts known state. When RESET RESET active, control inputs (MR, WDI, 2-wire interface) disabled. MAX6909/MAX6910 supervisory circuit asserts reset prevent code-execution errors during power-up, power-down, brownout conditions. RESET, opendrain active low, RESET (push-pull active high) guaranteed active VRST, provided VOUT greater than Once exceeds reset threshold, internal timer keeps RESET RESET active reset timeout period (tRP); after this interval, RESET becomes inactive (high) RESET becomes inactive (low). brownout condition occurs (VCC dips below reset threshold), RESET RESET become active. Each time RESET RESET asserted, they held active reset timeout period. MAX69_ _EO30 optimized monitor 3.0V ±10% power supplies. Except when asserted, reset does occur until falls below 2.7V (3.0V 10%), guaranteed occur before power supply falls below +2.5V. MAX69_ _EO33 optimized monitor 3.3V ±10% power supplies. Except when asserted, reset does occur until falls below 3.0V (3.0V just above 3.3V 10%), guaranteed occur before power supply falls below 2.8V. Maximum Transient Duration Reset Comparator Overdrive graph Typical Operating Characteristics.
Minutes Register (Alarm Status)
alarm status available desired alarm function polled alarm instead connecting directly output pin. minutes timekeeping register contains status output with indicating alarm function triggered zero indicating triggered alarm.
Manual Reset Input
Many microprocessor-based products require manualreset capability, allowing operator, test technician, external logic circuitry initiate reset. With MAX6909/MAX6910, logic asserts reset. Reset remains asserted while low, (Figure after returns high. internal pullup resistor typically 50k, left open used. Internal debounce circuitry requires minimum time input with 100ns (typ) minimum glitch immunity.
I2C-Compatible Real-Time Clocks with Supervisor Controller
Negative-Going Transients MAX6909/MAX6910 relatively immune shortduration negative transients (glitches) while issuing resets during power-up, power-down, brownout conditions. Therefore, resetting when experiences only small glitches usually recommended. Maximum transient duration reset comparator overdrive (see Typical Operating Characteristics) shows maximum pulse period that occur which reset pulses generated. graph produced using negative-going pulses, starting 3.6V ending below reset threshold magnitude indicated (reset comparator overdrive). graph shows typical maximum pulse width negative-going transient have without causing reset. amplitude transient increases (i.e., goes farther below reset threshold), maximum allowable pulse width decreases. Typically, transient that goes 60mV below reset threshold lasts 60µs less does cause reset pulse issued. capacitor least 0.1µF mounted close provides additional transient immunity. Interfacing Microprocessors with Bidirectional Reset Pins Microprocessors with bidirectional reset pins, such Motorola 68HC11 series, contend with MAX6909/MAX6910 RESET RESET outputs. example, RESET output driven high wants pull low, indeterminate logic levels result. correct this, connect 4.7k resistor between RESET output reset shown Figure Buffer RESET output other system components. positive voltage supply RESET VCC. drops, then does this pin.
Battery-On Output
battery-on output, BATT open-drain output indicator when MAX6909/MAX6910 powered from backup battery input, BATT. When falls below reset threshold, VRST, below VBATT, switches from BATT BATT asserted. When rises above VBATT reset threshold, VRST, reconnects BATT deasserted.
MAX6909/MAX6910
Watchdog Input
MAX6909/MAX6910, watchdog circuit monitors µP's activity. Data configuration register controls selection watchdog timeout period. power-up default 1.6s then watchdog timeout period changed 200ms. Data configuration register watchdog enable function. logic disables watchdog function logic enables watchdog function. power-on reset state logic meaning watchdog function disabled. When first watchdog timeout period following reset cycle always 1.6s reverts 200ms after first transition. This allow recover after RESET interrupt. does toggle within register-selectable watchdog timeout period, RESET RESET asserted 200ms. same time, bits configuration register reset. These bits have rewritten enable watchdog short timeout function again. While RESET RESET asserted, control inputs MAX6909/MAX6910 disabled (MR, WDI, 2-wire interface). Figure shows watchdog timing relationship.
BUFFERED RESET OTHER SYSTEM VRST RESET 4.7k RESET tWDI tWDS
MAX6909/ MAX6910
RESET
RESET
Figure Interfacing Microprocessors with Bidirectional Reset
Figure Watchdog Timing Relationship
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
START
HIGH PROGRAM CODE
MAX6909/ MAX6910
CHIP-ENABLE OUTPUT CONTROL
SUBROUTINE PROGRAM LOOP
RESET GENERATOR
RETURN
Figure Watchdog Flow Diagram
Figure Chip-Enable Transmission Gate
Watchdog Software Considerations There help watchdog-timer monitor software execution more closely, which involves setting resetting watchdog input different points program rather than "pulsing" watchdog input high-low-high low-high-low. This technique avoids "stuck" loop, which watchdog timer continues reset within loop, keeping watchdog from timing out. Figure shows example driving watchdog input high beginning program, beginning every subroutine loop, then high again when program returns beginning. program should "hang" subroutine, problem would quickly corrected since continually watchdog timer allowed time out, causing reset issued.
Chip-Enable Signal Gating
Internal gating chip-enable (CE) signals prevents erroneous data from corrupting CMOS event undervoltage condition. MAX6909/MAX6910 transmission gate from OUT. During normal operation (reset asserted), transmission gate enabled passes transitions. When reset asserted, this path becomes disabled, preventing erroneous data from corrupting CMOS RAM. short propagation delay from enables MAX6909/MAX6910 used with most microprocessors. when reset asserts, remains typically tRCE permit completion current write cycle. Figure shows chip-enable transmission gate.
Chip-Enable Input transmission gate disabled high impedance (disabled mode) while reset asserted. During power-down sequence when goes below reset threshold, transmission gate disables, immediately becomes high impedance voltage logic high. logic when reset asserts, transmission gate disables moment goes high tRCE after reset asserts (tRCE), whichever occurs first (Figure 12). This permits current write cycle complete during power-down. transmission gate remains disabled remains high impedance (regardless activity) (tRP), reset timeout period time reset generated. While disabled, high impedance. When transmission gate enabled, impedance appears load series with load OUT. propagation delay through transmission gate depends VCC, source impedance driver connected loading OUT. propagation delay measured from point point using driver 10pF load capacitance (Figure 14), typically 5ns. minimum propagation delay, minimize capacitive load OUT, lowoutput-impedance driver. Chip-Enable Output When transmission gate enabled, impedance equivalent resistor series with source driving disabled mode, transmission gate active pullup connects (Figure 12). This pullup turns when transmission gate enabled.
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
VRST VRST VRST VRST
VBATT tRCE VBATT
RESET
Figure Chip-Enable Timing
tRCE
BATT 3.6V
MAX6909/ MAX6910
EQUIVALENT SOURCE IMPEDANCE CABLE 50pF
RESET
Figure Chip-Enable Timing Including
Power-Fail Comparator
MAX6909/MAX6910 compared internal reference. voltage less than power-fail threshold (VPFT), goes low. power-fail comparator intended undervoltage detector signal failing power supply monitor either positive negative supplies using voltage-divider (Figure 26). However, comparator does need dedicated this function because completely separate from rest circuitry. time VRST, forced low, regardless state PFI. time VRST RESET active (during reset timeout period), forced high, regardless state PFI. comparator unused, connect leave floating. Figure shows timing.
INCLUDES LOAD CAPACITANCE SCOPE PROBE CAPACITANCE.
Figure Propagation-Delay Test Circuit
VRST
VBATT tRST
RESET
VPFT
Figure Timing
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Piezo Transducer Output Drive
push-pull, piezo transducer drive output, PZT, selectable through configuration register frequencies 1.024kHz, 2.048kHz, 4.096kHz, 8.192kHz (Table Bits control which frequency outputs PZT. battery backup mode (when falls below reset threshold below VBATT), output disabled high impedance prevent battery drain from backup battery BATT pin. Table lists piezo transducer control bits. bit, selects whether ALM, alarm output, controls when selected frequency gated whether control given CNTL bit, then controls gating selected frequency PZT. When alarm triggered, selected frequency stays until alarm cleared writing reading from alarm configuration register. then CNTL bit, determines when long selected frequency appears PZT. CNTL bit, controls whether selected frequency gated PZT, provided gates selected frequency inhibits selected frequency (PZT remains low). Anytime frequency selected gated through output, modulated square wave. output then turns 0.5s 0.5s. Since human particularly sensitive changes condition, switching sound makes more noticeable than continuous sound same frequency. output swings between through output stage's on-resistance, ROUT_PZT. allow flexibility output work with many different types piezo buzzers, ROUT_PZT designed practical. minimize peak currents into piezo buzzer, external current-limiting resistor required. Ipeak equal ROUT_PZT). adjusted reduce sound amplitude from external piezo buzzer. value varies each application should chosen prototype design stage with piezo buzzer installed cavity approximating final housing. typical value ROUT_PZT calculated from VOUT IPZT, where IPZT average sink source currents. Figure piezo transducer functional diagram.
Table Piezo Transducer Selectable Frequencies
(PZT FREQ) (PZT FREQ) TYPICAL FREQUENCY (kHz) 1.024 2.048 4.096 8.19
MAX6909/ MAX6910
ROUT_PZT PIEZO BUZZER
VPZT
Figure Piezo Transducer Functional Diagram
Table Piezo Transducer Control Bits
(PZT SEL) (PZT CNTL) CNTL bit, control CNTL bit, control control, ignored; assume alarm triggered control, ignored; assume alarm cleared reading alarm configuration register CONDITION Selected frequency Selected frequency
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
START CONDITION tLOW (A7) (A6) (R/W) ACKNOWLEDGE STOP CONDITION
tSU:STA
1/fSCL
tBUF
tHD:STA
tSU:DAT
tHD:DAT
tVD:DAT
tSU:STO
Figure 2-Wire Timing Diagram
TIME_OUT_CLR 1Hz_CLK CNT_UP TIME_OUT
neous communication from microprocessor. Figure 2-wire timing diagram.
Timeout Feature
purpose timeout reset serial interface change line from output input, which releases line from being held low. This necessary when MAX6909/MAX6910 transmitting data become stuck logic low. line stuck low, other device able communicate. logic above, shown Figure intended illustrate timeout feature. transaction takes more than (minimum timout period), timeout condition occurs. When timeout condition observed, interface resets IDLE state waits transaction. order complete 31-byte burst read/write from before timeout, minimum frequency must 0.32kHz. valid start condition sets Time_Out_CLR counting begins. valid stop condition returns Time_Out_CLR disables up/down counter. Figure shows normal 2-wire operation. Figure illustrates what happens when line stuck clock cycles 1Hz_CLK during valid transaction. Depending when actual valid transaction begins relative CLK, timeout period either
CNT_DOWN
TIMEOUT RESET SERIAL INTERFACE TIMEOUT
Figure Timeout Simplified Functional Diagram
Crystal-Fail Output
open-drain, crystal-fail output, FAIL, alerts user when 32.768kHz crystal failed loss contiguous cycles, typical, 32.768kHz clock. FAIL enable (D7) alarm configuration register then crystal-fail detect circuit enabled; crystal-fail detect circuit disabled. When FAIL, status register crystal failure been detected FAIL, open-drain output, goes low. FAIL output FAIL status register both cleared reading status register.
Test Configuration Register
This read-only register.
2-Wire Interface
MAX6909/MAX6910 bidirectional 2-wire serial interface. lines SCL. Both lines must connected positive supply through individual pullup resistors. Data transfers only initiated when busy (both high). When less than VRST, communication with serial terminated inactive prevent erro-
Transfer
data transferred each clock pulse. data must remain stable during high portion clock pulse changes data during this time interpreted control signals (Figure 21).
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
1Hz_CLK
TIME_OUT_CLR
VALID START CONDITION
VALID STOP CONDITION
TIME_OUT
Figure Normal 2-Wire Operation
1Hz_CLK
TIME_OUT_CLR
VALID START CONDITION
VALID START CONDITION
TIME_OUT
RESET SERIAL INTERFACE
Figure Timeout 2-Wire Operation
DATA LINE STABLE; DATA VALID CHANGE DATA ALLOWED
START CONDITION
STOP CONDITION
Figure Transfer
Figure START STOP Conditions
I2C-Compatible Real-Time Clocks with Supervisor Controller
START STOP Conditions
Both remain high when busy. high-to-low transition SDA, while high, defined START condition. low-to-high transition data line while high defined STOP condition (Figure 22).
Address/Command Byte
command byte shown Figure (bit must logic zero, writes MAX6909/ MAX6910 disabled. specifies clock/calendar data logic data logic Bits through specify designated registers input output, (bit specifies write operation (input) logic read operation (output) logic command byte always input starting with (bit
MAX6909/MAX6910
Acknowledge
number data bytes between START STOP conditions transmitter receiver unlimited. Each 8-bit byte followed acknowledge bit. acknowledge high-level signal transmitter, during which time master generates extra acknowledge-related clock pulse. slave receiver that addressed must generate acknowledge after each byte receives. Also, master receiver must generate acknowledge after each byte receives that been clocked slave transmitter. device that acknowledges must pull down line during acknowledge clock pulse, that line stable during high period acknowledge clock pulse (setup hold times must also met). master receiver must signal data transmitter generating acknowledge last byte that been clocked slave. this case, transmitter must leave high enable master generate STOP condition.
Reading from Timekeeping Registers
timekeeping registers (seconds, minutes, hours, date, month, day, year) read either with single read burst read. century register only read with single read. Since real-time clock runs continuously read takes finite amount time, there possibility that clock counters could change during read operation, thereby reporting inaccurate timekeeping data. MAX6909/MAX6910, each clock register's data buffered latch. Clock register data latched 2-wire read command falling edge when slave acknowledge sent after address/command byte been sent master read timekeeping register). Collision-detection circuitry ensures that this does happen coincident with seconds counter update ensure accurate time data being read. This avoids time data changes during read operation. clock counters continue count keep accurate time during read operation. single reads used read each timekeeping registers individually, then necessary some error checking receiving end. potential error case when seconds counter increments before other registers read out. example, suppose carry 13:59:59 14:00:00 occurs during single read operations timekeeping registers. Then, data could become 14:59:59, which erroneous real-time data. prevent this with single-read operations, read seconds register first (initial seconds) store this value future comparison. When remaining timekeeping registers have been read out, read seconds register again (final seconds). initial seconds value check that final seconds value still not, repeat entire single-read process timekeeping registers. comparison initial seconds value with final seconds value indicate there delay problem reading timekeeping data (difference should always less). Using 100kHz speed, sequential single reads would take under 2.5ms read seven timekeeping registers, plus second read seconds register.
Slave Address Byte
Before data transmitted bus, device that should respond addressed first. first byte sent after start procedure address byte. MAX6909/MAX6910 slave transmitter/receiver. Therefore, only input clock signal bidirectional data line. slave address MAX6909/MAX6910 shown Figure
RD/W
Figure MAX6909/MAX6910 2-Wire Slave Address Byte
/CLK
Figure Address/Command Byte
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
most accurate read timekeeping registers burst read. burst read, main timekeeping registers (seconds, minutes, hours, date, month, day, year) control register read sequentially, order listed with seconds register first. They must read group eight registers, with bits each, proper execution burst read function. seven timekeeping registers latched upon receipt burst read command. Worst-case errors that occur between actual time read time assuming entire burst read done less than single write operations used write each timekeeping registers, then error checking needed. seconds register updated, update first then read back store value initial seconds. Update remaining timekeeping registers then read seconds register again (final seconds). initial seconds were ensure they still initial seconds were ensure that final seconds within initial seconds. seconds register written then read seconds register first save initial seconds. Write required timekeeping registers then read seconds register again (final seconds). initial seconds were ensure they still initial seconds were ensure that final seconds within initial seconds. Although both single writes burst writes possible, most accurate write timekeeping registers burst write. burst write, main timekeeping registers (seconds, minutes, hours, date, month, day, year) control register written sequentially. They must written group eight registers, with bytes each, proper execution burst write function. seven timekeeping registers simultaneously loaded into input buffer 2-wire write operation. worst-case error that occur between actual time write time update Figure shows MAX6909/MAX6910 data transfer.
Writing Timekeeping Registers
time date writing timekeeping registers (seconds, minutes, hours, date, month, day, year, century). avoid changing current time incomplete write operation, current time value buffered from being written directly timekeeping registers. timekeeping registers continue count, next rising edge seconds clock, data loaded into timekeeping registers. value will incremented next rising seconds clock. Collision-detection circuitry ensures that this does happen coincident with seconds register update ensure accurate time data being written. This avoids time data changes during write operation. incomplete write operation aborts time update procedure contents input buffer discarded.
ADDRESS/COMMAND BYTE 7.BIT 7-BIT SLAVE ADDRESS SINGLE WRITE ADDRESS/COMMAND BYTE 7.BIT 7-BIT SLAVE ADDRESS SINGLE READ ADDRESS/COMMAND BYTE 7.BIT 7-BIT SLAVE ADDRESS BURST WRITE ADDRESS/COMMAND BYTE 7.BIT 7-BIT SLAVE ADDRESS BURST READ 7.BIT 11111 7.BIT 11111 7.BIT ADDR 7.BIT ADDR
7.BIT 8_BIT DATA
7.BIT 7-BIT SLAVE
7.BIT 8_BIT DATA
7.BIT FIRST 8_BIT DATA
7.BIT LAST 8_BIT DATA
7.BIT 7-BIT SLAVE
7.BIT FIRST 8_BIT DATA
SLAVE ADDRESS: 1101000 ADDR: 5-BIT REGISTER ADDRESS RAM/REGISTER SELECTION BIT. WHEN REGISTER SELECTED; WHEN SELECTED. START CONDITION FROM MASTER READ CONDITION FROM MASTER ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MASTER
7.BIT LAST 8_BIT DATA
Figure MAX6909/MAX6910 Data Transfer
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
MAX6909/ MAX6910
MAX6909/ MAX6910
ACTIVE HIGH WHEN MONITORING NEGATIVE SUPPLY
VTRIP (VPFT VPFH)
VTRIP VPFT
VPFT
(VPFT VPFH)
NOTE: VTRIP NEGATIVE.
VTRIP
VTRIP
MONITORING NEGATIVE SUPPLY
MONITORING SECONDARY SUPPLY
Figure Using Power-Fail Comparator Monitor Additional Power Supplies
Applications Information
Monitoring Additional Power Supplies
connected that voltage activates RESET RESET (Figure 26). this configuration, when monitored voltage causes fall below VPFT, pulls low, causing reset asserted. 200ms reset generated, during which forced high released. 200ms reset, power-fail comparator reflects state PFI, which below VPFT, causes another reset.
Adding Hysteresis Power-Fail Comparator
power-fail comparator typical input hysteresis 30mV. This sufficient most applications where power-supply line being monitored through external voltage-divider supply (Figure 27). additional noise margin desired, connect resistor between (Figure 27(a)). Select ratio such that sees VPFT when falls trip point (VTRIP). adds additional hysteresis should typically more than times value hysteresis window extends both above (VH) below (VL) original trip point (VTRIP).
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
MAX6909/ MAX6910
MAX6909/ MAX6910
VTRIP VPFT (VPFT VPFH) (R1)
VTRIP VPFT
(VPFT VPFH)
VPFT
DIODE FORWARD-VOLTAGE DROP VTRIP
VTRIP
VTRIP
SYMMETRICAL HYSTERESIS
HYSTERESIS ONLY RISING
Figure Adding Hysteresis Power-Fail Comparator
Connecting ordinary signal diode series with (Figure 27(b)) causes lower trip point (VL) coincide with trip point without hysteresis TRIP), that entire hysteresis window occurs above VTRIP. This method provides additional noise margin without compromising accuracy power-fail threshold when monitored voltage falling. useful accurately detecting when voltage falls past threshold. current through should least ensure that 100nA (max over temperature) input current does shift trip point. should larger than does load down pin. Capacitor optional adds noise rejection.
Early Power-Fail Warning Using Input
Critical systems often require early warning indicating that power failing. This warning provides time store vital data take care additional "housekeeping" functions before power supply gets tolerance operate reliably. access unregulated supply feasible, power-fail comparator input (PFI) connected unregulated supply through voltage-divider, with power-fail comparator output (PFO) providing nonmaskable interrupt (NMI) (Figure 28).
I2C-Compatible Real-Time Clocks with Supervisor Controller
Configuration
UNREGULATED SUPPLY REGULATOR
MAX6909/MAX6910
VIEW
BATT RESET RESET
MAX6909/ MAX6910
BATT
MAX6909/ MAX6910
FAIL
Figure Using Power-Fail Comparator Generate Power-Fail Warning
Selector Guide
PART MAX6909EO30 MAX6909EO33 MAX6910EO30 MAX6910EO33 RESET THRESHOLD (TYP) 2.63 2.93 2.63 2.93 TRICKLE CHARGER
QSOP
Chip Information
TRANSISTOR COUNT: 35,267 PROCESS: BiCMOS
I2C-Compatible Real-Time Clocks with Supervisor Controller MAX6909/MAX6910
Typical Operating Circuit
VBATT 6.98k USER RESET BATT 3.3V 3.3V µCONTROLLER tr/CBUS VBATT 3.0V 0.1µF BATT RESET INTO CMOS 3.3V 3.3V MULTIFUNCTION ASIC 1µF* FAIL RESET RESET BATTERY-ON INDICATOR 150k
MAX6909/ MAX6910
3.3V CRYSTAL 3.3V 3.3V 0.01µF
FAIL
LOW-LEAKAGE CAPACITOR.
I2C-Compatible Real-Time Clocks with Supervisor Controller
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
MAX6909/MAX6910
21-0055
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

I2C-Compatible Real-Time Clocks with Supervisor Controller MAX690

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