MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 NOISE) Al
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3D7418
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7418 NOISE)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Auto-insertable (DIP pkg.) ground bounce noise Leading- trailing-edge accuracy Increment range: 0.25 through 5.0ns Delay tolerance: (See Table Temperature stability: typical (0C-70C) stability: typical (4.75V-5.25V) Minimum input pulse width: total delay Programmable 3-wire serial 8-bit parallel interface
SO/P0
PACKAGES
SO/P0
3D7418 3D7418G Gull Wing
3D7418S (300 Mil)
mechanical dimensions, click here.
FUNCTIONAL DESCRIPTION
3D7418 Programmable 8-Bit Silicon Delay Line product family consists 8-bit, user-programmable CMOS silicon integrated circuits. Delay values, programmed either serial parallel interface, varied over equal steps ranging from 250ps 5.0ns inclusively. Units have typical inherent (zero step) delay 12ns 17ns (See Table input reproduced output without inversion, shifted time user selection. 3D7418 TTL- CMOS-compatible, capable driving 74LS-type loads, features both rising- falling-edge accuracy.
DESCRIPTIONS
P0-P7 Signal Input Signal Output Mode Select Address Enable Parallel Data Input Serial Clock Serial Data Input Serial Data Output Volts Ground
all-CMOS 3D7418 integrated circuit been designed reliable, economic alternative hybrid programmable delay lines. offered standard 16-pin auto-insertable space saving surface mount 16-pin SOIC.
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7418-0.25 3D7418-0.5 3D7418-1 3D7418-2 3D7418-3 3D7418-4 3D7418-5
DELAYS TOLERANCES
Step Delay (ns) Step Delay (ns) 75.75 139.5 267.0 522.0 782.0 1037 1292 Delay Increment (ns) 0.25 0.15 0.50 0.25 1.00 0.50 2.00 1.00 3.00 1.50 4.00 2.00 5.00 2.50 Operating Frequency 6.25 3.15 1.56 0.78 0.52 0.39 0.31
INPUT RESTRICTIONS
Absolute Oper Freq Operating P.W. 80.0 160.0 320.0 640.0 960.0 1280.0 1600.0 Absolute Oper P.W. 11.0 22.0 44.0 66.0 88.0 110.0
NOTES: delay increment between 0.25 shown also available. delays referenced input
"2002 Data Delay Devices
#02005
6/17/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7418
APPLICATION NOTES
8-bit programmable 3D7418 delay line architecture comprised number delay cells connected series with their respective outputs multiplexed onto Delay (OUT) user-selected programming data. Each delay cell produces output replica signal present input, shifted time.
OPERATING PULSE WIDTH
Absolute Minimum Operating Pulse Width (high low) specification, tabulated Table determines smallest Pulse Width delay line input signal that reproduced, shifted time device output, with acceptable pulse width distortion. Minimum Operating Pulse Width (high low) specification determines smallest Pulse Width delay line input signal which output delay accuracy tabulated Table guaranteed. guarantee Table delay accuracy input pulse width smaller than Minimum Operating Pulse Width, 3D7418 must tested user operating pulse width. Therefore, facilitate production device identification, part number will include custom reference designator identifying intended frequency duty cycle operation. programmed delay accuracy device guaranteed, therefore, only user specified input characteristics. Small input pulse width variation about selected pulse width will only marginally impact programmed delay accuracy, all. Nevertheless, strongly recommended that engineering staff DATA DELAY DEVICES consulted.
INPUT SIGNAL CHARACTERISTICS
Frequency and/or Pulse Width (high low) operation adversely impact specified delay increment accuracy particular device. reasons dependency output delay accuracy input signal characteristics varied complex. Therefore Maximum Absolute Maximum operating input frequency Minimum Absolute Minimum operating pulse width have been specified.
OPERATING FREQUENCY
Absolute Maximum Operating Frequency specification, tabulated Table determines highest frequency delay line input signal that reproduced, shifted time device output, with acceptable duty cycle distortion. Maximum Operating Frequency specification determines highest frequency delay line input signal which output delay accuracy guaranteed. guarantee Table delay accuracy input frequencies higher than Maximum Operating Frequency, 3D7418 must tested user operating frequency. Therefore, facilitate production device identification, part number will include custom reference designator identifying intended frequency operation. programmed delay accuracy device guaranteed, therefore, only user specified input frequency. Small input frequency variation about selected frequency will only marginally impact programmed delay accuracy, all. Nevertheless, strongly recommended that engineering staff DATA DELAY DEVICES consulted.
SPECIAL HIGH ACCURACY REQUIREMENTS
Table delay increment accuracy specifications aimed meeting requirements majority applications encountered date. However, some systems place tighter restrictions accuracy parameter favor others. example, channel delay equalizing system concerned minimizing delay variations among various channels. Therefore, because inter channel skew delay difference, programmed delay tolerance need considerably decreased, while increment tolerance consequence. opposite true under-sampled multi-channel data acquisition system.
#02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7418
APPLICATION NOTES (CONT'D)
flexible 3D7418 architecture exploited conform these more demanding user-dictated accuracy constraints. However, facilitate production device identification, part number will include custom reference designator identifying user requested accuracy specifications operating conditions. strongly recommended that engineering staff DATA DELAY DEVICES consulted. order ensure that spurious outputs occur, essential that input signal idle (held high low) short duration prior updating programmed delay. This duration given maximum programmable delay. Satisfying this requirement allows delay line "clear" itself spurious edges. When address loaded, input signal begin switch (and delay will valid) after time given tPDV tEDV (see section below).
POWER SUPPLY TEMPERATURE CONSIDERATIONS
delay CMOS integrated circuits strongly dependent power supply temperature. monolithic 3D7418 programmable delay line utilizes novel innovative compensation circuitry minimize delay variations induced fluctuations power supply and/or temperature. thermal coefficient reduced PPM/C, which equivalent variation, over 0C-70 operating range, from room-temperature delay settings. power supply coefficient reduced, over 4.75V5.25V operating range, delay settings nominal 5.0VDC power supply and/or r2ns, whichever greater. essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred.
PROGRAMMED DELAY (ADDRESS) INTERFACE
Figure illustrates main functional blocks 3D7418 delay program interface. Since 3D7418 CMOS design, unused input pins must returned well defined logic levels, Ground.
TRANSPARENT PARALLEL MODE
eight program pins directly control output delay. change more program pins will reflected output delay after time tPDV, shown Figure register required programming data bused.
LATCHED PARALLEL MODE PULSED)
eight program pins loaded falling edge Enable pulse, shown Figure After each change delay value, settling time tEDV required before input accurately delayed.
PROGRAMMED DELAY (ADDRESS) UPDATE
delay line memory device. stores information present input time equal delay setting before presenting output with minimal distortion. 3D7418 8-bit programmable delay line represented serially connected delay elements (individually addressed programming data), each capable storing data time equal device increment (step time). delay line memory property, conjunction with operational requirement "instantaneously" connecting delay element addressed programming data output, inject spurious information onto output data stream.
SERIAL MODE
While observing data setup (tDSC) data hold (tDHC) requirements, timing data loaded MSB-to-LSB order rising edge clock (SC) while enable (AE) high, shown Figure falling edge enable (AE) activates delay value which reflected output after settling time tEDV. data shifted into serial data input (SI), previous contents 8-bit input register shifted serial output port (SO) MSB-to-LSB order, thus allowing cascading multiple devices connecting serial output (SO) preceding device serial data input
#02005
6/17/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7418
APPLICATION NOTES (CONT'D)
(SI) succeeding device, illustrated Figure total number serial data bits cascade configuration must eight times number units, each group eight bits must transmitted MSB-to-LSB order. initiate serial read, enable (AE) driven high. After time tEQV (MSB) valid serial output port (SO). first rising edge serial clock (SC), loaded with value present serial data input (SI), while presented serial output
SIGNAL
(SO). retrieve remaining bits seven more rising edges must generated serial clock line. read operation destructive. Therefore, desired that original delay setting remain unchanged, read data must written back device(s) before enable (AE) brought low. unused, must allowed float device configured serial programming mode.
PROGRAMMABLE DELAY LINE
SIGNAL
ADDRESS ENABLE
LATCH
SERIAL OUTPUT
SERIAL INPUT SHIFT CLOCK MODE SELECT
8-BIT INPUT REGISTER
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL INPUTS P0-P7 DELAY TIME
PREVIOUS VALUE
VALUE
tPDX
PREVIOUS VALUE
tPDV
VALUE
Figure Non-latched parallel mode (MD=1, AE=1)
ENABLE (AE)
tDSE
PARALLEL INPUTS P0-P7 DELAY TIME VALUE
tDHE
tEDX
PREVIOUS VALUE
tEDV
VALUE
Figure Latched parallel mode (MD=1)
#02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7418
APPLICATION NOTES (CONT'D)
ENABLE (AE)
CLOCK (SC)
tDSC
SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIME
tDHC
tEGV
tCQV
tCQX
tEQZ tEDV
VALUE
tEDX
PREVIOUS VALUE
Figure Serial mode (MD=0)
3D7418
3D7418
3D7418
FROM WRITING DEVICE
NEXT DEVICE
Figure Cascading Multiple Devices
TABLE DELAY PROGRAMMED ADDRESS
PARALLEL SERIAL STEP STEP STEP STEP STEP STEP STEP STEP STEP DELAY CHANGE PROGRAMMED ADDRESS NOMINAL DELAY (NS) 3D7418 DASH NUMBER -.25 12.00 12.0 12.25 12.5 12.50 13.0 12.75 13.5 13.00 14.0 13.25 14.5 75.25 75.50 75.75 63.75 138.5 139.0 139.5 127.5
1283 1287 1292 1275
#02005
6/17/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7418
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Static Supply Current* Input Threshold Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
4.75V 4.0V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/line (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Clock Frequency Enable Width Clock Width Data Setup Clock Data Hold from Clock Data Setup Enable Data Hold from Enable Enable Serial Output Valid Enable Serial Output High-Z Clock Serial Output Valid Clock Serial Output Invalid Enable Setup Clock Enable Hold from Clock Parallel Input Valid Delay Valid Parallel Input Change Delay Invalid Enable Delay Valid Enable Delay Invalid Input Pulse Width Input Period Input Output Delay SYMBOL tDSC tDHC tDSE tDHE tEQV tEQZ tCQV tCQX tPDV tPDX tEDV tEDX Period tPLH, tPHL UNITS Total Delay Total Delay NOTES
Table Table Table
NOTES: Refer PROGRAMMED DELAY (ADDRESS) UPDATE section
#02005
6/17/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7418
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1.25 Total Delay Period: PERIN Total Delay OUTPUT: Rload: Cload: Threshold: 10K: 1.5V (Rising Falling)
Device Under Test
10K:
Digital Scope
470:
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
2.4V 1.5V 0.6V
tFALL
2.4V 1.5V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.5V
1.5V
Figure Timing Diagram
#02005
6/17/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
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