Dual-Phase, Parallelable, Average Current-Mode Controllers MAX503

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Dual-Phase, Parallelable, Average Current-Mode Controllers MAX503

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19-2514; 8/04
Dual-Phase, Parallelable, Average Current-Mode Controllers
MAX5038/MAX5041 dual-phase, controllers provide high-output-current capability compact package with minimum number external components. MAX5038/MAX5041 utilize dual-phase, average current-mode control that enables optimal RDS(ON) MOSFETs, eliminating need external heatsinks even when delivering high output currents. Differential sensing enables accurate control output voltage, while adaptive voltage positioning provides optimum transient response. internal regulator enables operation with input voltage ranges +4.75V +5.5V +28V. high switching frequency, 500kHz phase, dual-phase operation allow low-output inductor values input capacitor values. This accommodates boardembedded planar magnetics achieving superior reliability, current sharing, thermal management, compact size, system cost. MAX5038/MAX5041 also feature clock input (CLKIN) synchronization external clock, clock output (CLKOUT) with programmable phase delay (relative CLKIN) paralleling multiple phases. MAX5038 offers variety factory-trimmed preset output voltages (see Selector Guide) MAX5041 offers adjustable output voltage from +1.0V +3.3V. MAX5038/MAX5041 operate over extended industrial temperature range (-40°C +85°C) available 28-pin SSOP package. Refer MAX5037 data sheet 9.0-compatible, VIDcontrolled output voltage controller 44-pin MQFP package.
Features
+4.75V +5.5V +28V Input Voltage Range Output Current Internal Voltage Regulator +12V +24V Power True Differential Remote Output Sensing Out-Of-Phase Controllers Reduce Input Capacitance Requirement Distribute Power Dissipation Average Current-Mode Control Superior Current Sharing Between Individual Phases Paralleled Modules Accurate Current Limit Eliminates MOSFET Inductor Derating Integrated Gate Drivers Selectable Fixed Frequency 250kHz 500kHz Phase 1MHz Phases) Fixed (MAX5038) Adjustable (MAX5041) Output Voltages 0.5% Accurate Reference (MAX5041B) External Frequency Synchronization from 125kHz 600kHz Internal with Clock Output Paralleling Multiple DC-DC Converters Thermal Protection 28-Pin SSOP Package
MAX5038/MAX5041
Applications
Servers Workstations Point-Of-Load High-Current/High-Density Telecom DC-DC Regulators Networking Systems Large-Memory Arrays RAID Systems High-End Desktop Computers
Ordering Information
PART TEMP RANGE PINPACKAGE SSOP SSOP SSOP SSOP SSOP SSOP SSOP OUTPUT VOLTAGE Fixed +1.2V Fixed +1.5V Fixed +1.8V Fixed +2.5V Fixed +3.3V +1.0V +3.3V +1.0V +3.3V
MAX5038EAI12 -40°C +85°C MAX5038EAI15 MAX5038EAI18 MAX5038EAI25 MAX5038EAI33 MAX5041EAI MAX5041BEAI -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Configuration appears data sheet. _Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
ABSOLUTE MAXIMUM RATINGS
SGND.-0.3V +30V BST_ SGND.-0.3V +35V .-0.3V [(VBST_ VLX_) 0.3V] PGND .-0.3V (VCC 0.3V) BST_ .-0.3V SGND.-0.3V PGND.-0.3V SGND PGND .-0.3V +0.3V Other Pins SGND.-0.3V (VCC 0.3V) Continuous Power Dissipation +70°C) 28-Pin SSOP (derate 9.5mW/°C above +70°C) .762mW Operating Temperature Range .-40°C +85°C Maximum Junction Temperature .+150°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +5V, circuit Figure -40°C +85°C, unless otherwise noted. Typical specifications +25°C.) (Note
PARAMETER SYSTEM SPECIFICATIONS Input Voltage Range Quiescent Supply Current Efficiency OUTPUT VOLTAGE MAX5038 only, load Nominal Output Voltage Accuracy MAX5038 only, load, +4.75V +5.5V +28V (Note MAX5041 only, load SENSE+ SENSE- Voltage Accuracy MAX5041 only, load, +4.75V +5.5V +28V MAX5041B only, load MAX5041B only, load, +28V STARTUP/INTERNAL REGULATOR Undervoltage Lockout Undervoltage Lockout Hysteresis Output Accuracy MOSFET DRIVERS Output Driver Impedance Output Driver Source/Sink Current Non-Overlap Time IDH_, IDL_ CDH_/DL_ high output +28V, ISOURCE 80mA 4.85 UVLO falling 4.15 5.30 -0.8 0.992 0.990 0.995 0.995 +0.8 1.008 1.010 1.005 1.005 Short together input operation SGND ILOAD (26A phase) 4.75 SYMBOL CONDITIONS UNITS
Dual-Phase, Parallelable, Average Current-Mode Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VCC +5V, circuit Figure -40°C +85°C, unless otherwise noted. Typical specifications +25°C.) (Note
PARAMETER OSCILLATOR Switching Frequency Lock Range Locking Time CLKOUT Phase Shift 125kHz) CLKIN Input Pulldown Current CLKIN High Threshold CLKIN Threshold CLKIN High Pulse Width PHASE High Threshold PHASE Threshold PHASE Input Bias Current CLKOUT Output Level CLKOUT Output High Level CURRENT LIMIT Average Current-Limit Threshold Cycle-by-Cycle Current Limit Cycle-by-Cycle Overload Response Time CURRENT-SENSE AMPLIFIER CSP_ CSN_ Input Resistance Common-Mode Range Input Offset Voltage Amplifier Gain Bandwidth Transconductance Open-Loop Gain Common-Mode Voltage Range DIFF Output Voltage Input Offset Voltage Amplifier Gain RCS_ VCMR(CS) VOS(CS) AV(CS) f3dB gmca AVOL(CE) VCMR(DIFF) VOS(DIFF) AV(DIFF) MAX5038/MAX5041 (+1.2V, +1.5V, +1.8V output versions) MAX5038 (+2.5V +3.3V output versions) VSENSE+ VSENSE- 0.997 0.495 load -0.3 1.003 0.505 -0.3 +1.0 +3.6 VCLPK CSP_ CSN_ CSP_ CSN_ (Note VCSP_ VCSN_ +150mV fPLL tPLL PHASE ISINK (Note CLKIN SGND CLKIN degrees PHASE unconnected PHASE SGND ICLKIN VCLKINH VCLKINL tCLKIN VPHASEH VPHASEL IPHASEBIA VCLKOUTL VCLKOUTH ISOURCE (Note SYMBOL CONDITIONS UNITS
MAX5038/MAX5041
CLKOUT
CURRENT-ERROR AMPLIFIER (TRANSCONDUCTANCE AMPLIFIER)
DIFFERENTIAL VOLTAGE AMPLIFIER (DIFF)
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
ELECTRICAL CHARACTERISTICS (continued)
(VCC +5V, circuit Figure -40°C +85°C, unless otherwise noted. Typical specifications +25°C.) (Note
PARAMETER Bandwidth Minimum Output Current Drive SENSE+ SENSE- Input Resistance Open-Loop Gain Unity-Gain Bandwidth Input Bias Current Error-Amplifier Output Clamping Voltage THERMAL SHUTDOWN Thermal Shutdown Thermal-Shutdown Hysteresis INPUT Input Voltage Input High Voltage Pullup Current VENL VENH TSHDN SYMBOL f3dB IOUT(DIFF) RVS_ CDIFF 20pF CONDITIONS UNITS
VOLTAGE-ERROR AMPLIFIER (EAOUT) AVOL(EA) fUGEA IB(EA) VEAN +2.0V -100 +100
VCLAMP(EA) With respect
Note Specifications from -40°C guaranteed characterization production tested. Note Guaranteed design. production tested. Note Peak-Current Comparator section.
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Typical Operating Characteristics
(Circuit Figure +25°C, unless otherwise noted.)
EFFICIENCY OUTPUT CURRENT INTERNAL OSCILLATOR FREQUENCY
MAX5038/41 toc01
EFFICIENCY OUTPUT CURRENT INPUT VOLTAGE
MAX5038/41 toc02
EFFICIENCY OUTPUT CURRENT
MAX5038/41 toc03
+12V
500kHz 250kHz
VOUT +1.8V IOUT
VOUT +1.8V 250kHz IOUT
+24V VOUT +1.8V 125kHz IOUT
EFFICIENCY OUTPUT CURRENT OUTPUT VOLTAGE
MAX5038/41 toc04
EFFICIENCY OUTPUT CURRENT OUTPUT VOLTAGE
MAX5038/41 toc05
SUPPLY CURRENT FREQUENCY INPUT VOLTAGE
12.0 11.5 11.0 10.5 (mA) 10.0 +12V
MAX5038/41 toc06
+12V 250kHz VOUT +1.1V VOUT +1.5V VOUT +1.8V
500kHz VOUT +1.1V VOUT +1.5V VOUT +1.8V
+24V
EXTERNALCLOCK DRIVER LOAD
IOUT
IOUT
FREQUENCY (kHz)
SUPPLY CURRENT TEMPERATURE FREQUENCY
MAX5038/41 toc07
SUPPLY CURRENT TEMPERATURE FREQUENCY
MAX5038/41 toc08
SUPPLY CURRENT LOAD CAPACITANCE DRIVER
(mA)
MAX5038/41 toc09
(mA) 250kHz
600kHz 500kHz
+12V CDL_ 22nF CDH_ 8.2nF
125kHz
(mA)
CDL_ 22nF CDH_ 8.2nF
TEMPERATURE (°C) CDRIVER (nF) +12V 250kHz
TEMPERATURE (°C)
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Typical Operating Characteristics (continued)
(Circuit Figure +25°C, unless otherwise noted.)
CURRENT-SENSE THRESHOLD OUTPUT VOLTAGE
MAX5038/41 toc10
OUTPUT VOLTAGE OUTPUT CURRENT ERROR GAIN RIN)
+12V VOUT +1.8V
12.5
MAX5038/41 toc11
DIFFERENTIAL AMPLIFIER BANDWIDTH
PHASE
MAX5038/41 toc12
(VCSP_ VCSN_) (mV)
1.85
PHASE (deg)
1.80
VOUT
VOUT PHASE PHASE
1.75
GAIN (V/V)
GAIN -135 -180 -225 -270 0.01 FREQUENCY (MHz)
1.70
1.65
1.60 ILOAD
DIFF OUTPUT ERROR SENSE+ SENSE- VOLTAGE
MAX5038/41 toc13
LOAD REGULATION INPUT VOLTAGE
MAX5038/41 toc14
LINE REGULATION
5.20 5.15 5.10 40mA
MAX5038/41 toc15
0.200 0.175 0.150 ERROR 0.125
+12V DRIVER
5.20 5.15 5.10 5.05 5.00 4.95 4.90 4.85 LOAD 4.80 +24V +12V
5.25
0.100 0.075 0.050 0.025 VSENSE
5.05 5.00 4.95 4.90 4.85 4.80 4.75
(mA)
LINE REGULATION
5.20 5.15 5.10 (ns) 5.05 5.00 4.95 4.90 4.85 4.80 4.75 80mA 10.0 11.0 12.0 13.0
MAX5038/41 toc16
DRIVER RISE TIME DRIVER LOAD CAPACITANCE
CDRIVER (nF)
MAX5038/41 toc17
DRIVER FALL TIME DRIVER LOAD CAPACITANCE
MAX5038/41 toc18
5.25
(ns)
+12V 250kHz
+12V 250kHz
CDRIVER (nF)
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Typical Operating Characteristics (continued)
(Circuit Figure +25°C, unless otherwise noted.)
LOCKING TIME 250kHz 350kHz 350kHz 250kHz MAX5038/41 toc21
CLKOUT 5V/div 350kHz 1.6A/div 1.6A/div PLLCMP 200mV/div 250kHz +12V CDH_ 22nF 100ns/div +12V CDL_ 22nF 100ns/div +12V LOAD 100µs/div
HIGH-SIDE DRIVER (DH_) SINK SOURCE CURRENT
MAX5038/41 toc19
LOW-SIDE DRIVER (DL_) SINK SOURCE CURRENT
MAX5038/41 toc20
LOCKING TIME 250kHz 500kHz 500kHz 250kHz MAX5038/41 toc22
CLKOUT 5V/div CLKOUT 5V/div
LOCKING TIME 250kHz 150kHz 150kHz 250kHz MAX5038/41 toc23
HIGH-SIDE DRIVER (DH_) RISE TIME
MAX5038/41 toc24
250kHz 500kHz PLLCMP 200mV/div 250kHz 100µs/div +12V LOAD PLLCMP 200mV/div 150kHz +12V LOAD 100µs/div +12V CDH_ 22nF 40ns/div
2V/div
HIGH-SIDE DRIVER (DH_) FALL TIME
MAX5038/41 toc25
LOW-SIDE DRIVER (DL_) RISE TIME
MAX5038/41 toc26
LOW-SIDE DRIVER (DL_) FALL TIME
MAX5038/41 toc27
2V/div
2V/div
2V/div
+12V CDH_ 22nF 40ns/div
+12V CDL_ 22nF 40ns/div
+12V CDL_ 22nF 40ns/div
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Typical Operating Characteristics (continued)
(Circuit Figure +25°C, unless otherwise noted.)
OUTPUT RIPPLE
MAX5038/41 toc28
INPUT STARTUP RESPONSE
MAX5038/41 toc29
VPGOOD 1V/div
VOUT (AC-COUPLED) 10mV/div
VOUT 1V/div
5V/div +12V VOUT +1.75V IOUT 500ns/div 2ms/div +12V VOUT +1.75V IOUT
ENABLE STARTUP RESPONSE
MAX5038/41 toc30
LOAD-TRANSIENT RESPONSE
MAX5038/41 toc31
VPGOOD 1V/div
VOUT 1V/div
VOUT 50mV/div
+12V VOUT +1.75V IOUT 1ms/div
2V/div
+12V VOUT +1.75V ISTEP tRISE 40µs/div
Dual-Phase, Parallelable, Average Current-Mode Controllers
Description
NAME CSP2, CSP1 CSN2, CSN1 PHASE PLLCMP CLP2, CLP1 SGND SENSE+ FUNCTION Current-Sense Differential Amplifier Positive Input. Senses inductor current. differential voltage between CSP_ CSN_ amplified internally current-sense amplifier gain Current-Sense Differential Amplifier Negative Input. Senses inductor current. Phase-Shift Setting Input. Connect PHASE 120°, leave PHASE unconnected 90°, connect PHASE SGND phase shift between rising edges CLKOUT CLKIN/DH1. External Loop-Compensation Input. Connect compensation network phase lock loop (see PhaseLocked Loop section). Current-Error Amplifier Output. Compensate current loop connecting network ground. Signal Ground. Ground connection internal control circuitry. Differential Output Voltage-Sensing Positive Input. Used sense remote load. Connect SENSE+ VOUT+ load. MAX5038 regulates difference between SENSE+ SENSE- according factory preset output voltage. MAX5041 regulates SENSE+ SENSE- difference +1.0V. Differential Output Voltage-Sensing Negative Input. Used sense remote load. Connect SENSE- VOUT- PGND load. Differential Remote-Sense Amplifier Output. DIFF output precision unity-gain amplifier. Voltage-Error Amplifier Inverting Input. Receives output differential remote-sense amplifier. Referenced SGND. Voltage-Error Amplifier Output. Connect external gain-setting feedback resistor. external error amplifier gain-setting resistors determine amount adaptive voltage positioning Output Enable. logic shuts down power drivers. internal pullup current. Boost Flying-Capacitor Connection. Reservoir capacitor connection high-side driver supply. Connect 0.47µF ceramic capacitors between BST_ LX_. High-Side Gate Driver Output. Drives gate high-side MOSFET. Inductor Connection. Source connection high-side MOSFETs. Also serves return terminal high-side driver. Low-Side Gate Driver Output. Synchronous MOSFET gate drivers phases. Internal Regulator Output. derived internally from voltage. Bypass SGND with 4.7µF 0.1µF ceramic capacitors. Supply Voltage Connection. Connect system. Connect input through lowpass filter, resistor 0.1µF ceramic capacitor. Power Ground. Connect PGND, low-side synchronous MOSFET's source, bypass capacitor returns together. Oscillator Output. CLKOUT phase-shifted from CLKIN amount specified PHASE. CLKOUT parallel additional MAX5038/MAX5041s. CMOS Logic Clock Input. Drive internal oscillator with frequency range between 125kHz 600kHz. frequency defaults internal oscillator CLKIN connected SGND. Connect CLKIN SGND internal oscillator 250kHz connect internal oscillator 500kHz. CLKIN internal pulldown current.
MAX5038/MAX5041
SENSEDIFF EAOUT BST1, BST2 DH1, LX1, DL1, PGND CLKOUT
CLKIN
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Functional Diagram
REGULATOR
UVLO TEMP SENSOR
INTERNAL CIRCUITS DRV_VCC SHDN
CSP1 CSN1 CLP1 SGND
CSP1 CSN1 CLP1
BST1
PHASE
MAX5038 MAX5041
CLKIN PHASELOCKED LOOP
GMIN PGND RAMP1
CLKOUT PLLCMP DIFF SENSEDIFF SENSE+ EAOUT ERROR DRV_VCC VREF VOUT VOUT 1.8V (MAX5038) VREF VOUT/2 VOUT 1.8V (MAX5038) VREF +1.0V (MAX5041) RAMP2 GMIN CLP2 CSN2 CSP2 CLP2 CSN2 CSP2 PHASE PGND BST2 SHDN 0.6V RAMP GENERATOR
PGND
Dual-Phase, Parallelable, Average Current-Mode Controllers
Detailed Description
MAX5038/MAX5041 (Figures average current-mode controllers drive out-of-phase buck converter channels. Average current-mode control improves current sharing between channels while minimizing component derating size. Parallel multiple MAX5038/MAX5041 regulators increase output current capacity. maximum ripple rejection input, phase shift between phases paralleled converters, three paralleled converters. Paralleling MAX5038/MAX5041s improves design flexibility applications requiring upgrades (higher load).
MAX5038/MAX5041
SENSE SENSE PHASE CSN1 CSP1 +12V CLKIN
C3-C7
MAX5038
PLLCMP BST1 +1.8V VOUT
DIFF EAOUT
C8-C11
C14,
C16-C24, LOAD
CLP1
BST2 CLP2
SGND PGND CSP2 CSN2
NOTE: TABLE COMPONENT VALUES.
Figure MAX5038 Typical Application Circuit, +12V
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Dual-phase converters with out-of-phase locking arrangement reduce input output capacitor ripple current, effectively multiplying switching frequency number phases. Each phase MAX5038/MAX5041 consists inner average current loop controlled common outer-loop voltageerror amplifier (VEA) that corrects output voltage errors. MAX5038/MAX5041 utilize single controlling average current mode force phase currents equal.
SENSE SENSE PHASE CSN1 CSP1 +12V CLKIN
C3-C7
MAX5041
PLLCMP BST1 DIFF EAOUT C8-C11 C14, C16-C24, LOAD +1.8V VOUT
CLP1
BST2 CLP2
SGND PGND CSP2 CSN2
NOTE: TABLE COMPONENT VALUES.
Figure MAX5041 Typical Application Circuit, +12V
Dual-Phase, Parallelable, Average Current-Mode Controllers
MAX5038/MAX5041 accept wide input voltage range +4.75V +5.5V +28V. internal control circuitry operates from internally regulated nominal voltage (VCC). input voltages greater, internal regulator steps voltage down +5V. output voltage regulates while sourcing 80mA. Bypass SGND with 4.7µF 0.1µF low-ESR ceramic capacitors highfrequency noise rejection stable operation (Figures Calculate power dissipation MAX5038/MAX5041 product input voltage total regulator output current (ICC). includes quiescent current (IQ) gate drive current (IDD): (QG1 QG4) where, total gate charge low-side high-side external MOSFETs, (typ), switching frequency each individual phase. applications utilizing input voltage, disable regulator connecting together.
Internal Oscillator
internal oscillator generates 180° out-of-phase clock signals required pulse-width modulation (PWM) circuits. oscillator also generates 2VP-P voltage ramp signals necessary comparators. Connect CLKIN SGND internal oscillator frequency 250kHz connect CLKIN internal oscillator 500kHz. CLKIN CMOS logic clock input phaselocked loop (PLL). When driven externally, internal oscillator locks signal CLKIN. rising edge CLKIN starts cycle PWM. Ensure that external clock pulse width least 200ns. CLKOUT provides phase-shifted output with respect rising edge signal CLKIN. PHASE sets amount phase shift CLKOUT. Connect PHASE 120° phase shift, leave PHASE unconnected phase shift, connect PHASE SGND phase shift with respect CLKIN. MAX5038/MAX5041 require compensation PLLCMP even when operating from internal oscillator. device requires active order generate proper clock signal required operation.
MAX5038/MAX5041
Control Loop
MAX5038/MAX5041 average current-mode control scheme regulate output voltage (Figures 3b). main control loop consists inner current loop outer voltage loop. inner loop controls output currents (IPHASE1 PHASE2 while outer loop controls output voltage. inner current loop absorbs inductor pole reducing order outer voltage loop that singlepole system. current loop consists current-sense resistor (RS), current-sense amplifier (CA_), current-error amplifier (CEA_), oscillator providing carrier ramp, comparator (CPWM_). precision amplifies sense voltage across factor inverting input CEA_ senses output. CEA_ output difference between voltage-error amplifier output (EAOUT) gainedup voltage from CA_. compensation network connected CLP1 CLP2 provides external frequency compensation respective CEA_. start every clock cycle enables high-side drivers initiates cycle. Comparator CPWM_ compares output voltage from CEA_ with ramp from oscillator. cycle terminates when ramp voltage exceeds error voltage.
Undervoltage Lockout (UVLO)/ Power-On Reset (POR)/Soft-Start
MAX5038/MAX5041 include undervoltage lockout with hysteresis power-on reset circuit converter turn-on monotonic rise output voltage. UVLO threshold internally between +4.0V +4.5V with 200mV hysteresis. Hysteresis UVLO eliminates "chattering" during startup. Most internal circuitry, including oscillator, turns when input voltage reaches +4V. MAX5038/MAX5041 draw current before input voltage reaches UVLO threshold. compensation network current error amplifiers (CLP1 CLP2) provides inherent soft-start output voltage. includes parallel combination capacitors (C28, C30) resistors (R5, series with other capacitors (C27, C29) (see Figures voltage CLP_ limits maximum current available charge output capacitors. capacitor CLP_ conjunction with finite output-drive current current-error amplifier yields finite rise time output current thus output voltage.
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
CSN1
CSP1
CLP1
CCFF
MAX5038
SENSE+ DIFF SENSERIN*
CEA1 CPWM1
IPHASE1 DRIVE
VOUT CEA2 CPWM2 DRIVE IPHASE2 COUT LOAD
VREF
CSN2
CSP2
CLP2
EXTERNAL MAX5038 FIGURE
CCCF
Figure MAX5038 Control Loop
CSN1
CSP1
CLP1
CCFF
MAX5041
SENSE+ DIFF SENSERIN*
CEA1 CPWM1
IPHASE1 DRIVE
VOUT CEA2 CPWM2 DRIVE IPHASE2 COUT LOAD
VREF +1.0V
CSN2
CSP2
CLP2
EXTERNAL MAX5041 FIGURE
CCCF
Figure MAX5041 Control Loop
Dual-Phase, Parallelable, Average Current-Mode Controllers
outer voltage control loop consists differential amplifier (DIFF AMP), reference voltage, VEA. unity-gain differential amplifier provides true differential remote sensing output voltage. differential amplifier output connects inverting input (EAN) VEA. noninverting input internally connected internal precision reference voltage. MAX5041 reference voltage +1.0V MAX5038 reference preset output voltage. controls inner current loops (Figures 3b). resistive feedback network gain required adaptive voltage-positioning circuit (see Adaptive Voltage Positioning section). Current-Sense Amplifier differential current-sense amplifier (CA_) provides gain maximum input offset voltage current-sense amplifier common-mode voltage range -0.3V +3.6V. current-sense amplifier senses voltage across current-sense resistor. Peak-Current Comparator peak-current comparator provides path fast cycle-by-cycle current limit during extreme fault conditions such output inductor malfunction (Figure Note that average current-limit threshold 48mV still limits output current during short-circuit conditions. prevent inductor saturation, select output inductor with saturation current specification greater than average current limit (48mV). Proper inductor selection ensures that only extreme conditions trip peak-current comparator, such cracked output inductor. 112mV voltage threshold triggering peak-current limit twice full-scale average current-limit voltage threshold. peak-current comparator delay only 260ns.
MAX5038/MAX5041
Current-Error Amplifier
Each phase MAX5038/MAX5041 dedicated transconductance current-error amplifier (CEA_) with typical 550µS 320µA output sink source current capability. current-error amplifier outputs, CLP1 CLP2, serve inverting input comparator. CLP1 CLP2 externally accessible provide frequency compensation inner current loops (Figures 3b). Compensate CEA_ such that inductor current down slope, which becomes slope inverting input comparator, less than slope internally generated voltage ramp (see Compensation section). Comparator Flip-Flop comparator (CPWM) sets duty cycle each cycle comparing output current-error amplifier 2VP-P ramp. start each clock cycle, flip-flop resets high-side driver (DH_) turns comparator sets flip-flop soon ramp voltage exceeds CLP_ voltage, thus terminating cycle (Figure
DRV_VCC
PEAK-CURRENT COMPARATOR 112mV CLP_ CSP_ CSN_ GMIN RAMP (V/s) 500µS COMPARATOR
BST_
SHDN
PGND
Figure Phase Circuit (Phase 1/Phase
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Differential Amplifier differential amplifier (DIFF AMP) facilitates output voltage remote sensing load (Figures 3b). provides true differential output voltage sensing while rejecting common-mode voltage errors highcurrent ground paths. Sensing output voltage directly load provides accurate load voltage sensing high-current environments. provides difference between differential amplifier output (DIFF) desired output voltage. differential amplifier bandwidth 3MHz. difference between SENSE+ SENSE- regulates preset output voltage MAX5038 regulates MAX5041. Voltage-Error Amplifier sets gain voltage control loop determines error between differential amplifier output internal reference voltage (VREF). VREF equals VOUT(NOM) +1.8V lower voltage versions MAX5038 VREF equals VOUT(NOM)/2 +2.5V +3.3V versions. MAX5041, VREF equals +1V. offset added output voltage MAX5038/MAX5041 with finite gain (RF/RIN) such that no-load output voltage higher than nominal value. Choose from Adaptive Voltage Positioning section following equations calculate no-load output voltage. MAX5038: VOUT(NL) VOUT(NOM MAX5041: VOUT(NL) following equations calculate value MAX5038 versions VOUT(NOM) +1.8V: [VCC (VNOM 0.6)] VNOM VNOM
MAX5038 versions VOUT(NOM) +1.8V: [2VCC (VNOM 1.2)] MAX5041: VREF output clamps +0.9V (plus commonmode voltage +0.6V), thus limiting average maximum current from individual phases. maximum average current-limit threshold each phase equal maximum clamp voltage divided gain (18) current-sense amplifier. This allows accurate settings average maximum current each phase. gain using amount output voltage positioning required discussed Adaptive Voltage Positioning section (Figures 3b). [VCC 1.6]
Adaptive Voltage Positioning
Powering new-generation processors requires techniques reduce cost, size, power dissipation. Voltage positioning reduces total number output capacitors meet given transient response requirement. Setting no-load output voltage slightly higher than output voltage during nominally loaded conditions allows larger downward voltage excursion when output current suddenly increases. Regulating lower output voltage under heavy load allows larger upward-voltage excursion when output current suddenly decreases. larger allowed, voltage-step excursion reduces required number output capacitors allows higher capacitors. Voltage positioning ability operate with multiple reference voltages require output regulate away from center value. Define center value voltage where output drops (VOUT/2) half maximum output current (Figure
where feedback resistor network (Figure Some applications require VOUT equal VOUT(NOM) load. ensure that output voltage does exceed nominal output voltage (VOUT(NOM)), resistor from EAN.
Dual-Phase, Parallelable, Average Current-Mode Controllers
Phase-Locked Loop: Operation Compensation
VCNTR VOUT/2
MAX5038/MAX5041
VCNTR
VCNTR VOUT/2
LOAD
LOAD LOAD
FULL LOAD
Figure Defining Voltage-Positioning Window
voltage-positioning window (VOUT) using resistive feedback VEA. following equations calculate voltage-positioning window MAX5038: VOUT
synchronizes internal oscillator external frequency source when driving CLKIN. Connecting CLKIN SGND forces frequency default internal oscillator frequency 500kHz 250kHz, respectively. uses conventional architecture consisting phase detector charge pump capable providing 20µA output current. Connect external series combination capacitor (C25) resistor (R4) parallel capacitor (C26) from PLLCMP SGND provide frequency compensation (Figure pole-zero pair compensation provides zero (C25 C26)] pole C26). following typical values compensating PLL: 7.5k, 4.7nF, 470pF. changing frequency, expect finite locking time approximately 200µs. MAX5038/MAX5041 require compensation PLLCMP even when operating from internal oscillator. device requires active order generate proper internal clocks.
VOLTAGE-POSITIONING WINDOW
MOSFET Gate Drivers (DH_, DL_)
high-side (DH_) low-side (DL_) drivers drive gates external N-channel MOSFETs (Figures drivers' high-peak sink source current capability provides ample drive fast rise fall times switching MOSFETs. Faster rise fall times result reduced cross-conduction losses. modern voltage-regulating module applications where duty cycle less than 50%, choose highside MOSFETs with moderate RDS(ON) very gate charge. Choose low-side MOSFETs with very DS(ON) moderate gate charge. driver block also includes logic circuit that provides adaptive non-overlap time prevent shootthrough currents during transition. typical non-overlap time 60ns between high-side low-side MOSFETs.
0.05
following equation calculate voltage-positioning window MAX5041:
VOUT
IOUT
(10)
0.05
(11)
BST_
powers low- high-side MOSFET drivers. Connect 0.47µF low-ESR ceramic capacitor between BST_ LX_. Bypass PGND with 4.7µF 0.1µF low-ESR ceramic capacitors. Reduce board area formed these capacitors, rectifier diodes between boost capacitor, MAX5038/MAX5041, switching MOSFETs.
where input feedback resistors VEA, current-loop gain current-sense resistor using lossless inductor current sensing, resistance inductor.
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Overload Conditions
Average current-mode control ability limit average current sourced converter during fault condition. When fault condition occurs, output clamps +0.9V with respect common-mode voltage (VCM +0.6V) compared with output current-sense amplifiers (CA1 CA2) (see Figures 3b). current-sense amplifier's gain limits maximum current inductor sense resistor ILIMIT 50mV/RS. examples discussed this data sheet pertain typical application with following specifications: +12V VOUT +1.8V IOUT(MAX) 250kHz Peak-to-Peak Inductor Current (IL) Table shows list recommended external components (Figure Table provides component supplier information.
Parallel Operation
applications requiring large output current, parallel three MAX5038/MAX5041s (six phases) triple available output current. paralleled converters operate same switching frequency different phases keep capacitor ripple currents minimum. Three parallel MAX5038/MAX5041 converters deliver 180A output current. phase shift on-board PLL, leave PHASE unconnected phase shift paralleled converters), connect PHASE SGND phase shift converters parallel). Designate converter master remaining converters slaves. Connect master slave controllers daisy-chain configuration shown Figure Connect CLKOUT from master controller CLKIN first slaved controller, CLKOUT from first slaved controller CLKIN second slaved controller. Choose appropriate phase shift minimum ripple currents input output capacitors. master controller senses output differential voltage through SENSE+ SENSE- generates DIFF voltage. Disable voltage sensing slaved controllers leaving DIFF unconnected (floating). Figure shows detailed typical parallel application circuit using MAX5038s. This circuit provides four phases input voltage +12V output voltage range +3.3V 104A.
Number Phases
Selecting number phases voltage regulator depends mainly ratio input-to-output voltage (operating duty cycle). Optimum output-ripple cancellation depends right combination operating duty cycle number phases. following equation starting point choose number phases: (12) where duty cycle VOUT/VIN. Choose make integer number. example, converting +12V +1.8V yields better ripple cancellation six-phase converter than four-phase converter. Ensure that output load justifies greater number components multiphase conversion. Generally limiting maximum output current phase yields most costeffective solution. maximum ripple cancellation occurs when K/D. Single-phase conversion requires greater size power dissipation external components such switching MOSFETs inductor. Multiphase conversion eliminates heatsink distributing power dissipation external components. multiple phases operating given phase shifts effectively increase switching frequency seen input/output capacitors, thereby reducing input/output capacitance requirement same ripple performance. lower inductance value improves large-signal response converter during transient load output. Consider these issues when determining number phases necessary voltage regulator application.
Applications Information
Each MAX5038/MAX5041 circuit drives 180° out-ofphase channels. Parallel three MAX5038/ MAX5041 circuits achieve four- six-phase operation, respectively. Figure shows typical application circuit two-phase operation. design criteria two-phase converter includes frequency selection, inductor value, input/output capacitance, switching MOSFETs, sense resistors, compensation network. Follow same procedure four- sixphase converter design, except input output capacitance. input output capacitance requirements vary depending operating duty cycle.
Inductor Selection
switching frequency phase, peak-to-peak ripple current each phase, allowable ripple output determine inductance value.
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
SENSE+ SENSEVCC PHASE
CSN1 CSP1
CLKIN
MAX5038/ MAX5041
DIFF
CSP2
CSN2 EAOUT PGND SGND CLKOUT
CLKIN
CSN1 CSP1
PHASE
MAX5038/ MAX5041
LOAD
DIFF
EAOUT CSP2 CSN2 PGND SGND CLKOUT
CLKIN
CSN1 CSP1
PHASE
MAX5038/ MAX5041
DIFF
EAOUT CSP2 CSN2 PGND SGND CLKOUT
*FOR MAX5041 ONLY.
OTHER MAX5038/MAX5041s
Figure Parallel Configuration Multiple MAX5038/MAX5041s
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
+12V 47µF 0.1µF
C3-C7 22µF 0.47µF 0.6µH 1.35m
PLLCMP
CLKIN
SENSE- SENSE+ CSN1 CSP1
BST1 0.1µF
4.7µF
OVPIN DIFF EAOUT 0.47µF MAX5038 (MASTER) 22µF C8-C11
0.6µH
1.35m
CLP1
CLP2 PGND SGND CLKOUT PHASE PGOOD CSN2 CSP2
BST2
PGOOD
C26-C30, 10µF LOAD C16-C25, C43-C46 270µF
C14, C15, C41, 100µF 0.1µF
VOUT +1.1V +3.3V 104A
C48-C51 22µF 0.47µF 0.6µH 1.35m
PLLCMP
CLKIN SENSE-SENSE+ CSN1 CSP1
BST1
MAX5038 (SLAVE) DIFF EAOUT
0.1µF
4.7µF
C52-C55 22µF 0.6µH 0.47µF 1.35m
CLP1
CLP2
PGND
SGND
PHASE
CSN2 CSP2
BST2
Figure Four-Phase Parallel Application Circuit (VIN +12V, VOUT +1.1V +3.3V 104A)
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Table Component List
DESIGNATION C3-C11 C12, C14, C16-C24, C26, C28, C27, DESCRIPTION 47µF,16V input-filter capacitors C5750X5R1C476M 22µF, input-filter capacitors C4532X5R1C226M 0.47µF, capacitors C1608X5R1A474K 100µF, 6.3V, output-filter capacitors Murata GRM44-1X5R107K6.3 270µF, output-filter capacitors Panasonic EEFUE0D271R 4700pF, capacitor Vishay-Siliconix VJ0603Y471JXJ 470pF capacitors Murata GRM1885C1H471JAB01 0.01µF capacitors Murata GRM188R71H103KA01 4.7µF capacitor Murata GRM40-034X5R475k6.3 0.1µF capacitors Murata GRM188R71C104KA01 Schottky diodes ON-Semiconductor MBRS340T3 Schottky diodes ON-Semiconductor MBR0520LT1 0.6µH, inductors Panasonic ETQP1H0R6BFX Upper-power MOSFETs Vishay-Siliconix Si7860DP Lower-power MOSFETs Vishay-Siliconix Si7886DP resistor Current-sense resistors, 2.7m resistors parallel, Panasonic ERJM1WSF2M7U 7.5k resistor resistors 4.99k resistor 37.4k resistors
Table Component Suppliers
SUPPLIER Murata Semiconductor Panasonic Vishay-Siliconix PHONE 770-436-1300 602-244-6600 714-373-7939 847-803-6100 1-800-551-6933 770-436-3030 602-244-3345 714-373-7183 847-390-4405 619-474-8920 WEBSITE www.murata.com www.on-semi.com www.panasonic.com www.tcs.tdk.com www.vishay.com
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Selecting higher switching frequencies reduces inductance requirement, cost lower efficiency. charge/discharge cycle gate drain capacitances switching MOSFETs create switching losses. situation worsens higher input voltages, since switching losses proportional square input voltage. 500kHz phase 250kHz less phase +12V. Although lower switching frequencies phase increase peak-to-peak inductor ripple current (IL), ripple cancellation multiphase topology reduces input output capacitor ripple current. following equation determine minimum inductance value: following equation determine worst-case inductor current each phase: 0.051 RSENSE
PEAK
(15)
where RSENSE sense resistor each phase.
Switching MOSFETs
when choosing MOSFET voltage regulators, consider total gate charge, RDS(ON), power dissipation, package thermal impedance. product MOSFET gate charge on-resistance figure merit, with lower number signifying better performance. Choose MOSFETs optimized high-frequency switching applications. average gate-drive current from MAX5038/ MAX5041 output proportional total capacitance drives from DH1, DH2, DL1, DL2. power dissipated MAX5038/MAX5041 proportional input voltage average drive current. section determine maximum total gate charge allowed from driver outputs together. gate charge drain capacitance (CV2) loss, cross-conduction loss upper MOSFET finite rise/fall time, loss current MOSFET RDS(ON) account total losses MOSFET. Estimate power loss (PDMOS_) high-side low-side MOSFETs using following equations: PDMOS
LMIN
(VINMAX VOUT VOUT
(13)
Choose equal about output current phase. Since affects output-ripple voltage, inductance value need minor adjustment after choosing output capacitors full-rated efficiency. Choose inductors from standard high-current, surface-mount inductor series available from various manufacturers. Particular applications require custom-made inductors. high-frequency core material custom inductors. High causes large peak-to-peak flux excursion increasing core losses higher frequencies. high-frequency operation coupled with high reduces required minimum inductance even makes planar inductors possible. advantages using planar magnetics include lowprofile design, excellent current-sharing between phases tight control parasitics, cost. example, calculate minimum inductance VIN(MAX) +13.2V, VOUT +1.8V, 10A, 250kHz:
(16) IOUT 1.4RDS(ON)
where RDS(ON), upper-switching MOSFET's total gate charge, on-resistance +25°C, rise time, fall time, respectively.
LMIN
13.2 250k
(13.2 1.8) 0.6µH
(14)
IRMS-HI
(17)
average current-mode control feature MAX5038/MAX5041 limits maximum peak inductor current which prevents inductor from saturating. Choose inductor with saturating current greater than worst-case peak inductor current.
where (IOUT IL)/2
Dual-Phase, Parallelable, Average Current-Mode Controllers
PDMOS
(18) 1.4R DS(ON)
Input Capacitors
discontinuous input-current waveform buck converter causes large ripple currents input capacitor. switching frequency, peak inductor current, allowable peak-to-peak voltage ripple reflected back source dictate capacitance requirement. Increasing number phases increases effective switching frequency lowers peak-to-average current ratio, yielding lower input capacitance requirement. input ripple comprised (caused capacitor discharge) VESR (caused capacitor). low-ESR ceramic capacitors with high ripple-current capability input. Assume contributions from capacitor discharge equal 70%, respectively. Calculate input capacitance required specified ripple using following equation: ESRIN
MAX5038/MAX5041
IRMS-LO
(19)
example, from typical specifications Applications Information section with VOUT +1.8V, high-side low-side MOSFET currents 9.9A 24.1A, respectively. Ensure that thermal impedance MOSFET package keeps junction temperature least 25°C below absolute maximum rating. following equation calculate maximum junction temperature: PDMOS (20)
IOUT
(VESR
(21)
Table Peak-to-Peak Output Ripple Current Calculations
NUMBER PHASES DUTY CYCLE EQUATION IP-P
IOUT
(22)
where IOUT total output current multiphase converter number phases. example, +1.8V, input capacitance calculated input peak-to-peak ripple 100mV less yielding capacitance value 200µF.
(VIN )(2D
Output Capacitors
worst-case peak-to-peak capacitor ripple current, allowable peak-to-peak output ripple voltage, maximum deviation output voltage during step loads determine capacitance requirements output capacitors. multiphase converter design, ripple currents from individual phases cancel each other lower ripple current. degree ripple cancellation depends operating duty cycle number phases. Choose right equation from Table calculate peak-to-peak output ripple given duty cycle two-, four-, six-phase converters. maximum ripple cancellation occurs when
2D)(4D 1)(3
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
allowable deviation output voltage during fast transient load dictates output capacitance ESR. output capacitors supply load step until controller responds with greater duty cycle. response time (tRESPONSE) depends closed-loop bandwidth converter. resistive drop across capacitor capacitor discharge causes voltage drop during step load. combination polymer ceramic capacitors better transient load ripple/noise performance. Keep maximum output voltage deviation less than equal adaptive voltage-positioning window (VOUT). Assume contribution each from output capacitance discharge drop. following equations calculate required capacitance value: ESROUT ISTEP COUT STEP RESPONSE (23)
Compensation
main control loop consists inner current loop outer voltage loop. MAX5038/MAX5041 average current-mode control scheme regulate output voltage (Figures 3b). IPHASE1 IPHASE2 inner average current loops. output provides controlling voltage these current sources. inner current loop absorbs inductor pole reducing order outer voltage loop that single-pole system. resistive feedback around provides best possible response, since there capacitors charge discharge during large-signal excursions, determine gain. following equation calculate value IOUT VOUT 0.05 (27)
(24)
(28)
where STEP load step RESPONSE response time controller. Controller response time depends control-loop bandwidth.
Current Limit
average current-mode control technique MAX5038/MAX5041 accurately limits maximum output current phase. MAX5038/MAX5041 sense voltage across sense resistor limit peak inductor current (IL-PK) accordingly. cycle terminates when current-sense voltage reaches 45mV (min). following equation calculate maximum current-sense resistor value: RSENSE 0.045 IOUT (25)
where current-loop gain number phases. When designing current-control loop ensure that inductor downslope (when becomes upslope output) does exceed ramp slope. This necessary condition avoid sub-harmonic oscillations similar those peak current-mode control with insufficient slope compensation. following equation calculate resistor RCF: VOUT RSENSE (29)
10-3 RSENSE
(26)
example, maximum RSENSE 1.35m. provides low-frequency pole while provides midband zero. Place zero obtain phase bump crossover frequency. Place high-frequency pole (fP) least decade away from crossover frequency achieve maximum phase margin.
where power dissipation sense resistors. Select lower value RSENSE compensate parasitics associated with board. Also, select non-inductive resistor with appropriate wattage rating.
Dual-Phase, Parallelable, Average Current-Mode Controllers
following equations calculate CCFF: (30)
VIEW
CSP2 CLKIN CLKOUT BST2
Configuration
MAX5038/MAX5041
CCFF
(31)
CSN2 PHASE PLLCMP CLP2 SGND CLP1 SENSE+ SENSE- DIFF EAOUT CSP1 CSN1
Board Layout
following guidelines layout switching voltage regulator. Place bypass capacitors close MAX5038/MAX5041. Minimize high-current loops from input capacitor, upper switching MOSFET, inductor, output capacitor back input capacitor negative terminal. Keep short current loop from lower switching MOSFET, inductor, output capacitor return source lower MOSFET. Place Schottky diodes close lower MOSFETs same side board. Keep SGND PGND isolated connect them single point close negative terminal input filter capacitor. current-sense lines very close each other minimize loop area. Similarly, remote voltage sense lines SENSE+ SENSE- close each other. cross these critical signal lines through power circuitry. Sense current right pads current-sense resistors. Avoid long traces between bypass capacitors, driver output MAX5038/MAX5041, MOSFET gates PGND pin. Minimize loop formed bypass capacitors, bootstrap diode, bootstrap capacitor, MAX5038/MAX5041, upper MOSFET gate. Place bank output capacitors close load.
MAX5038A MAX5041A
PGND BST1
SSOP
Distribute power components evenly across board proper heat dissipation. Provide enough copper area around switching MOSFETs, inductor, sense resistors thermal dissipation. least copper keep trace inductance resistance minimum. Thin copper boards compromise efficiency since high currents involved application. Also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
Chip Information
TRANSISTOR COUNT: 5431 PROCESS: BiCMOS
Dual-Phase, Parallelable, Average Current-Mode Controllers MAX5038/MAX5041
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.
SSOP.EPS
INCHES 0.068 0.002 0.010 0.078 0.008 0.015
MILLIMETERS 1.73 0.05 0.25 1.99 0.21 0.38 INCHES 0.239 0.239 0.278 0.317 0.397 0.249 0.249 0.289 0.328 0.407 MILLIMETERS 6.07 6.07 7.07 8.07 10.07 6.33 6.33 7.33 8.33 10.33
0.09 0.20 0.004 0.008 VARIATIONS 0.205 0.301 0.025 0.212 0.311 0.037 5.20 7.65 0.63 5.38 7.90 0.95 0.0256 0.65
NOTES: INCLUDE MOLD FLASH. MOLD FLASH PROTRUSIONS EXCEED (.006"). CONTROLLING DIMENSION: MILLIMETERS. MEETS JEDEC MO150. LEADS COPLANAR WITHIN 0.10
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP,
APPROVAL DOCUMENT CONTROL REV.
21-0056
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Dual-Phase, Parallelable, Average Current-Mode Controllers MAX503

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