Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
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ALDC1-40S-M Data Sheet
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02 November 1994
Microelectronics Division
ALDC1-40S-M Data Compression
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Design Notes Software Reset Software Reset (CMND equals X'A000') will reset ALDC Decoder Control Code Error (ERRS(1)) ALDC Decoder Error (ERRS(0)). Recommendations: Start Decompression (CMND equals X'6800') Start Decompression Output Disabled (CMND equals X'6C00') followed immediately Software Reset (CMND equals X'A000') will reset these errors. Hardware Reset will reset these errors. Peripheral Access Read When +M1BYTE Tied High
+MDATA(07:00) will equal X'00' peripheral access reads addresses (+ADDR(0) high) when +M1BYTE tied high.
Recommendation: Force ALDC1-40S-M +ADDR(0) using external logic necessary read peripheral device under these conditions. Recommended Busy Status (STAT(7)) ALDC1-40S-M Busy state whenever STAT(7)='1'B both Done AnyError status bits (STAT(0:1)) equal '0'B. Avoid writing opcodes other than Hold Software Reset into CMND register while ALDC1-40S-M Busy state.
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
Contents
Chapter Product Overview Distinctive Features Package Part Number Quality 1.4.1 Reliability
Resets Data Expansion 3.4.1 Worst Case Expansion
3-12 3-13 3-13 4-12 4-16 4-19 4-28 4-28 4-28 4-28 4-29
Chapter Functional Description Functional Areas 2.1.1 Microprocessor Interface 2.1.2 Original Data Interface Compressed Data Interface 2.1.3 Clock Generation 2.1.4 ALDC Encoder 2.1.5 ALDC Decoder Data Transfer Operations 2.2.1 General Data Transfer Sequencing 2.2.2 Start Compression Bypass 2.2.3 Start Compression 2.2.4 Start Decompression Bypass 2.2.5 Start Decompression 2.2.6 Start Decompression Output Disabled
Chapter Hardware Interface Timing Control Pins Microprocessor Interface Original Data Interface Compressed Data Interface 4.3.1 Four-edge Mode 4.3.2 Burst Mode 4.3.3 Synchronous Mode 4.3.4 Peripheral Access Mode 4.3.5 FIFO Operation 4.3.5.1 Four-edge Burst Devices 4.3.5.2 Four-edge Burst Controllers 4.3.6 Almost Full Almost Empty Clock Interface Chapter Description
Chapter Microprocessor Interface Registers 3.1.1 Status (STAT) 3.1.2 Original Data Interface Configuration (OCNF) Compressed Data Interface Configuration (CCNF) 3.1.3 Level (ECL) 3.1.4 Original Data Interface Polarity (OPOL) Compressed Data Interface Polarity (CPOL) 3.1.5 Original Data Interface Transfer Count (TCO) 3.1.6 Compressed Data Interface Transfer Count (TCC) 3.1.7 Error Status (ERRS) 3.1.8 Interrupt Status (INTS) 3.1.9 Command (CMND) 3.1.10 Transfer Size (XFR) 3-10 3.1.11 Data Disable Count (DDC) 3-10 3.1.12 Error Mask (EMSK) 3-11 3.1.13 Interrupt Mask (IMSK) 3-12 Interrupts 3-12
Chapter Electrical Characteristics Recommended Operating Conditions Absolute Maximum Minimum Ratings Characteristics Characteristics Clock Frequency Chapter Physical Dimensions Appendix Notation Significance Binary Numbers Hexadecimal Numbers Signal Names Byte Order Device Controller
Appendix ALDC Compression Products Contact Microelectronics Division
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ALDC1-40S-M Data Compression
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
Chapter Product Overview
ALDC stands Adaptive, Lossless, Data Compression. ALDC1-40S-M cost, high speed data compression product data storage data transmission applications. Using ALDC compression algorithm, ALDC1-40S-M achieve average compression ratio approximately 3:1. Many applications flexible ALDC1-40S-M hardware interface. Also, ALDC1-40S-M's hardware interface allows growth capability future.
Package
ALDC1-40S-M designed CMOS micron triple-level metal gate array/standard cell technology. ALDC1-40S-M body size. 144-lead plastic flat package with molded heat sink. 0.65 lead spacing. Section Chapter page gives detailed physical dimension information. Other packaging options available suit application system requirements.
Distinctive Features
ALDC1-40S-M single clock input. ALDC1-40S-M interfaces with common CMOS/TTL circuits. ALDC1-40S-M requires additional external memory single chip data compression solution. ALDC1-40S-M operates sustained speeds MB/s. Compression decompression data rates symmetrical. ALDC1-40S-M compresses decompresses data blocks 4,294,967,295 bytes. ALDC1-40S-M provides flexible microprocessor interface controlling microprocessor. microprocessor interface supports both polling-driven interrupt-driven applications. original data interface compressed data interface independently configurable interfaces. original data interface compressed data interface contain independently configurable sixteen-byte FIFO buffers. original data interface compressed data interface both support configurable eight-bit peripheral access transfers from microprocessor interface.
Part Number
Your Marketing Representative will help obtain ALDC1-40S-M. Original Equipment Manufacturer (OEM) catalog number ALDC1-40S-M IBM22-ALDC1040S-00. ALDC1-40S-M part number 63G9792.
Quality
ALDC1-40S-M Acceptable Quality Level (AQL) less. Customers with different requirements should contact your Marketing Representative. Customers should return module believed defective. will replace module confirmed defective manufacturing tests. encourage return defective modules. failure analysis results obtained from these modules help improve quality products.
1.4.1 Reliability
reliability objective end-of-life Average Failure Rate (AFR) equal less than PPM/KPOH nominal temperature voltage conditions. This includes Early Failure Rate (EFR) contribution equal less than PPM/KPOH. Customers with different requirements should contact your Marketing Representative.
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ALDC1-40S-M Data Compression
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Chapter Functional Description
ALDC1-40S-M provides microprocessor interface, original data interface, compressed data interface, clock input. Internal ALDC1-40S-M ALDC encoder, ALDC decoder, ALDC1-40S-M registers. Figure illustrates these functional areas.
Device/Controller
Interface Original Data Interface
page describes ALDC1-40S-M registers detail.
2.1.2 Original Data Interface Compressed Data Interface
original data interface compressed data interface identically designed. They always discussed together this document. original data interface accepts data compression provides decompressed data connected compressed data interface accepts compressed data decompression from connected provides compressed data bus. original data interface counts bytes original data received during compression operations bytes decompressed data sent during decompression operations. This count available Original Data Interface Transfer Count (TCO) register. compressed data interface counts bytes compressed data received during decompression operations bytes compressed data sent during compression operations. This count available Compressed Data Interface Transfer Count (TCC) register. original data interface compressed data interface both buffer data during data transfer operations sixteen-byte FIFO's. Section page describes original data interface compressed data interface detail.
Registers
ALDC Encoder ALDC Decoder
clock Clock Generation
Compressed Data Interface
Device/Controller
Figure
2-1. ALDC1-40S-M High-level Functional Units
Functional Areas
2.1.1 Microprocessor Interface
microprocessor interface allows microprocessor query status control ALDC1-40S-M. ALDC1-40S-M registers externally accessible through microprocessor interface. These registers provide primary means which ALDC1-40S-M microprocessor communicate. Section page describes microprocessor interface timing detail. Section
2.1.3 Clock Generation
clock generation circuitry accepts single clock input. generates internal clocks necessary ALDC1-40S-M function. Section page 4-29 describes clock timing detail.
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2.1.4 ALDC Encoder
ALDC encoder accepts data bytes from original data interface provides compressed data bytes compressed data interface. ALDC implementation adaptive Lempel-Ziv lossless compression algorithm accomplishes this function. ALDC encoder contains 512-byte content addressable memory (CAM). history buffer during compression operations. ALDC encoder concatenates marker control code compressed data. also pads remaining bits with zeros align evenly byte boundary.
desired application. transfer size bytes loaded into appropriate microprocessor interface register. transfer proceeds until specified number bytes processed, hardware software reset occurs, error occurs, hold opcode occurs. After data transfer operation ended (either successfully unsuccessfully), microprocessor prepares ALDC1-40S-M next data transfer operation. Note: Interrupts disabled setting ALDC1-40S-M Interrupt Mask register X'FFFF'. interrupts disabled, then microprocessor must poll correct status bits determine progress outcome data transfer operation.
2.1.5 ALDC Decoder
ALDC decoder accepts compressed data bytes from compressed data interface provides reconstructed data bytes original data interface. ALDC implementation adaptive Lempel-Ziv lossless compression algorithm accomplishes this function. ALDC decoder contains 512-byte random access memory (RAM). history buffer during decompression operations. ALDC decoder expects find marker control code final data received from compressed data interface. does detect marker control code, then asserts ALDC decoder error. detects marker control code, then strips marker control code from decompressed data stream.
2.2.1 General Data Transfer Sequencing
This general control sequence which occurs during data transfer operations: history buffer cleared, transfer count registers reset X'000000', error status register reset X'0000', status register X'0080' (ie. Busy). original data interface compressed data interface enabled send receive data appropriate. Also, encoder decoder bypass paths appropriate. Data received processed until data reached. During processing, output data sent becomes available. When data reached sending interface, interrupt outputs asserted Done (STAT(0)) '1'. Exception Conditions: following exception conditions prevent general data transfer sequence from completing: error occurs during data transfer operation, then interrupt output immediately asserted; Error (STAT(1)) '1'; proper error status (ERRS) register also '1'; transfer ended. Depending type error, microprocessor attempt retry current
Data Transfer Operations
data transfer operations describe data transferred between original data interface compressed data interface. microprocessor interface controls internal sequencing ALDC1-40S-M accomplish data transfer operations. data transfer operations started when appropriate data transfer command decoded command register. Data transfer operations typically involve blocks data bytes. These blocks either have fixed variable length depending
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transfer, reset ALDC1-40S-M (and retry transfer), and/or report failure. hold opcode occurs during data transfer operation, then interrupt output asserted Hold (STAT(6)) after current processing step. microprocessor later time issue resume opcode continue data transfer operation. Note: resume opcode must come directly after hold opcode. hardware reset reset opcode occurs during data transfer operation, then history buffer cleared, microprocessor interface registers reset X'0000' appropriate, transfer ended.
2.2.4 Start Decompression Bypass
compressed data interface receives data from external compressed data sends decoder bypass. decoder bypass sends data without modification original data interface. original data interface sends unaltered data external original data bus.
2.2.5 Start Decompression
compressed data interface receives compressed data from external compressed data sends decoder bypass. decoder bypass sends data ALDC decoder. ALDC decoder decompresses data sends decoder bypass (using different port). decoder bypass sends decompressed data original data interface. original data interface sends decompressed data external original data bus.
2.2.2 Start Compression Bypass
original data interface receives data from external original data sends encoder bypass. encoder bypass sends data without modification compressed data interface. compressed data interface sends original data external compressed data bus.
2.2.6 Start Decompression Output Disabled
compressed data interface receives compressed data from external compressed data sends decoder bypass. decoder bypass sends data ALDC decoder. ALDC decoder decompresses data sends decoder bypass (using different port). decoder bypass sends decompressed data original data interface. original data interface counts decompressed bytes does send decompressed data external original data until Original Data Interface Transfer Count (TCO) register greater than Data Disable Count (DDC) register. When greater than DDC, original data interface sends remaining decompressed data external original data bus. Note: OCNF(10) number, then when equals original data interface sends remaining decompressed data external original data bus. This done maintain proper byte alignment.
2.2.3 Start Compression
original data interface receives data from external original data sends encoder bypass. encoder bypass sends data ALDC encoder. ALDC encoder compresses data sends encoder bypass (using different port). encoder bypass sends compressed data compressed data interface. compressed data interface sends compressed data external compressed data bus.
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Chapter Microprocessor Interface
Registers
Each register bytes wide. When +M1BYTE tied low, +ADDR(0) used. Data read written using +MDATA(15:00). When +M1BYTE tied high, +ADDR(0) used select eight bits which will read written +MDATA(07:00). this case, when +ADDR(0) equals then eight least significant register bits through read written. When +ADDR(0) equals '1', then eight most significant register bits through read written.
Figure
(Page Register Summary
+ADDR(4:1) X'0'
MNEMONIC STAT OCNF CCNF
REGISTER NAME Status
(See note
PAGE 3-10 3-10 3-10 3-10 3-11
Original Data Interface Configuration (See note Compressed Data Interface Configuration (See note Level
(See note (See note
X'1'
OPOL CPOL
Original Data Interface Polarity Compressed Data Interface Polarity (See note Original Data Interface Transfer Count High (See note Original Data Interface Transfer Count (See note Compressed Data Interface Transfer Count High (See note Compressed Data Interface Transfer Count (See note Error Status Command Reserved Transfer Size High Transfer Size Data Disabled Count High Data Disabled Count Error Mask
(See note (See note
X'2' X'3' X'4' X'5' X'6' X'7' X'8' X'9' X'C' X'D' X'E'
TCOH TCOL TCCH TCCL ERRS INTS CMND XFRH XFRL DDCH DDCL EMSK
Interrupt Status
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Figure
(Page Register Summary
+ADDR(4:1) X'F'
Notes:
MNEMONIC IMSK
REGISTER NAME Interrupt Mask
PAGE 3-12
When CMND equal X'C100', X'C200', X'C400', X'C800'. When CMND equals X'C100'. When CMND equals X'C200'.
3.1.1 Status (STAT)
Status register provides status bits microprocessor. STAT reset X'0000' hardware software reset. This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'0' read STAT. When +M1BYTE tied high, +ADDR(4:0) equals X'00' read STAT(7:0); +ADDR(4:0) equals X'01' read STAT(15:8).
Figure (Page STAT
Figure
(Page STAT
NAME/NOTES Output Disabled This when original data interface output disabled. reset when original data interface output re-enabled when reset occurs. Note: Start Decompression Output Disabled (CMND equals X'6C00') opcode Data Disabled Count (DDC) register used control original data interface output disabling.
Bypass This when compression decompression disabled. reset when compression decompression re-enabled when reset occurs. Note: Start Compression Bypass (CMND equals X'5000') Start Decompression Bypass (CMND equals X'6000') opcodes used control compression decompression disabling.
15:8
NAME/NOTES Reserved Busy This when data transfer operation initiated microprocessor. reset when data transfer operation completes successfully, when unmasked error occurs, when reset occurs, when hold opcode issued microprocessor. Important! ALDC1-40S-M Design Note page
Expansion This when Compressed Data Interface Transfer Count (TCC) register larger than Transfer Size (XFR) register compression operation. reset when another data transfer operation begins when reset occurs. section page 3-13 discussion data expansion.
Hold This when data transfer operation currently held. reset when held data transfer operation resumed when reset occurs.
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Figure
(Page STAT
NAME/NOTES Interrupt This when unmasked interrupt occurs. reset when data transfer operation begins when reset occurs. Notes: Interrupt Status (INTS) register used determine cause interrupt. Interrupt Mask (IMSK) register used control which interrupts masked.
OCNF only accessable when CMND equal X'C100'; CCNF when CMND equal X'C200'. Note: Original Data Interface Configuration (OCNF) Compressed Data Interface Configuration (CCNF) registers independently configurable. discussion below, these registers called xCNF register, where replaced only only, appropriate. When +M1BYTE tied low, +ADDR(4:1) equals X'0' read write xCNF. When +M1BYTE tied high, +ADDR(4:0) equals X'00' read write xCNF(7:0); +ADDR(4:0) equals X'01' read write xCNF(15:8).
Figure (Page xCNF
Error This when unmasked error occurs. reset when data transfer operation begins when reset occurs. Notes: Error Status (ERRS) register used determine cause error. Error Mask (EMSK) register used control which errors masked. NAME/NOTES Parity When '1', parity checking enabled +xDATA(15:00) data bus. When reset '0', parity checking disabled +xDATA(15:00) data bus. Notes: (xCNF(14)) determines even parity used. Byte (xCNF(10)) determines parity checked generated only +xPARITY(0) (for +xDATA(07:00)) both +xPARITY(1:0) (for +xDATA(15:00)). When '1', parity checking generation used +xDATA(15:00) data bus. When reset '0', even parity checking generation used +xDATA(15:00) data bus. Note: This only meaning Parity (xCNF(15)) '1'.
Done This when current data transfer operation complete. reset when data transfer operation begins when reset occurs.
3.1.2 Original Data Interface Configuration (OCNF) Compressed Data Interface Configuration (CCNF)
Original Data Interface Configuration register provides original data interface configuration capability microprocessor. Compressed Data Interface Configuration register provides compressed data interface configuration capability microprocessor. OCNF CCNF reset X'0000' hardware reset.
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Figure
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
Figure
(Page xCNF
(Page xCNF
NAME/NOTES Controller When '1', original data interface compressed data interface) acts controller. When reset '0', original data interface compressed data interface) acts device. Note: This only meaning xCNF(12) '0'.
NAME/NOTES Wait States These bits configure number wait states used during original data interface compressed data interface) peripheral access. values '001' through '111' valid. Notes: reset value (B'000') Wait States bits will cause improper operation original data interface (compressed data interface) during peripheral access. peripheral access will used original data interface compressed data interface), then these bits must valid value after every hardware reset. These bits only have meaning during original data interface compressed data interface) peripheral access.
12:11
Mode These bits configure interface communication protocol original data interface. values '00' through '11' defined below: '00' Four-edge communication. This default value after reset. Burst communication. Synchronous communication. Reserved.
'01' '10' '11' Byte
When '1', +xDATA(15:00) (and +xPARITY(1:0) original data interface compressed data interface) parity checking enabled) used. When reset '0', +xDATA(07:00) (and +xPARITY(0) original data interface compressed data interface) parity checking enabled) used. Reserved
FIFO Threshold These bits configure original data interface compressed data interface) FIFO threshold value. Values from '0000' '1111' valid. Note: When these bits reset '0000', original data interface compressed data interface) FIFO operates threshold X'1'.
3.1.3 Level (ECL)
Level register provides engineering change information bits microprocessor. never reset. This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'1' read ECL.
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Figure 3-5. xPOL
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When +M1BYTE tied high, +ADDR(4:0) equals X'02' read ECL(7:0); +ADDR(4:0) equals X'03' read ECL(15:8).
Figure 3-4.
NAME/NOTES
15:0
NAME/NOTES Level ALDC1-40S-M, value these bits '00000000 11000001'.
xCIN(1) xCOUT(0) xCOUT(1) xCOUT(2) xCOUT(3) xCOUT(4) xCOUT(5)
3.1.4 Original Data Interface Polarity (OPOL) Compressed Data Interface Polarity (CPOL)
Original Data Interface Polarity register provides original data interface polarity configuration capability microprocessor. Compressed Data Interface Polarity register provides compressed data interface polarity configuration capability microprocessor. OPOL CPOL reset X'00FF' hardware reset. OPOL only accessable when CMND equal X'C100'; CPOL when CMND equal X'C200'. Note: Original Data Interface Polarity (OPOL) Compressed Data Interface Polarity (CPOL) registers independently configurable. discussion below, these registers called xPOL register, where replaced only only, appropriate. When +M1BYTE tied low, +ADDR(4:1) equals X'1' read write xPOL. When +M1BYTE tied high, +ADDR(4:0) equals X'02' read write xPOL(7:0); +ADDR(4:0) equals X'03' read write xPOL(15:8). xPOL position will program corresponding control polarity positive active. will program corresponding control polarity negative active.
Figure 3-5. xPOL
3.1.5 Original Data Interface Transfer Count (TCO)
Original Data Interface Transfer Count register provides status information number bytes transferred current data transfer operation. Original Data Interface Transfer Count (TCO) four byte register with most significant bytes contained Original Data Interface Transfer Count High (TCOH) least significant bytes contained Original Data Interface Transfer Count (TCOL). TCOL TCOH reset X'0000' hardware software reset. This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'2' read TCOH +ADDR(4:1) equals X'3' read TCOL. When +M1BYTE tied high, +ADDR(4:0) equals X'04' read TCOH(7:0); +ADDR(4:0) equals X'05' read TCOH(15:8); +ADDR(4:0) equals X'06' read TCOL(7:0); +ADDR(4:0) equals X'07' read TCOL(15:8). During compression operation, incremented each original data byte received original data interface. When equals during compression, bytes compression operation have been received ALDC1-40S-M. During decompression operation, incremented each decompressed data byte sent original data interface.
15:8
NAME/NOTES Reserved
xCIN(0)
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Notes: OCNF(10) reset '0', then will always increment each byte received. OCNF(10) '1', then will increment each pair bytes received. data transfer operation, when OCNF(10) '1', there possibility that only byte will required complete transfer (ie. when number bytes transferred). this case, will incremented byte received. Because time needed complete outstanding compression operations final bytes received during compression, cannot used determine when compression operation complete. Done (STAT(0)) used this purpose. thirty-two register. Attempting transfer gigabytes more data will result register overflow. Therefore, application system designer must ensure that data partitioned into data blocks smaller than gigabytes, that each data block compressed decompressed separately.
Figure 3-6.
This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'4' read TCCH +ADDR(4:1) equals X'5' read TCCL. When +M1BYTE tied high, +ADDR(4:0) equals X'08' read TCCH(7:0); +ADDR(4:0) equals X'09' read TCCH(15:8); +ADDR(4:0) equals X'0A' read TCCL(7:0); +ADDR(4:0) equals X'0B' read TCCL(15:8). During decompression operation, incremented each compressed data byte received compressed data interface. When equals during decompression, bytes decompression operation have been received ALDC1-40S-M. During compression operation, incremented each compressed data byte sent compressed data interface. Notes: CCNF(10) reset '0', then will always increment each byte received. CCNF(10) '1', then will increment each pair bytes received. data transfer operation, when CCNF(10) '1', there possibility that only byte will required complete transfer (ie. when number bytes transferred). this case, will incremented byte received. Because time needed complete outstanding decompression operations final bytes received during decompression, cannot used determine when decompression operation complete. Done (STAT(0)) used this purpose. thirty-two register. Attempting transfer gigabytes more data will result register overflow. Therefore, application system designer must ensure that data partitioned into data blocks smaller than gigabytes, that each data block compressed decompressed separately.
31:16 15:0
NAME/NOTES Original Data Interface Transfer Count High (TCOH) Original Data Interface Transfer Count (TCOL)
3.1.6 Compressed Data Interface Transfer Count (TCC)
Compressed Data Interface Transfer Count register provides status information number bytes transferred current data transfer operation. Compressed Data Interface Transfer Count (TCC) four byte register with most significant bytes contained Compressed Data Interface Transfer Count High (TCCH) least significant bytes contained Compressed Data Interface Transfer Count (TCCL). TCCL TCCH reset X'0000' hardware software reset.
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Figure
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Figure
3-7.
(Page ERRS
31:16 15:0
NAME/NOTES Compressed Data Interface Transfer Count High Compressed Data Interface Transfer Count
NAME/NOTES Microprocessor Interface Parity Error This when parity error detected during microprocessor write +MDATA(15:00) +MENABLEP tied high. reset when data transfer operation begins when reset occurs.
3.1.7 Error Status (ERRS)
Error Status register provides error status bits microprocessor. ERRS reset X'0000' hardware software reset. This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'6' read ERRS. When +M1BYTE tied high, +ADDR(4:0) equals X'0C' read ERRS(7:0); +ADDR(4:0) equals X'0D' read ERRS(15:8).
Figure (Page ERRS
Compressed Data Interface Transfer Count (TCC) Overflow Error This when carry detected Compressed Data Interface Transfer Count (TCC) register. reset when data transfer operation begins when reset occurs.
Original Data Interface Transfer Count (TCO) Overflow Error This when carry detected Original Data Interface Transfer Count (TCO) register. reset when data transfer operation begins when reset occurs.
15:7
NAME/NOTES Reserved Original Data Interface Parity Error This when parity error detected during transfer into +ODATA(15:00) original data interface Parity (OCNF(15)) '1'. reset when data transfer operation begins when reset occurs.
ALDC Decoder Control Code Error This during decompression when invalid control code detected compressed data stream. reset when data transfer operation begins when reset occurs. Important! ALDC1-40S-M Design Note page
Compressed Data Interface Parity Error This when parity error detected during transfer into +CDATA(15:00) compressed data interface Parity (CCNF(15)) '1'. reset when data transfer operation begins when reset occurs.
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Figure
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
Figure
(Page ERRS
3-9. INTS
NAME/NOTES ALDC Decoder Error This during decompression when control code detected while Compressed Data Interface Transfer Count (TCC) less than Transfer Size (XFR) when equals control code detected compressed data stream. reset when data transfer operation begins when reset occurs. Important! ALDC1-40S-M Design Note page
NAME/NOTES Done Interrupt This when data transfer completed compressed data interface during compression when data transfer completed original data interface during decompression. reset when data transfer operation begins when reset occurs.
Hold Interrupt This when current transfer step after microprocessor issues Hold (CMND equals X'4200') opcode completed. reset when microprocessor issues Resume (CMND equals X'4400') opcode, when data transfer operation begins, when reset occurs.
3.1.8 Interrupt Status (INTS)
Interrupt Status register provides interrupt status bits microprocessor. INTS reset X'0000' hardware software reset. This register only accessable when CMND equal X'C100', X'C200', X'C400', X'C800'. When +M1BYTE tied low, +ADDR(4:1) equals X'7' read INTS. When +M1BYTE tied high, +ADDR(4:0) equals X'0E' read INTS(7:0); +ADDR(4:0) equals X'0F' read INTS(15:8). section page 3-12 more information interrupts.
Figure 3-9. INTS
Reserved Error Interrupt This when error occurs. reset when data transfer operation begins when reset occurs. Note: Error Status (ERRS) register used determine cause error.
3.1.9 Command (CMND)
Command register used program operation ALDC1-40S-M. CMND reset X'0000' hardware reset. CMND changed software reset. When +M1BYTE tied low, +ADDR(4:1) equals X'8' read write CMND. When +M1BYTE tied high, +ADDR(4:0) equals X'10' read write CMND(7:0); +ADDR(4:0) equals X'11' read write CMND(15:8).
15:8
NAME/NOTES Reserved
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Figure
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Figure
3-10. CMND
3-11 (Page Opcodes. Note: Opcodes explicitly named this table reserved future use. They invalid ALDC1-40S-M will produce operation.
15:0
NAME/NOTES Opcode Figure 3-11 page proposed opcode descriptions. OPCODE
NAME/NOTES Start Decompression Bypass section 2.2.4 page detailed description this data transfer operation.
CMND Register layout shown Figure 3-10 page defined opcode description given Figure 3-11.
Figure 3-11 (Page Opcodes. Note: Opcodes explicitly named this table reserved future use. They invalid ALDC1-40S-M will produce operation.
X'6000'
X'6800'
Start Decompression section 2.2.5 page detailed description this data transfer operation.
OPCODE X'0000' X'4200'
NAME/NOTES operation performed. Hold When data transfer operation progress, current operation steps completed original data interface compressed data interface data buses placed into high impedance state. Hold Interrupt (INTS(6)) Hold (STAT(6)) bits then '1'. data currently being processed data transfer operation preserved.
X'6C00'
Start Decompression Output Disabled section 2.2.6 page detailed description this data transfer operation.
X'A000'
Software Reset Original Data Interface Configuration (OCNF), Compressed Data Interface Configuration (CCNF), Level (ECL), Original Data Interface Polarity (OPOL), Compressed Data Interface Polarity (CPOL), Command (CMND) registers affected this opcode. other registers reset, current operations cancelled, history buffer cleared. Important! ALDC1-40S-M Design Note page
X'4400'
Resume previously held data transfer operation resumes processing. Hold Interrupt (INTS(6)) Hold (STAT(6)) bits reset Busy (STAT(7)) '1'.
X'C100'
Select Original Data Interface Configuration OCNF OPOL registers enabled reads writes.
X'5000'
Start Compression Bypass section 2.2.2 page detailed description this data transfer operation. X'C200'
Select Compressed Data Interface Configuration CCNF CPOL registers enabled reads writes.
X'5800'
Start Compression section 2.2.3 page detailed description this data transfer operation.
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Figure
3-11 (Page Opcodes. Note: Opcodes explicitly named this table reserved future use. They invalid ALDC1-40S-M will produce operation.
OPCODE X'C400'
NAME/NOTES Select Original Data Interface Peripheral Access peripheral access addresses (+ADDR(4) equals '0') enabled reads writes original data interface attached peripheral. Important! ALDC1-40S-M Design Note page
direction data transfer operation specifies whether Original Data Interface Transfer Count (TCO) register Compressed Data Interface Transfer Count (TCC) register used determine when data bytes have been received data transfer operation. During compression, used. During decompression, used. When appropriate Transfer Count register (TCO TCC) equals XFR, bytes current data transfer operation have been received ALDC1-40S-M. Note: thirty-two register. This means that maximum data block size which specified X'FFFF FFFF' 4,294,967,295) bytes. Therefore, application system designer must ensure that data partitioned into data blocks smaller than gigabytes, that each data block compressed decompressed separately.
Figure 3-12.
X'C800'
Select Compressed Data Interface Peripheral Access peripheral access addresses (+ADDR(4) equals '0') enabled reads writes compressed data interface attached peripheral. Important! ALDC1-40S-M Design Note page
31:16 15:0
NAME/NOTES Transfer Size High (XFRH) Transfer Size (XFRL)
3.1.11 Data Disable Count (DDC)
Data Disable Count register provides microprocessor control number bytes skipped during Start Decompression Output Disabled (CMND equals X'6C00') operation. Data Disable Count (DDC) four byte register with most significant bytes contained Data Disabled Count High (DDCH) least significant bytes contained Data Disabled Count (DDCL). DDCL DDCH reset X'0000' hardware software reset. When +M1BYTE tied low, +ADDR(4:1) equals X'C' read write DDCH +ADDR(4:1) equals X'D' read write DDCL. When +M1BYTE tied high, +ADDR(4:0) equals X'18' read write DDCH(7:0); +ADDR(4:0) equals X'19' read write DDCH(15:8); +ADDR(4:0) equals X'1A' read write DDCL(7:0); +ADDR(4:0) equals X'1B' read write DDCL(15:8). Note: Data Disable Count (DDC) X'0000' during Start Decompression Output Disabled (CMND equals X'6C00') operation
3.1.10 Transfer Size (XFR)
Transfer Size register provides microprocessor control number bytes transferred during data transfer operation. Transfer Size (XFR) four byte register with most significant bytes contained Transfer Size High (XFRH) least significant bytes contained Transfer Size (XFRL). XFRL XFRH reset X'0000' hardware software reset. When +M1BYTE tied low, +ADDR(4:1) equals read write XFRH +ADDR(4:1) equals read write XFRL. When +M1BYTE tied high, +ADDR(4:0) equals X'14' read write XFRH(7:0); +ADDR(4:0) equals X'15' read write XFRH(15:8); +ADDR(4:0) equals X'16' read write XFRL(7:0); +ADDR(4:0) equals X'17' read write XFRL(15:8).
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Figure 3-14. EMSK
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greater than Transfer Size (XFR) during Start Decompression Output Disabled (CMND equals X'6C00') operation, then original data interface output will disabled entire transfer.
Figure 3-13.
NAME/NOTES Microprocessor Interface Parity Error Mask When '1', corresponding Microprocessor Interface Parity Error (ERRS(4)) disabled. When reset '0', Microprocessor Interface Parity Error re-enabled.
31:16 15:0
NAME/NOTES Data Disabled Count High (DDCH) Data Disabled Count (DDCL)
3.1.12 Error Mask (EMSK)
Error Mask register provides error reporting configuration capability microprocessor. EMSK reset X'0000' hardware software reset. When +M1BYTE tied low, +ADDR(4:1) equals X'E' read write EMSK. When +M1BYTE tied high, +ADDR(4:0) equals X'1C' read write EMSK(7:0); +ADDR(4:0) equals X'1D' read write EMSK(15:8). Note: Error Mask register provided allow temporary masking error signals. This register should always reset X'0000' field usage.
Figure 3-14. EMSK
Compressed Data Interface Transfer Count (TCC) Overflow Error Mask When '1', corresponding Compressed Data Interface Transfer Count (TCC) Overflow Error (ERRS(3)) disabled. When reset '0', Compressed Data Interface Transfer Count Overflow Error re-enabled.
Original Data Interface Transfer Count (TCO) Overflow Error Mask When '1', corresponding Original Data Interface Transfer Count (TCO) Overflow Error (ERRS(2)) disabled. When reset '0', Original Data Interface Transfer Count Overflow Error reenabled.
15:7
NAME/NOTES Reserved Original Data Interface Parity Error Mask When '1', corresponding Original Data Interface Parity Error (ERRS(6)) disabled. When reset '0', Original Data Interface Parity Error re-enabled.
ALDC Decoder Control Code Error Mask When '1', corresponding ALDC Decoder Control Error (ERRS(1)) disabled. When reset '0', ALDC Decoder Control Code Error re-enabled.
ALDC Decoder Error Mask When '1', corresponding ALDC Decoder Error (ERRS(0)) disabled. When reset '0', ALDC Decoder Error reenabled.
Compressed Data Interface Parity Error Mask When '1', corresponding Compressed Data Interface Parity Error (ERRS(5)) disabled. When reset '0', Compressed Data Interface Parity Error reenabled.
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3.1.13 Interrupt Mask (IMSK)
Interrupt Mask register provides interrupt reporting configuration capability microprocessor. IMSK reset X'0000' hardware software reset. When +M1BYTE tied low, +ADDR(4:1) equals X'F' read write IMSK. When +M1BYTE tied high, +ADDR(4:0) equals X'1E' read write IMSK(7:0); +ADDR(4:0) equals X'1F' read write IMSK(15:8). Note: microprocessor disables interrupts setting bits IMSK. When interrupts disabled, microprocessor responsibility ensure that correct STAT bits polled.
Figure 3-15. IMSK
When active, they indicate that data transfer operation completed successfully, been held, failed. microprocessor determine data transfer operation failed reading testing Error (STAT(1)) bit. Error '1', then error occurred previously attempted data transfer operation. cause error determined reading Error Status (ERRS) register. Error recovery procedures then invoked appropriate. Error '0', then error occurred previous data transfer operation. Likewise, microprocessor determine data transfer operation held reading testing Hold (STAT(6)) bit. Hold '1', then data transfer operation held waiting resumed. both Error Hold Done (STAT(0)) '1', then data transfer operation completed successfully. hardware interrupt signals automatically return their inactive state when either hardware reset software reset occurs, when data transfer operation resumed, when data transfer operation begins. Note: -IREQOD open-drain output requires pull-up resistor. section Chapter page pull-up resistor selection considerations.
15:8
NAME/NOTES Reserved Done Interrupt Mask When '1', corresponding Done Interrupt (INTS(7)) disabled. When reset '0', Done Interrupt reenabled.
Hold Interrupt Mask When '1', corresponding Hold Interrupt (INTS(6)) disabled. When reset '0', Hold Interrupt reenabled.
Reserved Error Interrupt Mask When '1', corresponding Error Interrupt (INTS(0)) disabled. When reset '0', Error Interrupt reenabled.
Resets
There hardware reset signal ALDC1-40S-M (-RESET). When asserted, registers (except Level register) reset, current operations cancelled, history buffer cleared. There also software reset ALDC1-40S-M (CMND equals X'A000'). software reset does affect Original Data Interface Configuration (OCNF), Compressed Data Interface Configuration (CCNF), Level (ECL), Original Data Interface Polarity (OPOL), Compressed Data Interface Polarity (CPOL), Command (CMND) registers. other regis-
Interrupts
There hardware interrupt signals ALDC1-40S-M. -IREQOD, which negative active, open-drain output. other +IREQPP; positive active, push-pull output.
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ters reset, current operations cancelled, history buffer cleared. Important! ALDC1-40S-M Design Note page
Figure 3-16 summarizes hardware software resets ALDC1-40S-M. Because some register's contents modified during initialization data transfer operations, this information also included figure.
Figure
3-16. Reset Summary
+ADDR(4:1)
MNEMONIC
HARDWARE RESET X'0000' X'0000' X'0000' unchanged X'00FF' X'00FF' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' X'0000'
OPCODE X'A000': SOFTWARE RESET X'0000' unchanged unchanged unchanged unchanged unchanged X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' unchanged X'0000' X'0000' X'0000' X'0000' X'0000' X'0000'
DATA TRANSFER INITIALIZATION X'0080' (Busy) unchanged unchanged unchanged unchanged unchanged X'0000' X'0000' X'0000' X'0000' X'0000' X'0000' unchanged unchanged unchanged unchanged unchanged unchanged unchanged
X'0'
STAT OCNF CCNF
X'1'
OPOL CPOL
X'2' X'3' X'4' X'5' X'6' X'7' X'8' X'C' X'D' X'E' X'F'
TCOH TCOL TCCH TCCL ERRS INTS CMND XFRH XFRL DDCH DDCL EMSK IMSK
Data Expansion
Data expansion occurs when size data increases during compression operation. This rare occurrence because ALDC1-40S-M adapts data being compressed. However, application system designer must aware data expansion consider impact system operation. data expansion causes Compressed Data Interface Transfer Count (TCC) exceed 4,294,967,295 bytes, then ALDC1-40S-M would Overflow Error (ERRS(12)) '1', Error (STAT(14))
'1', assert -IREQOD +IREQPP outputs, cancel transfer. ALDC1-40S-M also Expansion (STAT(12)) which used detect data expansion when errors occur.
3.4.1 Worst Case Expansion
ALDC compression algorithm approaches worst case 12.5% data expansion. example, given system always compresses 60,000 byte data blocks, then there small possibility that about 67,500 bytes result from worst case compression operation.
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Continuing with example, microprocessor might detect that expansion occurred initiate recovery transferring original 60,000 bytes instead. example demonstrates data expansion might handled system level. application system designer determine appropriate system response data expansion. Data modeling indicate that probability data expansion small nonexistent (for specific application). this case, application system designer need concerned about data expansion. Note: data expansion design concern, then following formula used calculate maximum allowable transfer size given compressed data buffer size:
XFRmax INT(
(CDB
where XFRmax maximum allowable transfer size bytes, compressed data buffer size bytes, INT(x) integer function (sometimes called floor function). under control application system designer. compressed data buffer part ALDC1-40S-M. Rather, this document, compressed data buffer size describes byte limit imposed number compressed bytes output during compression operation. This limit might imposed because bus, memory, real-time, other system constraints. compressed data buffer size exists design, compressed data buffer size larger than 4,294,967,295 bytes, then XFRmax should 3,817,748,700,
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Chapter Hardware Interface Timing
Control Pins
control pins those pins which have more than logical function depending upon mode which their respective interface configured. They summarized below. signal names used associate names with their logical function.
Figure 4-1. Microprocessor Interface Control Pins
used Signal When.
MMODE tied
Name low.
MMODE tied
high.
MCIN(0) MCIN(1) MCOUT
-READ -WRITE -WAIT
+R/-W -WAIT
Figure
4-2. Original Data Interface Compressed Data Interface Control Pins. When using this figure, replace only only, appropriate. used describe original data interface control pins signals. used describe compressed data interface control pins signals.
used Signal When. xCNF(13:12) '10' (Controller) xCNF(12) (Synchronous) CMND X'C400' (Peripheral Access) used used used
Name
xCNF(13:12) '00' (Device)
xCIN(0) xCIN(1) xCOUT(0) xCOUT(1) xCOUT(2) xCOUT(3) xCOUT(4) xCOUT(5)
xREQ
used
xACK
used
xACK
used
xREQ
used used used
xENABLE xREADY
used used used
xPCS
Note: xPOL register controls polarity control pins.
Microprocessor Interface
ALDC1-40S-M provides asynchronous interface controlling microprocessor. microprocessor interface shown Figure page 4-2. microprocessor interface either modes which selected using MMODE pin. When MMODE tied high, microprocessor interface controlled using chip select read/write signal. When
MMODE tied low, microprocessor interface
controlled using read write signal. Read timing using +R/-W microprocessor interface shown Figure page 4-2. Write timing using +R/-W microprocessor interface shown Figure page 4-4. Read timing using -READ -WRITE microprocessor interface shown Figure page 4-5. Write timing using -READ -WRITE microprocessor interface shown Figure page 4-7. Hardware reset timing microprocessor interface shown Figure page 4-8.
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+MDATA(15:00) +MPARITY(1:0) MCIN(0) MCIN(1) MCOUT +ADDR(4:0) +MENABLEP +MODDP MMODE +M1BYTE -RESET -IREQOD +IREQPP
Interface
Figure
4-3. Microprocessor Interface
|\_/ |\_/| |_|_| VALID _/\_/\_|_/\_/\_ _//// VALID \\\\_ \\\\_////
MCIN(1) (+R/-W input)
MCIN(0) (-CS input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional output)
Figure
(Part Microprocessor Interface Read Timing with MMODE Tied High
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Note:
DESCRIPTION
clock cycles clock cycles clock cycles clock cycle clock cycle clock cycle clock cycle
+R/-W high before active +R/-W high after active active inactive (See note inactive active -WAIT active after active inactive after -WAIT inactive (See note -WAIT inactive after active +ADDR valid before active +ADDR hold time after active +MDATA valid after active +MDATA disable time after inactive +MDATA enable time after active +MDATA valid after inactive
17.5 clock cycles
clock cycles clock cycle clock cycles 21.5 clock cycle
When using -WAIT control inactive, ignore Otherwise, ignore Usage note: microprocessor interface latches address falling edge -CS. user should latch output data rising edge -CS.
Figure (Part Microprocessor Interface Read Timing with MMODE Tied High
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_\_/_\_/_ |\_/| VALID _/\_/\_|_/\_/\_ VALID _/\_/\_
MCIN(1) (+R/-W input)
MCIN(0) (-CS input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional input)
Figure
(Part Microprocessor Interface Write Timing with MMODE Tied High
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Note:
DESCRIPTION
clock cycles clock cycles clock cycle
+R/-W before active +R/-W after active active inactive (See note inactive active -WAIT active after active inactive after -WAIT inactive (See note -WAIT inactive after active +ADDR valid before active +ADDR hold time after active +MDATA valid before inactive +MDATA hold time after inactive
17.5 clock cycles
When using -WAIT control inactive, ignore Otherwise, ignore Usage note: microprocessor interface latches address falling edge -CS. microprocessor interface latches input data rising edge -CS.
Figure (Part Microprocessor Interface Write Timing with MMODE Tied High
|\_/| |_|_| VALID _/\_/\_|_/\_/\_ _//// VALID \\\\\\_ \\\\_//////
MCIN(0) (-READ input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional output)
Figure
(Part Microprocessor Interface Read Timing with MMODE Tied
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Note:
DESCRIPTION
(See note
-READ active -READ inactive -READ inactive -READ active -WAIT active after -READ active -WAIT inactive before -READ inactive
note
clock cycles clock cycles
(See
clock cycles clock cycle clock cycle clock cycle clock cycle clock cycles clock cycles clock cycles 21.5 clock cycles clock cycles
-WAIT inactive after -READ active +ADDR valid before -READ active +ADDR hold time after -READ active +MDATA valid after -READ active +MDATA disable time after -READ inactive +MDATA enable time after -READ active +MDATA valid after -READ inactive
When using -WAIT control -READ inactive, ignore Otherwise ignore Usage note: microprocessor interface latches address falling edge -READ. user should latch output data rising edge -READ. Note: -WRITE must inactive during transfers microprocessor interface.
Figure (Part Microprocessor Interface Read Timing with MMODE Tied
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|\_/| VALID _/\_/\_|_/\_/\_ VALID _/\_/\_
MCIN(1) (-WRITE input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional input)
Note:
DESCRIPTION
clock cycles clock cycles clock cycle
-WRITE active -WRITE inactive (See note -WRITE inactive -WRITE active -WAIT active after -WRITE active -WAIT inactive before -WRITE inactive (See
note
-WAIT inactive after -WRITE active +ADDR valid before -WRITE active +ADDR hold time after -WRITE active +MDATA valid before -WRITE inactive +MDATA hold time after -WRITE inactive
clock cycles
When using -WAIT control -WRITE inactive, ignore Otherwise, ignore Usage note: microprocessor interface latches address falling edge -WRITE. microprocessor interface latches input data rising edge -WRITE. Note: -READ must inactive during transfers into microprocessor interface.
Figure 4-7. Microprocessor Interface Write Timing with MMODE Tied
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|\_/|
-RESET (input)
MCIN(0) MCIN(1) (-CS -READ -WRITE inputs)
DESCRIPTION
clock cycles clock cycles
-RESET active -RESET inactive -RESET inactive -READ -WRITE
active
Figure
4-8. Microprocessor Interface Hardware Reset
Original Data Interface Compressed Data Interface
Both original data interface compressed data interface operate four modes. These modes described below. Note: original data interface compressed data interface idependently configured using OCNF, OPOL, CCNF, CPOL registers. pages more detail these registers. Note: following timing diagrams describe communication between original data interface compressed data interface external module connected these timing diagrams, Original Data Interface Polarity (OPOL) Compressed Data Interface Polarity (CPOL) registers assumed reset X'00FF'. This their default state (ie. negative active polarity). OPOL CPOL bits changed, then corresponding control will inverted from what shown these timing diagrams (ie. positive active polarity).
OCIN(1:0) OCOUT(5:0) +ODATA(15:00) +OPARITY(1:0)
Original Data Interface
Figure
4-9. Original Data Interface
CCIN(1:0) CCOUT(5:0) +CDATA(15:00) +CPARITY(1:0)
Compressed Data Interface
Figure
4-10. Compressed Data Interface
4.3.1 Four-edge Mode
This mode asynchronous data transfer which bytes transferred every request/acknowledge pair. shown Figure 4-11 page Figure 4-12 page 4-10, typical four-edge transfer assumes request goes active initiate transfer, acknowledge then goes active response request, which leads withdrawal request finally acknowledge withdrawn data transferred inactivating edge acknowledge.
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|\_|_/ VALID
ALDC1-40S-M
xCOUT(0) (xREQ output)
xCIN(0) (xACK input)
+xDATA (bidirectional output)
|\_|_/ VALID
Into ALDC1-40S-M
Figure 4-11 (Part Four-edge Device Timing
xCOUT(0) (xREQ output)
xCIN(0) (xACK input)
+xDATA (bidirectional input)
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Figure
DESCRIPTION
clock cycles clock cycle clock cycles clock cycle
xACK active xREQ inactive xREQ inactive next xREQ active xREQ active xACK active xACK active xACK inactive xACK inactive next xREQ active +xDATA valid after xACK active +xDATA valid after xACK inactive +xDATA valid before xACK inactive +xDATA hold time after xACK inactive
4-11 (Part Four-edge Device Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
VALID
ALDC1-40S-M
Figure 4-12 (Part Four-edge Controller Timing
xCIN(0) (xREQ input)
xCOUT(0) (xACK output)
xCOUT(1) (xWR output)
+xDATA (bidirectional output)
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VALID
Into ALDC1-40S-M
Figure 4-12 (Part Four-edge Controller Timing
xCIN(0) (xREQ input)
xCOUT(0) (xACK output)
xCOUT(2) (xRD output)
+xDATA (bidirectional input)
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DESCRIPTION
clock cycles clock cycle
clock cycles clock cycles
xREQ active xREQ inactive xREQ inactive xACK inactive
xACK inactive next xREQ active xREQ active xACK active xACK active xACK inactive +xDATA valid after xACK active
clock cycle clock cycles clock cycle clock cycle clock cycle
+xDATA valid after xACK inactive
clock cycle clock cycle
clock cycle clock cycle
Figure
+xDATA valid before xACK inactive +xDATA hold time after xACK inactive
4-12 (Part Four-edge Controller Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
4.3.2 Burst Mode
This mode like four-edge mode. asynchronous requires both request acknowledge signal. difference that there multiple acknowledges therefore multiple data transfers during single extended request, thereby reducing number cycles required transfer.
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|\_|_/ |T2| _|_/// VALID \_/// VALID \_/// VALID \\\_/ \\\_/ \\\_/ |T8|
ALDC1-40S-M
xCOUT(0) (xREQ output)
xCIN(0) (xACK input)
+xDATA (bidirectional output)
|\_|_/ |T2| |T9| T10| VALID VALID VALID
Into ALDC1-40S-M
Figure 4-13 (Part Burst Device Timing
xCOUT(0) (xREQ output)
xCIN(0) (xACK input)
+xDATA (bidirectional input)
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DESCRIPTION Last xACK active xREQ inactive Ending Burst (See note
clock cycle clock cycle
Notes:
xREQ active xACK active Starting Burst xACK active xACK inactive xACK inactive xACK active (See notes
clock cycle clock cycles clock cycles clock cycles clock cycle
Last xACK inactive next xREQ active Start burst
+xDATA valid after xACK inactive +xDATA valid after xACK active. (See note +xDATA enable time after xACK active +xDATA valid before xACK inactive +xDATA hold time after xACK inactive
clock cycles greater, then maximum ns}. clock cycles greater, then maximum only xACK active interval occurs during xREQ cycle, then does exist.
Figure 4-13 (Part Burst Device Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
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4-14
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
|\_|_/ |T2| _|_/ VALID VALID VALID
ALDC1-40S-M
xCIN(0) (xREQ input)
xCOUT(0) (xACK output)
xCOUT(1) (xWR output)
+xDATA (bidirectional output)
|\_|_/ |T2| |T8| VALID VALID VALID
Into ALDC1-40S-M
Figure 4-14 (Part Burst Controller Timing
xCIN(0) (xREQ input)
xCOUT(0) (xACK output)
xCOUT(2) (xRD output)
+xDATA (bidirectional input)
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4-15
Microelectronics Division
ALDC1-40S-M Data Compression
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
DESCRIPTION Last xACK active xREQ inactive Ending Burst
clock cycle clock cycles clock cycles clock cyccles
clock cycles
xREQ active xACK active Starting Burst xACK active xACK inactive
clock cycles clock cycles
xACK inactive xACK active
Last xACK inactive next xREQ active Start burst
clock cycles clock cycle clock cycle clock cycle
+xDATA valid after xACK inactive
+xDATA valid after xACK active
clock cycle
clock cycle clock cycle
Figure
+xDATA valid before xACK inactive +xDATA hold time after xACK inactive
4-14 (Part Burst Controller Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
4.3.3 Synchronous Mode
This mode allows fast data transfers MB/s which bytes data transferred every cycle activating edge externally supplied clock. transmit, ALDC1-40S-M activates xREADY indicating +xDATA valid. receiver acti-
vates both xENABLE accept +xDATA. ALDC1-40S-M generate +xDATA next rising edge +OSC. receiving mode, ALDC1-40S-M activates
xREADY indicating waiting valid +xDATA. transmitter activates both xENABLE validate +xDATA. ALDC1-40S-M accepts +xDATA next rising edge +OSC.
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4-16
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
\_/| \_/| \_/| \_|_|_|_/ \_|_|_|_/ _|_| |\_|_|_/| _|_/// VALID0 VALID1 VALID2 \\\\\_ \\\_/\_/\_/////
ALDC1-40S-M
Figure 4-15 (Part Synchronous Timing
+OSC (input)
xCOUT(0) (xREADY output)
xCIN(1) (xENABLE input)
xCIN(0) (xCS input)
+xDATA (bidirectional output)
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4-17
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ALDC1-40S-M Data Compression
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
\_/| \_/| \_|_|_/ \_|_|_/ \_|_/ T10| T11| VALID VALID VALID
Into ALDC1-40S-M
Figure 4-15 (Part Synchronous Timing
+OSC (input)
xCOUT(0) (xREADY output)
xCIN(1) (xENABLE input)
xCIN(0) (xCS input)
+xDATA (bidirectional input)
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ALDC1-40S-M Data Compression
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DESCRIPTION high transition +OSC xREADY active high transition +OSC xREADY inactive
xENABLE active high transition +OSC high transition +OSC xENABLE
inactive
active high transition +OSC high transition +OSC inactive high transition +OSC +xDATA valid
+xDATA disable time after inactive +xDATA enable time after active +xDATA valid before high transition +OSC +xDATA hold time after high transition +OSC
Figure
4-15 (Part Synchronous Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values negative active timing values identical.
4.3.4 Peripheral Access Mode
Peripheral access allows microprocessor write read from peripheral connected original data interface compressed data interface. This mode relatively slow, asynchronous transfer.
Note: Peripheral access mode used microprocessor program peripheral allowed during data transfer operation.
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4-19
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ALDC1-40S-M Data Compression
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
_|_|_|_ |_|_| VALID _/\_/\_|_/\_/\_ _|_| _|_//// VALID \\\\_/ \_|_|_/ \_|_/ VALID _/\_/\_
MCIN(1) (+R/-W input)
MCIN(0) (-CS input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional output)
xCOUT(2) (xRD output)
xCOUT(3) (xPCS output) +xDATA (bidirectional input)
Figure
4-16 (Part Peripheral Access Read Timing with MMODE Tied High
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4-20
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
DESCRIPTION
clock cycles clock cycles clock cycles clock cycle clock cycle clock cycle clock cycle
+R/-W high before active +R/-W high after active active inactive (See notes inactive active -WAIT active after active inactive after -WAIT inactive (See note -WAIT inactive after active (See note +ADDR valid before active +ADDR hold time after active +MDATA enable time after active +MDATA disable time after inactive
Delay from +xDATA valid +MDATA valid
(See note
17.5 clock cycles
clock cycles 21.5 clock cycle 24.5 clock cycles clock cycles 12.5 clock cycles 16.5
active after active inactive after inactive
xPCS active after active xPCS inactive after inactive
clock cycle clock cycle
clock cycles clock cycles clock cycles
Notes: When using -WAIT control inactive, ignore Otherwise, ignore value stored register xCNF(6:4). +MENABLEP tied low, maximum 19.5 Usage note: microprocessor interface latches address falling edge -CS. user should latch output data rising edge -CS. Important! ALDC1-40S-M Design Note page
Figure
4-16 (Part Peripheral Access Read Timing with MMODE Tied High. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
_\_|_/_ |_|_| VALID _/\_/\_|_/\_/\_ |_|_| _|_/ VALID \_|_/ \_|_/ _/////////////////// VALID \\\\\\\\\\\\\\\\\\\
MCIN(1) (+R/-W input)
MCIN(0) (-CS input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional input)
xCOUT(1) (xWR output)
xCOUT(3) (xPCS output)
+xDATA (bidirectional output)
Figure
4-17 (Part Peripheral Access Write Timing with MMODE Tied High
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4-22
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
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DESCRIPTION
clock cycles clock cycles clock cycles clock cycle clock cycle
+R/-W before active +R/-W after active active inactive (See notes inactive active -WAIT active after active inactive after -WAIT inactive (See note -WAIT inactive after active (See note +ADDR valid before active +ADDR hold time after active +MDATA valid before inactive +MDATA hold time after inactive active after active inactive after inactive
17.5 clock cycles
clock cycles clock cycles 12.5 clock cycles 16.5
xPCS active after active xPCS inactive after inactive
clock cycle clock cycle
clock cycles clock cycles clock cycles
Notes:
+xDATA disable time after inactive +xDATA enable time after active +xDATA valid after inactive
clock cycles clock cycle
clock cycles 17.5 clock cycles 13.5 18.5
When using -WAIT control inactive, ignore Otherwise, ignore value stored register xCNF(6:4). Usage note: microprocessor interface latches address falling edge -CS. Microprocessor Interface latches input data rising edge -CS.
Figure 4-17 (Part Peripheral Access Write Timing with MMODE Tied High. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
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4-23
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
|_|_| VALID _/\_/\_|_/\_/\_ _|_| _|_//// VALID \\\\_/ \_|_|_/ \_|_/ VALID _/\_/\_
MCIN(0) (-READ input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional output)
xCOUT(2) (xRD output)
xCOUT(3) (xPCS output) +xDATA (bidirectional input)
Figure
4-18 (Part Peripheral Access Read Timing with MMODE Tied
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4-24
Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
ALDC1-40S-M Data Compression
Microelectronics Division
DESCRIPTION
(See notes
-READ active -READ inactive
clock cycles clock cycles
-READ inactive -READ active -WAIT active after -READ active -READ inactive after -WAIT inactive
(See note
clock cycles clock cycle clock cycle clock cycle clock cycle clock cycles 21.5 clock cycles 24.5 clock cycles clock cycles 12.5 clock cycles 16.5 clock cycles
-WAIT inactive after -READ active
(See note
+ADDR valid before -READ active +ADDR hold time after -READ active +MDATA enable time after -READ active +MDATA disable time after -READ inactive
Delay from +xDATA valid +MDATA valid
(See note
active after -READ active inactive after -READ inactive
xPCS active after -READ active xPCS inactive after -READ inactive
clock cycle clock cycle
clock cycles clock cycles clock cycles
Notes: When using -WAIT control -READ inactive, ignore Otherwise, ignore value stored register xCNF(6:4). +MENABLEP tied low, maximum 19.5 Usage note: microprocessor interface latches address falling edge -READ. user should latch output data rising edge -READ. Note: -WRITE must inactive during transfers Microprocessor Interface. Important! ALDC1-40S-M Design Note page
Figure
4-18 (Part Peripheral Access Read Timing with MMODE Tied Low. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
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4-25
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
|_|_| VALID _/\_/\_|_/\_/\_ |_|_| _|_/ VALID \_|_/ \_|_/ _/////////////////// VALID \\\\\\\\\\\\\\\\\\\
MCIN(1) (-WRITE input)
MCOUT (-WAIT output)
+ADDR (input)
+MDATA (bidirectional input)
xCOUT(1) (xWR output)
xCOUT(3) (xPCS output)
+xDATA (bidirectional output)
Figure
4-19 (Part Peripheral Access Write Timing with MMODE Tied
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DESCRIPTION
(See notes
-WRITE active -WRITE inactive
clock cycles clock cycles
-WRITE inactive -WRITE active -WAIT active after -WRITE active -WAIT inactive before -WRITE inactive
note
(See
clock cycles clock cycle clock cycle clock cycles clock cycles 12.5 clock cycles 16.5 clock cycles
-WAIT inactive after -WRITE active
(See note
+ADDR valid before -WRITE active +ADDR hold time after -WRITE active +MDATA valid before -WRITE inactive +MDATA hold time after -WRITE inactive active after -WRITE active inactive after -WRITE inactive
xPCS active after -WRITE active xPCS inactive after -WRITE inactive
clock cycle clock cycle
clock cycles clock cycles clock cycles
Notes:
+xDATA disable time after -WRITE inactive +xDATA enable time after -WRITE active +xDATA valid after -WRITE inactive
clock cycle clock cycle
clock cycles 17.5 clock cycles 13.5 18.5
When using -WAIT control -WRITE inactive, ignore Otherwise, ignore value stored register xCNF(6:4). Usage note: microprocessor interface latches address falling edge -WRITE. Microprocessor Interface latches input data rising edge -WRITE. Note: -READ must inactive during transfers into Microprocessor Interface.
Figure 4-19 (Part Peripheral Access Write Timing with MMODE Tied Low. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values given brackets when different from negative active timing values.
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4-27
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
4.3.5 FIFO Operation
original data interface compressed data interface both contain sixteen-byte FIFO's that allow user optimize performance providing configurable FIFO thresholds. These FIFO's reset empty hardware reset, software reset, data transfer operation. Note: Original Data Interface FIFO Threshold (OCNF(3:0)) bits Compressed Data Interface FIFO Threshold (CCNF(3:0)) bits independently configurable. discussion below, these threshold bits called xFIFO threshold, where replaced only only, appropriate. xFIFO threshold written into respective xCNF register through microprocessor interface. xFIFO threshold take value from '0000' '1111'.
xFIFO full, xREQ deactivates. xREQ signal activates each time number empty byte locations xFIFO greater than equal xFIFO threshold. xREQ signal remains active until xFIFO full.
4.3.5.2 Four-edge Burst Controllers
When original data interface compressed data interface configured four-edge burst controller, then xFIFO threshold used trigger when xACK activates deactivates. xFIFO conditions which cause xACK activate deactivate identical those which cause xREQ activate deactivate when configured four-edge burst device. section 4.3.5.1 above. Note: xACK signal only active after original data interface compressed data interface receives active xREQ regardless xFIFO threshold.
4.3.5.1 Four-edge Burst Devices
When original data interface compressed data interface configured four-edge burst device, then xFIFO threshold used trigger when xREQ activates deactivates. When transferring data original data interface compressed data interface, xREQ activates when number available bytes xFIFO greater than equal xFIFO threshold. xREQ signal remains active until xFIFO empty. When xFIFO empty, xREQ deactivates. Note: xREQ signal also activates when, during compression, Original Data Interface Transfer Count (TCO) register (or, during decompression, Compressed Data Interface Transfer Count (TCC) register) equals Transfer Size (XFR) register. This condition indicates that bytes current data operation have been received that only transfers compressed data interface original data interface, respectively) remain. When transferring data into original data interface compressed data interface, xREQ activates beginning transfer. When
4.3.6 Almost Full Almost Empty
Almost Full (xAF) Almost Empty (xAE) signals always available user. signal used perform look-ahead stop when transferring data into original data interface compressed data interface. signal used perform lookahead stop when transferring data original data interface compressed data interface. signal deactivates when transfer operation begins. signal activates clock cycle after number empty byte locations xFIFO less than equal xFIFO threshold. signal deactivates clock cycle after number empty byte locations xFIFO greater than xFIFO threshold. signal activates when transfer operation begins. signal deactivates clock cycle after number available bytes xFIFO greater than xFIFO threshold. signal activates clock cycle after number available bytes xFIFO less than equal xFIFO threshold. Figure 4-20 page 4-29 details.
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\_/| \_/| \_/|
DESCRIPTION high transition +OSC active high transition +OSC inactive high transition +OSC inactive high transition +OSC active
+OSC (input)
xCOUT(4) (xAF output)
xCOUT(5) (xAE output)
Figure
4-20. Almost Full Almost Empty Timing. When using this figure, replace only only, appropriate. Negative active timings shown. Positive active timing values negative active timing values identical.
Clock Interface
+OSC signal clock input ALDC1-40S-M. timings microprocessor interface, original data interface, compressed data interface specified relative clock timing.
clock interface shown Figure 4-21. Detailed clock timing information given Figure 4-22 page 4-30.
+OSC
Clock Interface
Figure
4-21. Clock Interface
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Product Part Number: IBM22-ALDC1040S-00 Document Number: DCAL40DSU-02
+OSC (input)
Figure
DESCRIPTION
+OSC period +OSC rise time +OSC width high +OSC fall time +OSC width
4-22. Clock Timing
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Chapter Description
Figure
5-1. ALDC1-40S-M Numbering Diagram. Module viewed from top. Figure corresponding names, signal directions, descriptions. (Page ALDC1-40S-M Description. Figure identify locations.
Figure
NAME
DESCRIPTION ground pin. original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(15)
+ODATA(15) enabled setting OCNF(10) '1'.
+ODATA(14)
original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(14) enabled setting OCNF(10) '1'.
-TEST OCIN(0)
manufacturing test input. Must tied high. original data interface control input pin. When OCNF(13:12) '10', this used OREQ signal. When OCNF(13:12) '00', this used OACK signal. When OCNF(12) '1', this used signal. Figure page 4-1. polarity OCIN(0) controlled OPOL(7). ground pin.
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION original data interface control input pin. When OCNF(12) '1', this used OENABLE signal. Figure page 4-1. polarity OCIN(1) controlled OPOL(6). Volt power supply pin.
OCIN(1)
+ODATA(13)
original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(13) enabled setting OCNF(10) '1'.
+ODATA(12)
original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(12) enabled setting OCNF(10) '1'.
+ODATA(11)
original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(11) enabled setting OCNF(10) '1'.
+ODATA(10)
ground pin. original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(10) enabled setting OCNF(10) '1'.
+ODATA(09)
original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(09) enabled setting OCNF(10) '1'.
+ODATA(08)
Volt power supply pin. original data interface data pin. tied high, tied low, connected when enabled.
+ODATA(08) enabled setting OCNF(10) '1'.
+OPARITY(1)
original data interface parity pin. When enabled, this checks parity input generates parity output associated +ODATA(08) through +ODATA(15) pins. tied high, tied low, connected when enabled.
+OPARITY(1) enabled setting OCNF(15) OCNF(10) '1'.
MCIN(0)
ground pin. Volt power supply pin. microprocessor interface control input pin. When MMODE high, this used signal. When MMODE low, this used -READ signal. microprocessor interface control input pin. When MMODE high, this used +R/-W signal. When MMODE low, this used -WRITE signal.
MCIN(1)
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(15)
+MDATA(15) enabled tieing +M1BYTE low.
+MDATA(14)
microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(14) enabled tieing +M1BYTE low.
+MDATA(13)
ground pin. microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(13) enabled tieing +M1BYTE low.
+MDATA(12)
microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(12) enabled tieing +M1BYTE low.
+MDATA(11)
microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(11) enabled tieing +M1BYTE low.
+MDATA(10)
microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(10) enabled tieing +M1BYTE low.
+MDATA(09)
Volt power supply pin. microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(09) enabled tieing +M1BYTE low.
+MDATA(08)
microprocessor interface data pin. tied high, tied low, connected when enabled.
+MDATA(08) enabled tieing +M1BYTE low.
MCOUT -TEST +MPARITY(1)
microprocessor interface control output pin. This used -WAIT signal. manufacturing test input. Must tied high. ground pin. microprocessor interface parity pin. When enabled, this checks parity input generates parity output associated +MDATA(08) through +MDATA(15) pins. tied high, tied low, connected when enabled.
+MPARITY(1) enabled tieing +MENABLEP high tieing +M1BYTE low.
+MDATA(07) +MDATA(06)
Volt power supply pin. ground pin. microprocessor interface data pin. microprocessor interface data pin.
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION microprocessor interface data pin. Volt power supply pin. manufacturing test input. Must tied high. manufacturing test input. Must tied high. microprocessor interface data width selector pin. microprocessor interface data pin. ground pin. microprocessor interface data pin. microprocessor interface data pin. microprocessor interface data pin. Volt power supply pin. microprocessor interface data pin. microprocessor interface parity pin. When enabled, this checks parity input generates parity output associated +MDATA(00) through +MDATA(07) pins. tied high, tied low, connected when enabled.
+MDATA(05) -TEST -TEST +M1BYTE +MDATA(04) +MDATA(03) +MDATA(02) +MDATA(01) +MDATA(00) +MPARITY(0)
+MPARITY(0) enabled tieing +MENABLEP high.
-TEST +CDATA(07) +CDATA(06) +CDATA(05) +CDATA(04) +CDATA(03) +CDATA(02) +CDATA(01) +CDATA(00) +CPARITY(0)
manufacturing test input. Must tied high. ground pin. Volt power supply pin.
compressed data interface data pin. compressed data interface data pin. ground pin. compressed data interface data pin. compressed data interface data pin. Volt power supply pin. compressed data interface data pin. compressed data interface data pin. ground pin. compressed data interface data pin. compressed data interface data pin. Volt power supply pin. compressed data interface parity pin. When enabled, this checks parity input generates parity output associated +CDATA(00) through +CDATA(07) pins. tied high, tied low, connected when enabled.
+CPARITY(0) enabled setting CCNF(15) '1'.
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION Must tied low. ground pin. Unused. tied high, tied low, connected. Volt power supply pin. ground pin.
-TIE +CDATA(15)
compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(15) enabled setting CCNF(10) '1'.
+MENABLEP +CDATA(14)
Volt power supply pin. test output. Must connected. microprocessor interface parity enable pin. ground pin. compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(14) enabled setting CCNF(10) '1'.
+CDATA(13)
compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(13) enabled setting CCNF(10) '1'.
+CDATA(12)
Volt power supply pin. compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(12) enabled setting CCNF(10) '1'.
+CDATA(11)
compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(11) enabled setting CCNF(10) '1'.
+CDATA(10)
ground pin. compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(10) enabled setting CCNF(10) '1'.
+CDATA(09)
compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(09) enabled setting CCNF(10) '1'.
+CDATA(08)
Volt power supply pin. compressed data interface data pin. tied high, tied low, connected when enabled.
+CDATA(08) enabled setting CCNF(10) '1'.
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION compressed data interface parity pin. When enabled, this checks parity input generates parity output associated +CDATA(08) through +CDATA(15) pins. tied high, tied low, connected when enabled.
+CPARITY(1)
+CPARITY(1) enabled setting CCNF(15) CCNF(10) '1'.
CCIN(0)
ground pin. Volt power supply pin. compressed data interface control input pin. When CCNF(13:12) '10', this used CREQ signal. When CCNF(13:12) '00', this used CACK signal. When CCNF(12) '1', this used signal. Figure page 4-1. polarity CCIN(0) controlled CPOL(7). compressed data interface control input pin. When CCNF(12) '1', this used CENABLE signal. Figure page 4-1. polarity CCIN(1) controlled CPOL(6). microprocessor interface address pin. ground pin. compressed data interface control output pin. When CCNF(13:12) '10', this used CACK signal. When CCNF(13:12) '00', this used CREQ signal. When CCNF(12) '1', this used CREADY signal. Figure page 4-1. polarity CCOUT(0) controlled CPOL(5). compressed data interface control output pin. When CCNF(13:12) '10' when CMND register X'C800', this used signal. Figure page 4-1. polarity CCOUT(1) controlled CPOL(4). compressed data interface control output pin. When CCNF(13:12) '10' when CMND register X'C800', this used signal. Figure page 4-1. polarity CCOUT(2) controlled CPOL(3). compressed data interface control output pin. When CMND register X'C800', this used CPCS signal. Figure page 4-1. polarity CCOUT(3) controlled CPOL(2). Volt power supply pin.
CCIN(1)
+ADDR(4) CCOUT(0)
CCOUT(1)
CCOUT(2)
CCOUT(3)
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION compressed data interface control output pin. This used signal. Figure page 4-1. polarity CCOUT(4) controlled CPOL(1). microprocessor interface address pin. microprocessor interface address pin. microprocessor interface address pin. microprocessor interface address pin. tied high, tied low, connected when enabled. +ADDR(0) enabled tieing +M1BYTE high. ground pin. compressed data interface control output pin. This used signal. Figure page 4-1. polarity CCOUT(5) controlled CPOL(0). Volt power supply pin. ground pin.
CCOUT(4)
+ADDR(3) +ADDR(2) +ADDR(1) +ADDR(0)
CCOUT(5)
-IREQOD
microprocessor interface open-drain interrupt request pin. Note: -IREQOD open-drain output requires pull-up resistor used. Chapter page pull-up resistor selection considerations.
+IREQPP OCOUT(5)
microprocessor interface push-pull interrupt request pin. Volt power supply pin. original data interface control output pin. This used signal. Figure page 4-1. polarity OCOUT(5) controlled OPOL(0). original data interface control output pin. When OCNF(13:12) '10', this used OACK signal. When OCNF(13:12) '00', this used OREQ signal. When OCNF(12) '1', this used OREADY signal. Figure page 4-1. polarity OCOUT(0) controlled OPOL(5). original data interface control output pin. When OCNF(13:12) '10' when CMND register X'C400', this used signal. Figure page 4-1. polarity OCOUT(1) controlled OPOL(4).
OCOUT(0)
OCOUT(1)
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION original data interface control output pin. When OCNF(13:12) '10' when CMND register X'C400', this used signal. Figure page 4-1. polarity OCOUT(2) controlled OPOL(3). original data interface control output pin. This used signal. Figure page 4-1. polarity OCOUT(4) controlled OPOL(1). ALDC1-40S-M hardware reset pin. ground pin. Unused. tied high, tied low, connected.
OCOUT(2)
OCOUT(4)
-RESET -TIE OCOUT(3)
Must tied low. Volt power supply pin. original data interface control output pin. When CMND register X'C400', this used OPCS signal. Figure page 4-1. polarity OCOUT(3) controlled OPOL(2). microprocessor interface parity mode selector pin. When high (and +MENABLEP high), microprocessor interface generates checks parity. When (and +MENABLEP high), microprocessor interface generates checks even parity. microprocessor interface mode selector pin. ground pin. Volt power supply pin.
+MODDP
MMODE +OSC +ODATA(07) +ODATA(06) +ODATA(05) +ODATA(04) +ODATA(03) +ODATA(02) +ODATA(01) -TEST
system clock pin. high +OSC transitions used clock ALDC1-40S-M. ground pin. original data interface data pin. original data interface data pin. original data interface data pin. Volt power supply pin. original data interface data pin. original data interface data pin. ground pin. original data interface data pin. original data interface data pin. manufacturing test input. Must tied high. Volt power supply pin.
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Figure
(Page ALDC1-40S-M Description. Figure page identify locations.
NAME
DESCRIPTION original data interface data pin. ground pin. original data interface parity pin. When enabled, this checks parity input generates parity output associated +ODATA(00) through +ODATA(07) pins. tied high, tied low, connected when enabled.
+ODATA(00) +OPARITY(0)
+OPARITY(0) enabled setting OCNF(15) '1'.
Volt power supply pin.
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5-10
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Chapter Electrical Characteristics
Recommended Operating Conditions
Figure 6-1. Recommended Operating Conditions
Note:
PARAMETER Supply Voltage Input Voltage Output Voltage Ambient Operating Temperature Case Temperature Input Rise Time Input Fall Time
(See note (See note
4.75
5.00
5.25
UNIT
Measured from Vdd.
Absolute Maximum Minimum Ratings
Figure 6-2. Absolute Maximum Minimum Ratings. These absolute maximum minimum values that applied extended periods time without damaging ALDC1-40S-M. Circuit functionality implied.
Note:
PARAMETER Supply Voltage Storage Temperature Power Dissipation
(See note
UNIT
Worst case power dissipation maximum data transfer rate MB/s) 5.25
Characteristics
Figure (Page Characteristics
PARAMETER Positive Logic Level Input Voltage Negative Logic Level Input Voltage Positive Logic Level Input Current
2.00 0.30
5.00 0.00
5.25 0.80
UNIT
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Figure
(Page Characteristics
PARAMETER Negative Logic Level Input Current inputs without internal pull-up resistors.
UNIT
Negative Logic Level Input Current inputs with internal pull-up resistors.
Positive Logic Level Output Voltage outputs except -IREQOD. Negative Logic Level Output Voltage outputs except -IREQOD. Negative Logic Level Output Voltage -IREQOD (open-drain) output.
2.40
5.00
5.25
0.00
0.00
0.50
0.00
0.00
0.40
Positive Logic Level Output Current outputs except -IREQOD. Negative Logic Level Output Current outputs except -IREQOD. Negative Logic Level Output Current -IREQOD (open-drain) output. (See note
High Impedance Leakage Current Supply Current Leakage current clock frequency.
Note:
Input Capacitance Output Capacitance
negative logic level output current -IREQOD output sets lower bound choice pull-up resistor used. Pull-up resistor -IREQOD output should less than 5.25 0.02
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Characteristics
Figure 6-4. Characteristics. differences observed output transition times -IREQOD output open-drain driver this output.
PARAMETER Negative Logic Level Positive Logic Level Output Transition Time outputs except -IREQOD.
note (See
UNIT
Positive Logic Level Negative Logic Level Output Transition Time outputs except -IREQOD.
note (See
Negative Logic Level Positive Logic Level Output Transition Time -IREQOD (open-drain) output. (See notes
38.6
ns/k
Positive Logic Level Negative Logic Level Output Transition Time -IREQOD (open-drain) output. (See note
Notes: Worst case 4.75 load capacitance (CL) 50pf. Transition time dependent value pull-up resistor used. example, using 2000 resistor pull-up -IREQOD output gives maximum 38.6 77.2
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Clock Frequency
Figure
6-5. Clock Frequency. Maximum measured maximum input output data rates 5.25 given clock frequency. Minimum measured standby state data input output) 4.75 given clock frequency. clock frequency measured +OSC input. Note: This graph contains preliminary power measurements.
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Chapter Physical Dimensions
Figure
7-2. ALDC1-40S-M Close-up View. length tolerance dimensions millimeters.
Figure
7-1. ALDC1-40S-M Side Views. length tolerance dimensions millimeters. orientation mark shown lower left-hand corner view.
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Appendix Notation
Significance
numbering significance notation follow industry standard usage convention. That lower numbers have lower significance higher numbers have higher significance. range bits noted writing most significant least significant range separated colon (:). example, bits seven through zero written 7:0. bits five through register named SAMP written SAMP(5:2).
Byte Order
this document, lower order bytes stored lower addresses memory. When writing reading from ALDC1-40S-M interfaces (configured bytes wide), second (higher order) byte consecutively higher address than first byte. example, X'1234' written into CMND register, then +MDATA(15) through +MDATA(08) would X'12' +MDATA(07) through +MDATA(00) would X'34'. memory, X'12' address above X'34'. same holds true original data interface compressed data interface. Suppose long string bytes transferred into original data interface during compression operation. this example, first byte X'01', second byte X'02', third byte X'03', etc. Each higher order byte stored consecutively higher address. Then first transfer into original data interface, +ODATA(15) through +ODATA(08) would X'02' +ODATA(07) through +ODATA(00) would X'01'. interface configured byte wide, then order byte completely determined order which sent received from interface.
Binary Numbers
Binary numbers denoted this document, where binary number being represented. example, '1010' binary representation decimal ten. '11000101' equivalent 197.
Hexadecimal Numbers
Hexadecimal numbers denoted X'## this document, where hexadecimal number represented. example, hexadecimal representation decimal ten. X'2CBE' equivalent 11454.
Signal Names
signal names written this document using special font. name -RESET (the ALDC1-40S-M hardware reset pin) demonstrates this font. addition, signal name begins with then always positive active +ODATA(04)). signal name begins with then always negative active -RESET). signal name does begin with then active state undefined configurable.
Device Controller
Asynchronous handshaking protocols distinguish between devices (sometimes called slaves) controllers (sometimes called masters Within this document, references made devices controllers following convention: Device device circuitry which generates request signal receives acknowledge signal. Controller controller circuitry which receives request signal generates acknowledge signal.
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Note: concept device controller used when discussing synchronous communication.
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Appendix ALDC Compression Products
Figure (Page ALDC Compression Products
PRODUCT NAME (OEM CATALOG NUMBER) ALDC1-5S-L (IBM22-ALDC1005S-00)
PACKAGE lead quad flat package. body size with lead spacing. lead plastic flat package. body size with 0.65 lead spacing.
DESCRIPTION Maximum MB/s data rate compression decompression. microprocessor interface, original data interface, compressed data interface one-byte wide data buses. Maximum MB/s data rate compression decompression. microprocessor interface, original data interface, compressed data interface one-byte wide data buses. Maximum MB/s data rate compression decompression. microprocessor interface uses one- twobyte wide data which operates handshaking modes. original data interface compressed data interface one- two-byte wide data buses which operate four handshaking modes. Maximum MB/s data rate compression decompression. microprocessor interface uses one- twobyte wide data which operates handshaking modes. original data interface compressed data interface one- two-byte wide data buses which operate four asynchronous synchronous handshaking modes.
AVAILABILITY
ALDC1-5S-P (IBM22-ALDC1005S-01)
ALDC1-20S-H (IBM22-ALDC1020S-00)
lead plastic flat package with heat spreader. body size with 0.65 lead spacing.
ALDC1-40S-M (IBM22-ALDC1040S-00)
lead plastic flat package with molded heat sink. body size with 0.65 lead spacing.
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Figure
(Page ALDC Compression Products
PRODUCT NAME (OEM CATALOG NUMBER) ALDC1-20S-HA (IBM22-ALDC1020S-01)
PACKAGE lead plastic flat package with heat spreader. body size with 0.65 lead spacing.
DESCRIPTION Maximum MB/s data rate compression decompression. microprocessor interface uses one-byte wide data which operates handshaking modes. original data interface compressed data interface oneor two-byte wide data buses which operate four handshaking modes.
AVAILABILITY
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ALDC1-40S-M Data Compression
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Contact Microelectronics Division
REGION United States Canada: ADDRESS Microelectronics Division 1580 Route Building Hopewell Junction, 12533-6531 Pompignane 1021 34006 Montpellier France Informations Systeme GmbH Laatzener Strasse 30539 Hannover Germany Japan: Ichimiyake Yasu-cho, Yasu-gun Shiga-ken, Japan 520-23 TELEPHONE NUMBER (800) IBM-0181 ext: (33) 6713-5757 (Francais) (33) 6713-5756 (Italiano) (33) 6713-5750 (FAX)* *From Paris (49) 511-516-3444 (English) (49) 511-516-3555 (Deutsch) (49) 511-516-3888 (FAX) (81) 775-87-4745 (81) 775-87-4735 (FAX)
Europe:
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Printed U.S.A.
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