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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04 Jun


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ALDC1-5S Data Sheet
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04 June 1994
Microelectronics
ALDC1-5S Data Compression
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
This document contain preliminary information subject change without notice. assumes responsibility liability information contained herein. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. products described this document intended implantation other direct life support applications where malfunction result direct physical harm injury persons. WARRANTIES KIND, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, OFFERED THIS DOCUMENT. registered trademark International Business Machines Corporation. following terms denoted this document trademarks United States and/or other countries: Microelectronics. Copyright International Business Machines Corporation 1993, 1994. rights reserved. Note U.S. Government Users Documentation related restricted rights Use, duplication disclosure subject restrictions forth Schedule Contract with Corp.
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
ALDC1-5S Data Compression
Microelectronics
Contents
Chapter Product Overview Distinctive Features Package Part Number Quality 1.4.1 Reliability
3.4.1 Worst Case Expansion
Chapter Functional Description Functional Areas 2.1.1 Microprocessor Interface 2.1.2 Original Data Interface 2.1.3 Compressed Data Interface 2.1.4 Clock Generation 2.1.5 ALDC Encoder 2.1.6 ALDC Decoder Data Transfer Operations 2.2.1 Compression 2.2.2 Decompression
Chapter Hardware Interface Timing Microprocessor Interface Original Data Interface Compressed Data Interface 4.3.1 Compressed Data Interface FIFO Operation Clock Interface 4-10 Chapter Description ALDC1-5S-L ALDC1-5S-P
Chapter Microprocessor Interface Registers 3.1.1 Status (STAT) 3.1.2 Level (ECL) 3.1.3 Original Data Interface Transfer Count (TCO) 3.1.4 Compressed Data Interface Transfer Count (TCC) 3.1.5 Error Status (ERRS) 3.1.6 Command (CMND) 3.1.7 Transfer Size (XFR) 3.1.8 Compressed Data Interface Configuration (CCNF) Interrupt Resets Data Expansion
Chapter Electrical Characteristics Recommended Operating Conditions Absolute Maximum Minimum Ratings Characteristics Characteristics Clock Frequency Chapter Physical Dimensions ALDC1-5S-L ALDC1-5S-P Appendix Notation Significance Binary Numbering Hexadecimal Numbering Direct Memory Access
Appendix ALDC Compression Products Contact Microelectronics
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Microelectronics
ALDC1-5S Data Compression
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
ALDC1-5S Data Compression
Microelectronics
Chapter Product Overview
ALDC stands Adaptive, Lossless, Data Compression. ALDC1-5S cost, high speed data compression product data storage data transmission applications. Using ALDC compression algorithm, ALDC1-5S achieve average compression ratio approximately 3:1. Many applications flexible ALDC1-5S hardware interface. Also, ALDC1-5S's hardware interface allows growth capability future.
Package
ALDC1-5S designed CMOS micron triple-level metal gate array/standard cell technology. There package options: ALDC1-5S-L body size. 100-lead quad flat package with lead spacing. suitable PCMCIA applications. ALDC1-5S-P body size. 100-lead plastic flat package with 0.65 lead spacing. Section Chapter page gives detailed physical dimension information. Other packaging options available suit application system requirements.
Distinctive Features
ALDC1-5S single clock input. ALDC1-5S interfaces with common CMOS/TTL circuits. ALDC1-5S requires additional external memory single chip data compression solution. ALDC1-5S operates sustained speeds MB/s. Compression decompression data rates symmetrical. ALDC1-5S comes package options. ALDC1-5S compresses decompresses data blocks 65,535 bytes. ALDC1-5S provides simple, eight bit, programmable interface controlling microprocessor. microprocessor interface supports both polling-driven interrupt-driven applications. original data interface eight bit, asynchronous direct memory access interface. compressed data interface eight bit, asynchronous burst mode direct memory access interface. compressed data interface contains configurable, sixteen-byte FIFO buffer.
Part Number
Your Marketing Representative will help obtain ALDC1-5S. Original Equipment Manufacturer (OEM) catalog number quad flat package IBM22-ALDC1005S-00. Original Equipment Manufacturer (OEM) catalog number plastic flat package IBM22-ALDC1005S-01. ALDC1-5S-L part number 50G6935. ALDC1-5S-P part number 03H4969.
Quality
ALDC1-5S Acceptable Quality Level (AQL) less. Customers with different requirements should contact your Marketing Representative. Customers should return module believed defective. will replace module confirmed defective manufacturing tests. encourage return defective modules. failure analysis results obtained from these modules help improve quality products.
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ALDC1-5S Data Compression
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
1.4.1 Reliability
ALDC1-5S offered with module level burn-in. reliability objective end-oflife Average Failure Rate (AFR) equal less than PPM/KPOH nominal temperature voltage conditions. This includes Early Failure Rate (EFR) contribution equal less
than PPM/KPOH. Customers with different requirements should contact your Marketing Representative.
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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
ALDC1-5S Data Compression
Microelectronics
Chapter Functional Description
ALDC1-5S provides microprocessor interface, original data interface, compressed data interface, clock input. Internal ALDC1-5S ALDC encoder, ALDC decoder, ALDC1-5S registers. Figure shows these functional areas.
Device
Interface Original Data Interface
2.1.2 Original Data Interface
original data interface accepts data compression provides decompressed data external device connected original data interface counts bytes original data received during compression operations bytes decompressed data sent during decompression operations. This count available Original Data Interface Transfer Count (TCO) register. Section page describes original data interface timing detail.
Registers
ALDC Encoder ALDC Decoder
2.1.3 Compressed Data Interface
compressed data interface accepts compressed data decompression from external controller connected compressed data interface provides compressed data external controller. compressed data interface counts bytes compressed data received during decompression operations bytes compressed data sent during compression operations. This count available Compressed Data Interface Transfer Count (TCC) register. compressed data interface buffers data during data transfer operations sixteenbyte FIFO. compressed data interface operates burst mode which makes bytes available external controller stream. Section page describes compressed data interface timing detail.
clock Clock Generation
Compressed Data Interface
Controller
Figure
2-1. ALDC1-5S Functional Areas
Functional Areas
2.1.1 Microprocessor Interface
microprocessor interface allows microprocessor query status control ALDC1-5S. ALDC1-5S registers externally accessible through microprocessor interface. These registers provide primary means which ALDC1-5S microprocessor communicate. Section page describes microprocessor interface timing detail. Section page describes ALDC1-5S registers detail.
2.1.4 Clock Generation
clock generation circuitry accepts single clock input. generates internal clocks necessary ALDC1-5S function. Section page 4-10 describes clock timing detail.
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ALDC1-5S Data Compression
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
2.1.5 ALDC Encoder
ALDC encoder accepts data bytes from original data interface provides compressed data bytes compressed data interface. ALDC implementation adaptive Lempel-Ziv lossless compression algorithm accomplishes this function. ALDC encoder contains 512-byte content addressable memory (CAM). history buffer during compression operations. ALDC encoder concatenates marker control code compressed data. also pads remaining bits with zeros align evenly byte boundary.
Transfer Size (XFR) register specifies number bytes transfer during data transfer operation. This number sometimes called frame size. microprocessor must load register before data transfer operation begin. Compressed Data Interface Configuration (CCNF) register specifies Compressed Data Interface FIFO Threshold value. This value tunes compressed data interface performance meet application system requirements. microprocessor typically loads CCNF register after hardware software resets. more information, 4.3.1 page 4-9. Command (CMND) register specifies which data transfer other) operation perform. When microprocessor writes Start Compression Start Decompression opcode into CMND register, then data transfer operation begins. transfer proceeds until complete, reset occurs, error occurs. error occurs, ALDC1-5S sets appropriate error status bits, asserts -UPIRQ output, cancels transfer operation. Depending type error, microprocessor reset ALDC1-5S, attempt retry entire transfer, and/or report failure. When data transfer successful, ALDC1-5S sets Done (STAT(0)) asserts -UPIRQ output. After data transfer operation ended, microprocessor prepares ALDC1-5S next operation. -UPIRQ returns high (inactive) automatically when data transfer operation starts when reset occurs.
2.1.6 ALDC Decoder
ALDC decoder accepts compressed data bytes from compressed data interface provides reconstructed data bytes original data interface. ALDC implementation adaptive Lempel-Ziv lossless compression algorithm accomplishes this function. ALDC decoder contains 512-byte random access memory (RAM). history buffer during decompression operations. ALDC decoder expects find marker control code final data received from compressed data interface. does detect marker control code, then asserts ALDC decoder error. detects marker control code, then strips marker control code from decompressed data stream.
2.2.1 Compression
original data interface receives data from external direct memory access device sends ALDC encoder. ALDC encoder compresses data sends compressed data interface. compressed data interface sends compressed data external direct memory access controller. following sequence occurs: ALDC1-5S clears history buffer, resets transfer count registers (TCO TCC) X'0000', resets Error Status (ERRS) register X'00', sets Status (STAT) register X'80' (ie. Busy).
Data Transfer Operations
ALDC1-5S data transfer operations. These compression decompression. data transfer operations allow data pass between original data interface compressed data interface. important note that data passes through ALDC1-5S. ALDC1-5S carries appropriate operations data flows from source (ie. external direct memory access device) destination (external direct memory access controller) and, later, when flows back again.
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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
ALDC1-5S Data Compression
Microelectronics
ALDC1-5S enables original data interface receive data enables compressed data interface send data. ALDC1-5S receives, compresses, sends data until original data interface transfer count (TCO) equals transfer size (XFR). original data interface signals data encoder. encoder adds marker compressed data stream. When compressed data interface sends marker, ALDC1-5S asserts -UPIRQ output sets Done (STAT(0)) one. error occurs during compression operation then -UPIRQ output immediately asserted, Error (STAT(1)) one, proper Error Status (ERRS) register also one, transfer cancelled.
pressed data external direct memory access device. following sequence occurs: ALDC1-5S clears history buffer, resets transfer count registers (TCO TCC) X'0000', resets Error Status (ERRS) register X'00', sets Status (STAT) register X'80' (ie. Busy). ALDC1-5S enables compressed data interface receive data enables original data interface send data. ALDC1-5S receives, decompresses, sends data until compressed data interface transfer count (TCC) equals transfer size (XFR). compressed data interface signals data decoder. decoder strips marker which encoder added. When original data interface sends last decompressed byte, -UPIRQ output asserted Done (STAT(0)) one. error occurs during decompression operation then -UPIRQ output immediately asserted, Error (STAT(1)) one, proper Error Status (ERRS) register also one, transfer cancelled.
2.2.2 Decompression
compressed data interface receives compressed data from external direct memory access controller sends ALDC decoder. ALDC decoder decompresses data sends original data interface. original data interface sends decom-
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ALDC1-5S Data Compression
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
ALDC1-5S Data Compression
Microelectronics
Chapter Microprocessor Interface
Registers
ALDC1-5S sixteen registers which addressed using four address bus. Each register eight bits wide. ALDC1-5S expects single, encoded chip select which activates microprocessor interface registers. Figure shows registers ALDC1-5S.
Figure 3-1. ALDC1-5S Registers
UPADDR X'0' X'1' X'2' X'3' X'4' X'5' X'6' X'7' X'8' X'9' X'C' X'D' X'E' X'F'
MNEMONIC STAT TCOH TCOL TCCH TCCL ERRS
REGISTER NAME Status Level Original Data Interface Transfer Count (High) Original Data Interface Transfer Count (Low) Compressed Data Interface Transfer Count (High) Compressed Data Interface Transfer Count (Low) Error Status Reserved
REFERENCE 3.1.1 3.1.2 page 3.1.3 page 3.1.3 page 3.1.4 page 3.1.4 page 3.1.5 page 3.1.6 page 3.1.7 page 3.1.7 page
CMND
Command Reserved
XFRH XFRL
Transfer Size (High) Transfer Size (Low) Reserved Reserved Reserved
CCNF
Compressed Data Interface Configuration
3.1.8 page
3.1.1 Status (STAT)
UPADDR: X'0' Type: Read
Status (STAT) register provides status bits microprocessor. STAT reset X'00' hardware software reset. Status register layout given Figure 3-2.
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ALDC1-5S Data Compression
Figure
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
Figure
3-2. Status Register
3-3. Level Register
NAME/NOTES Busy This ALDC1-5S when data transfer operation initiated microprocessor reset zero when transfer completed successfully, when error occurs, when reset occurs.
NAME/NOTES Level ALDC1-5S, value these bits '11101100'.
3.1.3 Original Data Interface Transfer Count (TCO)
UPADDR: X'2' X'3' Type: Read
Original Data Interface Transfer Count (TCO) register provides number bytes transferred original data interface current data transfer operation. byte register with most significant byte contained Original Data Interface Transfer Count High (TCOH) least significant byte contained Original Data Interface Transfer Count (TCOL). reset X'0000' hardware software reset. Also, reset X'0000' when data transfer operation initialized. Original Data Interface Transfer Count register layout given Figure 3-4. During compression operation, incremented each original data byte received original data interface. When equals during compression, bytes compression operation have been received ALDC1-5S. During decompression operation, incremented each decompressed data byte sent original data interface.
Figure (Page Original Data Interface Transfer Count Register
Reserved Expansion This when ALDC1-5S detects that Compressed Data Interface Transfer Count (TCC) register larger than Original Data Interface Transfer Count (TCO) register compression operation. section page discussion data expansion.
Reserved Error This logical error bits Error Status (ERRS) register.
Done This when ALDC1-5S completed current data transfer operation.
3.1.2 Level (ECL)
UPADDR: X'1' Type: Read
Level (ECL) register provides engineering change information bits microprocessor. never reset. Level register layout given Figure 3-3.
15:8
NAME/NOTES Original Data Interface Transfer Count (High) Accessed through address X'2' microprocessor interface.
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ALDC1-5S Data Compression
Microelectronics
Figure
(Page Original Data Interface Transfer Count Register
NAME/NOTES Original Data Interface Transfer Count (Low) Accessed through address X'3' microprocessor interface.
received compressed data interface. When equals during decompression, bytes decompression operation have been received ALDC1-5S. During compression operation, incremented each compressed data byte sent compressed data interface.
Figure 3-5. Compressed Data Interface Transfer Count Register
Notes: Because time needed complete outstanding compression operations final bytes received during compression, cannot used determine when compression operation complete. Done (STAT(0)) used this purpose. sixteen register. Attempting transfer kilobytes more data will result register overflow. Therefore, application system designer must ensure that data partitioned into data blocks smaller than kilobytes, that each data block compressed decompressed separately. section page discussion data expansion.
15:8
NAME/NOTES Compressed Data Interface Transfer Count (High) Accessed through address X'4' microprocessor interface.
Compressed Data Interface Transfer Count (Low) Accessed through address X'5' microprocessor interface.
Notes: Because time needed complete outstanding decompression operations final bytes received during decompression, cannot used determine when decompression operation complete. Done (STAT(0)) used this purpose. sixteen register. Attempting transfer kilobytes more data will result register overflow. Therefore, application system designer must ensure that data partitioned into data blocks smaller than kilobytes, that each data block compressed decompressed separately. section page discussion data expansion.
3.1.4 Compressed Data Interface Transfer Count (TCC)
UPADDR: X'4' X'5' Type: Read
Compressed Data Interface Transfer Count (TCC) register provides number bytes transferred compressed data interface current data transfer operation. byte register with most significant byte contained Compressed Data Interface Transfer Count High (TCCH) least significant byte contained Compressed Data Interface Transfer Count (TCCL). reset X'0000' hardware software reset. Also, reset X'0000' when data transfer operation initialized. Compressed Data Interface Transfer Count register layout given Figure 3-5. During decompression operation, incremented each compressed data byte
3.1.5 Error Status (ERRS)
UPADDR: X'6' Type: Read
Error Status (ERRS) register provides error status bits microprocessor. ERRS reset X'00' hardware software reset. Error Status register layout given Figure 3-6.
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Figure
Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
Figure
3-6. Error Status Register
3-7. ALDC1-5S Opcodes
NAME/NOTES Reserved Compressed Data Interface Transfer Count (TCC) Overflow Error This error ALDC1-5S detects carry Compressed Data Interface Transfer Count (TCC) register.
OPCODE X'00' X'20'
NAME/NOTES operation performed. Test High Impedance When this opcode written CMND, output bidirectional pins placed into high impedance state. This command useful isolate ALDC1-5S from external circuits.
Original Data Interface Transfer Count (TCO) Overflow Error This error ALDC1-5S detects carry Original Data Interface Transfer Count (TCO) register. X'58'
Start Compression section 2.2.1 page detailed description this data transfer operation.
ALDC Decoder Control Code Error This error during decompression ALDC1-5S detects invalid control code compressed data stream.
X'68'
Start Decompression section 2.2.2 page detailed description this data transfer operation.
X'A0'
Software Reset When this opcode written CMND, registers (except CMND) reset X'00'.
ALDC Decoder Error This error during decompression ALDC1-5S detects control code before Compressed Data Interface Transfer Count (TCC) equals Transfer Size (XFR) ALDC1-5S does detect control code equals XFR.
Note: Opcodes explicitly named this table reserved future use. They invalid ALDC1-5S will produce operation.
Figure 3-8. Command Register
3.1.6 Command (CMND)
UPADDR: X'8' Type: Read/Write
Command (CMND) register used microprocessor program operations ALDC1-5S. CMND reset X'00' hardware reset. CMND changed software reset. opcodes given Figure Command register layout given Figure 3-8.
NAME/NOTES Opcode Figure proposed opcode descriptions.
3.1.7 Transfer Size (XFR)
UPADDR: X'A' X'B' Type: Read/Write
Transfer Size (XFR) register allows microprocessor control number bytes transferred during data transfer operation. byte register with most significant byte contained Transfer Size High (XFRH) least significant byte contained Transfer Size (XFRL). reset X'0000' hardware software reset.
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ALDC1-5S Data Compression
Figure
Microelectronics
Transfer Size register layout given Figure page 3-5. direction data transfer operation specifies whether Original Data Interface Transfer Count (TCO) register Compressed Data Interface Transfer Count (TCC) register used determine when data bytes have been received data transfer operation. During compression, used. During decompression, used. When appropriate transfer count register (TCO TCC) equals XFR, bytes current data transfer operation have been received ALDC1-5S.
Figure 3-9. Transfer Size Register
3-10. Compressed Data Interface Configuration Register
NAME/NOTES Reserved Compressed Data Interface FIFO Threshold These four bits specify Compressed Data Interface FIFO Threshold value. Values from '0001' '1111' valid. Note: reset value '0000') Compressed Data Interface FIFO Threshold bits will cause improper operation compressed data interface. These bits must valid value after every hardware software reset.
15:8
NAME/NOTES Transfer Size (High) Accessed through address microprocessor interface.
Transfer Size (Low) Accessed through address microprocessor interface.
Interrupt
hardware interrupt output ALDC1-5S named -UPIRQ. When active (low), indicates that either data transfer operation completed successfully that data transfer operation canceled prematurely error. microprocessor determines which these conditions activated hardware interrupt reading Status (STAT) register testing Error (STAT(1)) bit. Error one, then error occurred previously attempted data transfer operation. cause error then determined reading Error Status (ERRS) register. Error recovery procedures then invoked appropriate. Error zero, then error occurred previous data transfer operation therefore successful. hardware interrupt signal high (inactive) automatically when either hardware reset software reset occurs, when data transfer operation started. Note: -UPIRQ open drain output requires pull-up resistor. section Chapter page pull-up resistor selection considerations.
Note: sixteen register. This means that maximum data block size X'FFFF' 65,535) bytes. Therefore, application system designer must ensure that data partitioned into data blocks smaller than kilobytes, that each data block compressed decompressed separately. section page discussion data expansion.
3.1.8 Compressed Data Interface Configuration (CCNF)
UPADDR: X'F' Type: Read/Write
Compressed Data Interface Configuration (CCNF) register provides compressed data interface configuration capability microprocessor. CCNF reset X'00' hardware software reset. Compressed Data Interface Configuration register layout given Figure 3-10
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Product Part Number: IBM22-ALDC1005S Document Number: DCALD5DSU-04
Resets
There hardware reset ALDC1-5S. When asserted, registers (except ECL) reset zero, current operations cancelled, history buffer cleared. There software reset ALDC1-5S. software reset identical hardware reset
Figure 3-11. Effect Reset ALDC1-5S Registers.
except that Command (CMND) register changed. Figure 3-11 summarizes hardware software resets ALDC1-5S. Because some register's contents modified during initialization data transfer operations, this information also included figure below.
UPADDR
MNEMONIC
HARDWARE RESET X'00' unchanged X'00' X'00' X'00' X'00' X'00' X'00' X'00' X'00' X'00'
OPCODE X'A0': SOFTWARE RESET X'00' unchanged X'00' X'00' X'00' X'00' X'00' unchanged X'00' X'00' X'00'
DATA TRANSFER INITIALIZATION X'80' (Busy) unchanged X'00' X'00' X'00' X'00' X'00' unchanged unchanged unchanged unchanged
X'0' X'1' X'2' X'3' X'4' X'5' X'6' X'8' X'F'
STAT TCOH TCOL TCCH TCCL ERRS CMND XFRH XFRL CCNF
Data Expansion
Data expansion occurs when size data increases during compression operation. This rare occurrence because ALDC1-5S adapts data being compressed. However, application system designer must aware data expansion consider impact system operation. data expansion causes Compressed Data Interface Transfer Count (TCC) exceed 65,535 bytes, then ALDC1-5S would Overflow Error (ERRS(3)) one, Error (STAT(1)) one, assert -UPIRQ output, cancel transfer. ALDC1-5S also Expansion (STAT(3)) which used detect data expansion when errors occur.
3.4.1 Worst Case Expansion
ALDC compression algorithm approaches worst case 12.5% data expansion. example, given system always compresses 60,000 byte data blocks, then there small possibility that about 67,500 bytes result from worst case compression operation. Compressed Data Interface Transfer Count (TCC) would exceed 65,535 this case, ALDC1-5S would cancel compression operation with Overflow error. Continuing with example, microprocessor might detect that error occurred initiate recovery transferring original 60,000 bytes instead. example demonstrates data expansion might handled system level. application system designer determine appropriate system response data expansion.
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ALDC1-5S Data Compression
Microelectronics
Data modeling indicate that probability data expansion small nonexistent (for specific application). this case, application system designer need concerned about data expansion. Note: data expansion design concern, then following formula used calculate maximum allowable transfer size given compressed data buffer size: XFRmax INT( (CDB
data buffer size bytes, INT(x) integer function (sometimes called floor function). under control application system designer. compressed data buffer part ALDC1-5S. Rather, this document, compressed data buffer size describes byte limit imposed number compressed bytes output during compression operation. This limit might imposed because bus, memory, real-time, other system constraints. compressed data buffer size exists design, compressed data buffer size larger than 65,535 bytes, then XFRmax should 58,250.
where XFRmax maximum allowable transfer size bytes, compressed
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Chapter Hardware Interface Timing
Microprocessor Interface
ALDC1-5S provides asynchronous interface controlling microprocessor. ALDC1-5S chip select which used microprocessor show that wishes directly read write from register. microprocessor interface shown Figure 4-1. Read timing microprocessor interface shown Figure page 4-2. Write timing microprocessor interface shown Figure page 4-3. Hardware reset timing microprocessor interface shown Figure page 4-4.
Interface +UPADDR3+UPADDR0 (input) (input) +R/-W (input) -UPIRQ (open drain output)
+UPDATA7+UPDATA0 (bidirectional)
-RESET (input)
Figure
4-1. Microprocessor Interface
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+R/-W (input) (input)
\/Add.Valid\/ +UPADDR3_/\_/\_/\_/\_ +UPADDR0 (input) _/Data Valid\_+UPDATA7\_/ +UPDATA0 (bidi. out)
DESCRIPTION
clock cycles clock cycles clock cycle
+R/-W high before active +R/-W high after inactive active inactive inactive active +UPADDR valid before active +UPADDR hold time after active +UPDATA enable time after active +UPDATA hold time after inactive
clock cycle clock cycle
Usage note: microprocessor interface latches address falling edge -CS. user should latch output data rising edge -CS.
Figure 4-2. Microprocessor Interface Read Timing
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+R/-W (input) _\_/_\_/_ (input)
\/Add.Valid\/ +UPADDR3_/\_/\_/\_/\_ +UPADDR0 (input) \/DataValid\/ +UPDATA7_/\_/\_ +UPDATA0 (bidi.
Note:
DESCRIPTION
clock cycle clock cycles clock cycles
+R/-W before active +R/-W after active active inactive inactive active (See note +UPADDR valid before active +UPADDR hold time after active +UPDATA valid before inactive +UPDATA hold time after inactive
Minimum three clock cycles after software reset (opcode X'A0'). Usage note: microprocessor interface latches address falling edge -CS. microprocessor interface latches input data rising edge -CS.
Figure 4-3. Microprocessor Interface Write Timing
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-RESET (input)
(input) \_/_
Figure
DESCRIPTION
clock cycles clock cycles
-RESET active -RESET inactive -RESET inactive active
4-4. Microprocessor Interface Hardware Reset
Original Data Interface
original data interface works asynchronous direct memory access handshaking protocol. original data interface direct memory access controller expects connected external direct memory access device. Original Data Interface shown Figure 4-5. timing details transfer into original data interface shown Figure page 4-5. timing details
transfer original data interface shown Figure page 4-6.
Original Data Interface
-OACK (output) -OREQ (input) -ORD (output) -OWR (output)
+ODATA7+ODATA0 (bidirectional)
Figure
4-5. Original Data Interface
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-OREQ (input) -OACK (output) -ORD (output)
Data Valid \_+ODATA7\_/ +ODATA0 (bidi.
Notes:
DESCRIPTION
clock cycles clock cycles clock cycles clock cycles clock cycle
clock cycles clock cycles
-OREQ active -OREQ inactive -OREQ active -OACK active (See note -OREQ inactive -OACK inactive
(See note
-OACK inactive next -OREQ active -OACK/ -ORD pulse width (See note +ODATA valid before -OACK inactive +ODATA hold time after -OACK inactive
Maximum time assumes ALDC1-5S ready take data. ready take data, maximum approaches dominates necessary. -OWR inactive during transfers into original data interface. Usage note: original data interface latches input data rising edge -OACK. user should provide data latched falling edge -OACK output hold data least clock cycle after rising edge -OACK output. Also, user should follow four-edge handshaking protocol original data interface shown Figure page simplify timing.
Figure 4-6. Data Transfer into Original Data Interface (Compression)
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-OREQ (input)
-OACK (output) -OWR (output)
Data Valid \_+ODATA7\_/ +ODATA0 (bidi. out)
Notes:
DESCRIPTION
clock cycles clock cycles clock cycles clock cycles clock cycle
clock cycles clock cycles
-OREQ active -OREQ inactive -OREQ active -OACK active (See note -OREQ inactive -OACK inactive
(See note
-OACK inactive next -OREQ active -OACK/ -OWR pulse width (See note +ODATA enable time after -OACK active +ODATA hold time after -OACK inactive
clock cycle
Maximum time assumes ALDC1-5S ready send data. ready send data, maximum approaches dominates necessary. -ORD inactive during transfers original data interface. Usage note: user should latch output data rising edge -OACK. Also, user should follow four-edge handshaking protocol original data interface shown Figure page simplify timing.
Figure 4-7. Data Transfer Original Data Interface (Decompression)
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Compressed Data Interface
compressed data interface works asynchronous burst mode direct memory access handshaking protocol. sixteen byte FIFO buffer intrinsic part compressed data interface. compressed data interface shown Figure 4-9. timing details transfer into compressed data interface shown Figure 4-10. timing details transfer compressed data interface shown Figure 4-11 page 4-9.
Figure
4-8. Four-edge Handshaking. Although other timings allowed, four-edge handshaking protocol will simplify timing original data interface. shown, falling edge -OREQ causes -OACK become active. When falling edge -OACK detected, user -OREQ become inactive. rising -OREQ will turn cause -OACK become inactive, complete data transfer.
Compressed Data Interface
-CREQ (output) -CACK (input)
+CDATA7+CDATA0 (bidirectional)
Figure
4-9. Compressed Data Interface
-CREQ (output)
-CACK (input)
+CDATA0 (bidi.
Figure
4-10 (Part Data Transfer into Compressed Data Interface (Decompression)
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Note:
DESCRIPTION
clock cycles clock cycles clock cycles clock cycles
-CREQ active -CACK active -CACK active -CACK inactive -CACK inactive -CACK active Last -CACK active -CREQ inactive
burst
(See note
clock cycles
-CREQ inactive -CREQ active +CDATA valid before -CACK inactive +CDATA hold time after -CACK inactive
Maximum time exception condition last byte decompression transfer operation (ie. during decompression). exception condition occurs, maximum clock cycles Usage note: compressed data interface latches input data rising edge -CACK.
Figure 4-10 (Part Data Transfer into Compressed Data Interface (Decompression)
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-CREQ (output)
-CACK (input) +CDATA0 (bidi. out)
DESCRIPTION
clock cycles clock cycles clock cycles clock cycles clock cycle
-CREQ active -CACK active -CACK active -CACK inactive -CACK inactive -CACK active Last -CACK active -CREQ inactive
burst
clock cycles clock cycles
-CREQ inactive -CREQ active +CDATA enable time after -CACK active +CDATA hold time after -CACK inactive
Usage note: user should latch output data rising edge -CACK.
Figure 4-11. Data Transfer Compressed Data Interface (Compression)
4.3.1 Compressed Data Interface FIFO Operation
During compression data transfer operations, data transferred compressed data interface. FIFO starts empty accepts compressed data from ALDC encoder. When FIFO accepts number compressed data bytes equal Compressed Data Interface FIFO Threshold (CCNF(3:0)), switches -CREQ active (and continues accepting compressed data). When external direct memory access controller responds active -CREQ active -CACK), compressed data interface enables +CDATA drivers outputs first available byte. This byte remains +CDATA until -CACK goes inactive. -CACK continue
these transitions from high back high again, each time getting next byte +CDATA until -CREQ goes inactive. -CREQ will inactive (high) only FIFO empty. During decompression data transfer operations, data transferred into compressed data interface. FIFO accepts compressed data from external direct memory access controller. When FIFO becomes full during decompression operation, stops requesting more data switching -CREQ high. When number empty spaces FIFO equals Compressed Data Interface FIFO Threshold (CCNF(3:0)), switches -CREQ active (low). Data transferred during compression) rising edge -CACK. Transfer continues until Compressed Data Interface Transfer Count (TCC) equals ALDC1-5S
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Transfer Size (XFR), which point -CREQ stays inactive. information programming Compressed Data Interface FIFO Threshold (CCNF(3:0)), 3.1.8 page 3-5. information programming register, 3.1.4 page 3-3. information programming register, 3.1.7 page 3-4.
clock interface shown Figure 4-12. Detailed clock timing information given Figure 4-13.
Clock Interface
+OSC (input)
Figure
4-12. Clock Interface
Clock Interface
+OSC signal clock input ALDC1-5S. timings microprocessor interface, original data interface, compressed data interface specified relative clock timing.
+OSC (input)
Figure
DESCRIPTION
+OSC period +OSC rise time +OSC width high +OSC fall time +OSC width
4-13. Clock Timing
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4-10
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Chapter Description
This chapter describes layout ALDC1-5S-L ALDC1-5S-P. diagrams show locations tables show names, signal directions, descriptions pins respective packages. physical dimensions both packages provided Chapter page 7-1.
ALDC1-5S-L
Figure
5-1. ALDC1-5S-L Numbering Diagram. numbering starts upper right corner with proceeds counterclockwise direction N25, then through W25, through S25, through E25. Figure corresponding names, signal directions, descriptions.
Figure
(Page ALDC1-5S-L Description. Figure identify locations.
NAME
DESCRIPTION Volt power supply pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. ground pin. test output. Must connected. test output. Must connected. Volt power supply pin. test output. Must connected. test output. Must connected.
+ODATA0 +ODATA1 +ODATA2 +ODATA3 +ODATA4 +ODATA5 +ODATA6 +ODATA7 TESTPOINT TESTPOINT TESTPOINT TESTPOINT
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Figure
(Page ALDC1-5S-L Description. Figure page identify locations.
NAME
DESCRIPTION Unused. tied high, tied low, connected. original data interface direct memory access acknowledge pin. original data interface direct memory access request pin. original data interface direct memory access controller write pin. original data interface direct memory access controller read pin. manufacturing test input. Must tied high. manufacturing test input. Must tied high. manufacturing test input. Must tied high. Unused. tied high, tied low, connected. ground pin. Volt power supply pin. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
-OACK -OREQ -OWR -ORD -TEST -TEST -TEST
-TEST -TEST TESTINPUT
manufacturing test input. Must tied high. manufacturing test input. Must tied high. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT
ground pin. manufacturing test input. tied high, tied low, connected. Volt power supply pin. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT
manufacturing test input. tied high, tied low, connected. manufacturing test input. tied high, tied low, connected.
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Figure
(Page ALDC1-5S-L Description. Figure page identify locations.
NAME
DESCRIPTION manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT
+OSC -RESET +R/-W -UPIRQ
ground pin. Volt power supply pin. system clock pin. ALDC1-5S hardware reset pin. microprocessor interface read write register control pin. microprocessor chip select pin. ground pin. microprocessor interrupt request pin. Note: -UPIRQ open drain output requires pull-up resistor. section Chapter page pull-up resistor selection considerations.
Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
+UPADDR0 +UPADDR1 +UPADDR2 +UPADDR3 +UPDATA0 +UPDATA1 +UPDATA2 +UPDATA3 +UPDATA4 +UPDATA5 +UPDATA6 +UPDATA7 +CDATA0 +CDATA1 +CDATA2
microprocessor register address pin. microprocessor register address pin. Volt power supply pin. microprocessor register address pin. microprocessor register address pin. ground pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. ground pin. Volt power supply pin.
compressed data interface data pin. compressed data interface data pin. compressed data interface data pin.
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Figure
(Page ALDC1-5S-L Description. Figure page identify locations.
NAME
DESCRIPTION compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. Unused. tied high, tied low, connected. ground pin.
+CDATA3 +CDATA4 +CDATA5 +CDATA6 +CDATA7 TESTINPUT TESTINPUT
manufacturing test input. tied high, tied low, connected. Volt power supply pin. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT -TEST -CACK -CREQ
manufacturing test input. tied high, tied low, connected. manufacturing input. tied high, tied low, connected. manufacturing test input. Must tied high. Unused. tied high, tied low, connected. compressed data interface direct memory access acknowledge pin. compressed data interface direct memory access request pin. ground pin.
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ALDC1-5S-P
Figure
5-3. ALDC1-5S-P Numbering Diagram. numbering starts upper right corner with proceeds counterclockwise direction N30, then through W20, through S30, through E20. Figure corresponding names, signal directions, descriptions.
Figure
(Page ALDC1-5S-P Description. Figure identify locations.
NAME
DESCRIPTION compressed data interface direct memory access request pin. ground pin. Volt power supply pin.
-CREQ +ODATA0 +ODATA1 +ODATA2 +ODATA3 +ODATA4 +ODATA5 +ODATA6 +ODATA7 TESTPOINT TESTPOINT TESTPOINT TESTPOINT -OACK
original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. original data interface data pin. ground pin. test output. Must connected. test output. Must connected. Volt power supply pin. test output. Must connected. test output. Must connected. Unused. tied high, tied low, connected. original data interface direct memory access acknowledge pin.
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Figure
(Page ALDC1-5S-P Description. Figure page identify locations.
NAME
DESCRIPTION original data interface direct memory access request pin. original data interface direct memory access controller write pin. original data interface direct memory access controller read pin. manufacturing test input. Must tied high. manufacturing test input. Must tied high. manufacturing test input. Must tied high. Unused. tied high, tied low, connected. ground pin. Volt power supply pin. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
-OREQ -OWR -ORD -TEST -TEST -TEST
-TEST -TEST TESTINPUT
manufacturing test input. Must tied high. manufacturing test input. Must tied high. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT
ground pin. manufacturing test input. tied high, tied low, connected. Volt power supply pin. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT TESTINPUT
manufacturing test input. tied high, tied low, connected. manufacturing test input. tied high, tied low, connected. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected.
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Figure
(Page ALDC1-5S-P Description. Figure page identify locations.
NAME
DESCRIPTION Unused. tied high, tied low, connected. ground pin. Volt power supply pin.
+OSC -RESET +R/-W -UPIRQ
system clock pin. ALDC1-5S hardware reset pin. microprocessor interface read write register control pin. microprocessor chip select pin. ground pin. microprocessor interrupt request pin. Note: -UPIRQ open drain output requires pull-up resistor. section Chapter page pull-up resistor selection considerations.
Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
+UPADDR0 +UPADDR1 +UPADDR2 +UPADDR3 +UPDATA0 +UPDATA1 +UPDATA2 +UPDATA3 +UPDATA4 +UPDATA5 +UPDATA6 +UPDATA7 +CDATA0 +CDATA1 +CDATA2 +CDATA3 +CDATA4 +CDATA5
microprocessor register address pin. microprocessor register address pin. Volt power supply pin. microprocessor register address pin. microprocessor register address pin. ground pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. microprocessor register data pin. ground pin. Volt power supply pin.
compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. compressed data interface data pin. compressed data interface data pin.
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Figure
(Page ALDC1-5S-P Description. Figure page identify locations.
NAME
DESCRIPTION compressed data interface data pin. compressed data interface data pin. Unused. tied high, tied low, connected. ground pin.
+CDATA6 +CDATA7 TESTINPUT TESTINPUT
manufacturing test input. tied high, tied low, connected. Volt power supply pin. manufacturing test input. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected. Unused. tied high, tied low, connected.
TESTINPUT TESTINPUT -TEST -CACK
manufacturing test input. tied high, tied low, connected. manufacturing test input. tied high, tied low, connected. manufacturing test input. Must tied high. Unused. tied high, tied low, connected. compressed data interface direct memory access acknowledge pin.
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Chapter Electrical Characteristics
Recommended Operating Conditions
Figure 6-1. Recommended Operating Conditions
Note:
PARAMETER Supply Voltage Input Voltage Output Voltage Ambient Operating Temperature Case Temperature Input Rise Time Input Fall Time
(See note (See note
4.75
5.00
5.25
UNIT
Measured from Vdd.
Absolute Maximum Minimum Ratings
Figure 6-2. Absolute Maximum Minimum Ratings. These absolute maximum minimum values that applied extended periods time without damaging ALDC1-5S. Circuit functionality implied.
Note:
PARAMETER Supply Voltage Storage Temperature Power Dissipation
(See note
1.63
UNIT
Worst case power dissipation maximum data transfer rate MB/s) 5.25
Characteristics
Figure (Page Characteristics. difference observed input current -CS, -RESET, +R/-W, -CACK, -OREQ, -TEST inputs internal pull-up resistors these inputs. differences observed output voltages currents -UPIRQ output open-drain driver this output.
PARAMETER Positive Logic Level Input Voltage Negative Logic Level Input Voltage
2.00 0.30
5.00 0.00
5.25 0.80
UNIT
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Figure
(Page Characteristics. difference observed input current -CS, -RESET, +R/-W, -CACK, -OREQ, -TEST inputs internal pull-up resistors these inputs. differences observed output voltages currents -UPIRQ output open-drain driver this output.
PARAMETER Positive Logic Level Input Current Negative Logic Level Input Current inputs except -CS, -RESET, +R/-W, -CACK, -OREQ, -TEST.
UNIT
Negative Logic Level Input Current -CS, -RESET, +R/-W, -CACK, -OREQ, -TEST inputs.
Positive Logic Level Output Voltage outputs except -UPIRQ. Negative Logic Level Output Voltage outputs except -UPIRQ. Negative Logic Level Output Voltage -UPIRQ output. Positive Logic Level Output Current outputs except -UPIRQ. Negative Logic Level Output Current outputs except -UPIRQ. Negative Logic Level Output Current -UPIRQ output.
(See note
2.40
5.00
5.25
0.00
0.00
0.50
0.00
0.00
0.40
High Impedance Leakage Current Supply Current Leakage current clock frequency.
Note:
Input Capacitance Output Capacitance
negative logic level output current -UPIRQ output sets lower bound choice pull-up resistor used. Pull-up resistor -UPIRQ output should less than 5.25 0.02
Characteristics
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Figure
6-4. Characteristics. differences observed output transition times -UPIRQ output open-drain driver this output.
PARAMETER Negative Logic Level Positive Logic Level Output Transition Time outputs except -UPIRQ.
note (See
UNIT
Positive Logic Level Negative Logic Level Output Transition Time outputs except -UPIRQ.
note (See
Negative Logic Level Positive Logic Level Output Transition Time -UPIRQ output.
(See notes
38.6
ns/k
Positive Logic Level Negative Logic Level Output Transition Time -UPIRQ output.
(See note
Notes: Worst case 4.75 load capacitance (CL) 50pf. Transition time dependent value pull-up resistor used. example, using 2000 resistor pull-up -UPIRQ output gives maximum 38.6 77.2
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Clock Frequency
Figure
6-5. Clock Frequency. Maximum measured maximum input output data rates 5.25 given clock frequency. Minimum measured standby state data input output) 4.75 given clock frequency. clock frequency measured +OSC input.
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Chapter Physical Dimensions
ALDC1-5S-L ALDC1-5S-P
Figure
7-1. ALDC1-5S-L Side Views. length tolerance dimensions millimeters. orientation mark shown lower left-hand corner view.
Figure
7-3. ALDC1-5S-P Side Views. length tolerance dimensions millimeters. orientation mark shown lower left-hand corner view.
Figure Figure 7-2. ALDC1-5S-L Close-up View. length tolerance dimensions millimeters.
7-4. ALDC1-5S-P Close-up View. length tolerance dimensions millimeters.
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Appendix Notation
Significance
numbering significance notation follow industry standard usage convention. That lower numbers have lower significance higher numbers have higher significance. range bits noted writing most significant least significant range separated colon (:). example, bits zero through seven written 7:0. bits through five register named SAMP written SAMP(5:2).
Hexadecimal Numbering
Hexadecimal numbers denoted X'## this document, where hexadecimal number represented. example, hexadecimal representation decimal ten. X'2CBE' equivalent 11454.
Direct Memory Access
Direct Memory Access (DMA) common, asynchronous handshaking protocol used send receive information between components digital systems. Within this document, references made devices controllers. Device direct memory access device circuitry which generates Request signal receives Acknowledge signal. Controller direct memory access controller circuitry which receives Request signal generates Acknowledge signal.
Binary Numbering
Binary numbers denoted this document, where binary number being represented. example, '1010' binary representation decimal ten. '11000101' equivalent 197.
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Appendix ALDC Compression Products
Figure B-1. ALDC Compression Products
PRODUCT NAME (OEM CATALOG NUMBER) ALDC1-5S-L (IBM22-ALDC1005S-00)
PACKAGE lead quad flat package. body size with lead spacing. lead plastic flat package. body size with 0.65 lead spacing.
DESCRIPTION Maximum MB/s data rate compression decompression. microprocessor interface, original data interface, compressed data interface one-byte wide data buses. Maximum MB/s data rate compression decompression. microprocessor interface, original data interface, compressed data interface one-byte wide data buses. Maximum MB/s data rate compression decompression. microprocessor interface uses one- twobyte wide data which operates handshaking modes. original data interface compressed data interface one- two-byte wide data buses which operate four handshaking modes. Maximum MB/s data rate compression decompression. microprocessor interface uses one- twobyte wide data which operates handshaking modes. original data interface compressed data interface one- two-byte wide data buses which operate four asynchronous synchronous handshaking modes.
AVAILABILITY
ALDC1-5S-P (IBM22-ALDC1005S-01)
ALDC1-20S-H (IBM22-ALDC1020S-00)
lead plastic flat package with heat spreader. body size with 0.65 lead spacing.
Samples
ALDC1-40S-M (IBM22-ALDC1040S-00)
lead plastic flat package with molded heat sink. body size with 0.65 lead spacing.
Samples
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Contact Microelectronics
REGION United States: ADDRESS Microelectronics Document Distribution Center P.O. 7932 Mount Prospect, 60056-7932 Eurocoordination S.A. Microelectronics D/8142-TPS Cedex 92066 Paris-la-Defense France TELEPHONE NUMBER (800) IBM-0181
Europe:
(708) 296-9300
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Printed U.S.A.

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