Communications Advanced Consumer Technologies Group M68000 A

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Communications Advanced Consumer Technologies Group M68000 A

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Communications Advanced Consumer Technologies Group
M68000
Addendum
M68000 User Manual
August 1997 This addendum M68000UM/AD User's Manual, Revision provides corrections original text well additional information. This document other information this product maintained World Wide http://www.motorola.com/68000.
OVERVIEW
This manual includes hardware details programming information MC68HC000, MC68HC001, MC68EC000, MC68SEC000. ease reading, name M68000 MPUs will used when referring processors. Refer M68000PM/AD, M68000 Programmer's Reference Manual, detailed information MC68000 instruction set. four microprocessors very similar each other contain following features: Sixteen 32-Bit Data Address Registers 16-Mbyte Direct Addressing Range Program Counter Instruction Types Operations Five Main Data Types Memory-Mapped Input/Output (I/O) Addressing Modes
following processors contain additional features: MC68HC001/MC68EC000/MC68SEC000 Statically selectable 16-bit data
power
This document contains information product under development. Motorola reserves right change discontinue this product without notice.
SEMICONDUCTOR PRODUCT INFORMATION
1997 Motorola, Inc. Rights Reserved.
primary features MC68SEC000 embedded processor include following: Direct Replacement MC68EC000 Pin-for-pin compatibility with MC68EC000 plastic TQFP packages Vast selection existing third-party development tools MC68EC000 support MC68SEC000 Software written MC68EC000 will unchanged MC68SEC000
Power Management Low-power HCMOS technology Static design allows stopping processor clock 3.3V operation Typical 0.5µA current consumption 3.3V sleep mode
Software Strength Fully upward object-code compatible with other M68000 Family products M68000 architecture allows effective assembly code with compiler
Upgrade Fully upward code-compatible with higher performance 680x0 68300 Family members ColdFire® code-compatible with minor modifications
MC68HC000
primary benefit MC68HC000 reduced power consumption. device dissipates less power order magnitude) than NMOS MC68000. MC68HC000 implementation M68000 16/-32 microprocessor architecture. MC68HC000 16-bit data implementation MC68000 upward code-compatible with MC68010 MC68020 32-bit implementation architecture.
MC68HC001
MC68HC001 provides functional extension MC68HC000 HCMOS 16-/32-bit microprocessor with addition statically selectable 16-bit data operation. MC68HC001 object-code compatible with MC68HC000. migrate code written MC68HC001 without modification member M68000 Family.
MC68EC000
MC68EC000 economical high-performance embedded controller designed suit needs cost-sensitive embedded-controller market. HCMOS MC68EC000 internal 32-bit architecture that supported statically selectable 16-bit data bus. This architecture provides fast efficient processing device that satisfy requirements sophisticated applications based high-level languages. MC68EC000 fully object-code compatible with MC68000. migrate code written MC68EC000 without modification member M68000 Family. MC68EC000 brings performance level M68000 Family cost levels previously associated with 8-bit microprocessors. MC68EC000 benefits from rich M68000 instruction related high code density with memory bandwidth requirements.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
MC68SEC000
MC68SEC000 cost-effective static embedded processor engineered low-power applications. addition providing substantial cost performance benefits MC68EC000, low-power mode MC68SEC000 provides significant advantages power consumption power management. typical current consumption MC68SEC000 only 0.5µA static standby mode 15.0mA normal 3.3V operation. MC68SEC000 operates either 3.3V 5.0V systems. remarkably power consumption, small footprint packages, static implementation combined MC68SEC000 lowpower applications such portable measuring equipment, electronic games, battery-operated hand-held consumer products. HCMOS MC68SEC000's static architecture direct replacement MC68EC000, which offers lowest cost entry point 32-bit processing. internal 32-bit architecture provides fast efficient processing that satisfies requirements sophisticated applications based high-level languages. existing third-party developer tools widely available MC68EC000 will directly support MC68SEC000. find detailed descriptions these tools High Performance Embedded Systems Source Catalog.
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
SIGNAL DESCRIPTION
Change Figure Page 3-2.
A23-A0
ADDRESS
D15-D0
DATA
PROCESSOR STATUS
DTACK MC68SEC000 ARBITRATION CONTROL ASYNCHRONOUS CONTROL
BERR SYSTEM CONTROL RESET HALT MODE
IPL0 IPL1 IPL2 AVEC INTERRUPT CONTROL
Figure Input Output Signals (MC68EC000 MC68SEC000)
Data (D15-D0)
Section page 3-4, replace "The MC68EC000 MC68HC001 D7-D0 8-bit mode, D15D8 undefined." with "Using MC68HC001, MC68EC000, MC68SEC000 mode pin, statically select either 16-bit modes data transfer. MC68EC000, MC68SEC000, MC68HC001 D7-D0 8-bit mode. D15-D8 undefined."
Arbitration Control
Section page 3-5, sentence 48-pin version MC68008 MC68EC000, available grant acknowledge signal; this microprocessor uses two-wire arbitration scheme." should read 64-pin MC68EC000 MC68SEC000, available grant acknowledge signal. These microprocessors two-wire arbitration scheme."
System Control
Mode subsection heading Section page should read ``Mode (MODE) (MC68HC001/ 68EC000/68SEC000).''
MC68SEC000 Low-Power Mode
following Sections Operation. MC68SEC000 been redesigned provide fully static- low-power operation. This section describes recommended method placing MC68SEC000 into low-power mode reduce M68000 USER'S MANUAL ADDENDUM MOTOROLA
power consumption quiescent value1 while maintaining internal state processor. low-power mode described below will routinely tested part MC68SEC000 test vectors provided Motorola. successfully enter low-power mode, MC68SEC000 must first supervisor mode. recommended method entering low-power mode TRAP instruction, which causes processor begin exception processing, thus entering supervisor mode. External circuitry should accomplish following steps during trap routine: Externally detect write low-power address. select this address which address Mbyte addressing range MC68SEC000. write low-power address detected polling A23-A0, R/W, FC2-FC0. When low-power address detected, logic low, function codes have five (101) their output, processor writing low-power address supervisor mode user-designed circuitry should assert ADDRESS_MATCH signal shown Figure Figure
ADDRESS_MATCH
CPU_CLK
RESTART RESET SYSTEM_CLK
Figure MC68SEC000 Low-Power Circuitry 16-Bit Data
ADDRESS_MATCH
CPU_CLK
RESTART RESET
SYSTEM_CLK
Figure MC68SEC000 Low-Power Circuitry 8-Bit Data Execute STOP instruction. external circuitry shown Figure Figure will count number cycles starting with write low-power address will stop processor clock first falling edge system clock after cycle that reads immediate data STOP instruction. Figure more flip-flop than Figure because MC68SEC000
preliminary specification MC68SEC000's current drain while low-power mode 3.3V operation 5.0V operation.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
8-bit mode requires cycles fetch immediate data STOP instruction. After processor clock disabled, often necessary disable clock other sections your circuit. This done, careful that runt clocks spurious glitches presented MC68SEC000. timing diagram shown Figure
CPU_CLK
DTACK Write Low-Power Address Fetch Immediate Data STOP Instruction Stop
Figure MC68SEC000 Clock Stop Timing 16-Bit Data
Note: While MC68SEC000 low-power mode, inputs must driven VSS, have pull-up pull-down resistor.
This step optional depending whether your applications require MC68SEC000 signals with three-state capability placed into high-impedance state. place MC68SEC000 into three-state condition, proper method arbitrating described Arbitration M68000 User's Manual, should completed during fetch status register data STOP instruction. timing diagram with arbitration sequence shown Figure
CPU_CLK
DTACK
Write Low-Power Address Fetch Immediate Data STOP Instruction
Stop
Figure MC68SEC000 Clock Stop Timing with Arbitration 16-Bit Data
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
After previous steps completed, MC68SEC000 will remain low-power mode until recognizes appropriate interrupt External logic will also have poll IPLB2-IPLB0 detect proper interrupt. When correct interrupt level received, following steps will bring processor low-power mode: Restart system clock stopped. Wait system clock become stable. Assert RESTART signal. This will cause processor's clock start next falling edge system clock. Figure shows timing bringing processor low-power mode. Both RESTART RESET signals subject asynchronous setup time specified Electrical Characteristics section this addendum. WARNING system clock must stable before RESTART signal asserted prevent glitches clock. unstable clock cause unpredictable results MC68SEC000.
CPU_CLK
RESTART
Figure MC68SEC000 Clock Start Timing MC68SEC000 placed three-state condition, signal must negated before processor begin executing instructions.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
example trap routine follows: TRAP_x MOVE.B #0,$low_power_address STOP #$2000 Write that causes ADDRESS_MATCH assert STOP instruction with desired interrupt mask Return from exception
first instruction (MOVE.B #0,$low_power_address) writes byte low-power address that will cause external circuitry begin sequence that will stop processor's clock. second instruction (STOP #$2000) loads with immediate data. This lets interrupt that will cause processor come low-power mode. final instruction (RTE) tells processor return from exception resume normal processing.
MC68SEC000 ELECTRICAL SPECIFICATIONS
following table Section 10.1.
MC68SEC000 MAXIMUM RATINGS
RATING Supply Voltage Input Voltage Maximum Operating Temperature Range Commercial Extended Grade Storage Temperature SYMBOL VALUE -0.3 -0.5 UNIT
Tstg
CMOS CONSIDERATIONS
following change should made Section 10.4, CMOS Considerations. "Although MC68HC000 MC68EC000 implemented with input protection diodes, care should exercised ensure that maximum input voltage specification exceeded." should read "Although MC68HC000, MC68EC000, MC68SEC000 implemented with input protection diodes, careful exceed maximum input voltage specification."
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
MC68SEC000 ELECTRICAL SPECIFICATIONS
Replace Figure 10-2 page 10-6 with Figure
DRIVE DRIVE OUTPUTS(1) VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
OUTPUTS(2)
VALID OUTPUT
DRIVE INPUTS(3) DRIVE
VALID INPUT
INPUTS(4)
DRIVE DRIVE
VALID INPUT
SIGNALS(5) NOTES: This output timing applicable parameters specified relative rising edge clock. This output timing applicable parameters specified relative falling edge clock. This input timing applicable parameters specified relative rising edge clock. This input timing applicable parameters specified relative falling edge clock. This timing applicable parameters specified relative assertion/negation another signal. LEGEND: Maximum output delay specification. Minimum output hold time. Minimum input setup time specification. Minimum input hold time specification. Signal valid signal valid specification (maximum minimum). Signal valid signal invalid specification (maximum minimum).
Figure Drive Levels Test Points Specifications applies parts M68000 USER'S MANUAL ADDENDUM MOTOROLA
MC68SEC000 ELECTRICAL SPECIFICATIONS
following table Section 10.13 page 10-23. (VCC ±5%, ±10%,; Vdc;
CHARACTERISTIC Input High Voltage Input Voltage Input Leakage Current BERR, DTACK, CLK, PL2-IPL0, AVEC MODE, HALT, RESET Three-State (Off State) Input Current Output High Voltage Output Voltage (IOL HALT (IOL A23-A0, FC2-FC0 (IOL RESET (IOL D15-D0, LDS, R/W, Current Dissipation* f=10MHz f=16 Capacitance (Vin Frequency MHz)** Load Capacitance HALT Others SYMBOL ITSI 20.0 VCC-0.75 20.0 UNIT
*During normal operation, instantaneous current requirements high 1.5A. Currents listed with loading. **Capacitance periodically sampled rather than 100% tested.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
MC68SEC000 ELECTRICAL SPECIFICATIONS CLOCK TIMING (See Figure
following table Figure Section 10.9 page 10-9.
10MHz 10.0 16MHz 16.7 20MHz 20.0 UNIT
NUM.
CHARACTERISTIC Frequency Operation Cycle time Clock Pulse Width Clock Rise Fall Times
SYMBOL tcyc
Applies 3.3V
NOTE: Timing measurements referenced from voltage high voltage unless otherwise noted. voltage swing through this range should start outside pass through range such that rise fall will linear between
Figure MC68SEC000 Clock Input Timing Diagram
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
MC68SEC000 ELECTRICAL SPECIFICATIONS READ WRITE CYCLES
following table Figures Section 10.16. Applies 3.3V (GND Figures
10MHz 16MHz 20MHz
CHARACTERISTIC Clock Address Valid Clock High Valid Clock High Address, Data High Impedance (Maximum) (Write) Clock High Address, Invalid (Minimum) Clock High LDS, Asserted
UNIT
Address Valid LDS, Asserted (Read)/ Asserted (Write) 11A2 Valid LDS, Asserted (Read)/ Asserted (Write) Clock LDS, Negated
LDS, Negated Address, Invalid (and LDS, Read) Width Asserted
14A2 LDS, Width Asserted (Write) LDS, Width Negated
Clock High Control High Impedance LDS, Negated Invalid Clock High High (Read) Clock High (Write) Asserted (Write) Address Valid (Write) Valid (Write) Asserted (Write) Clock Data-Out Valid (Write) LDS, Negated Data-Out Invalid (Write) Data-Out Valid LDS, Asserted (Write) Data-In Valid Clock (Setup Time Read) LDS, Negated DTACK Negated (Asynchronous Hold) Clock High DTACK Negated
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
ELECTRICAL SPECIFICATIONS READ WRITE CYCLES (Continued)
10MHz 16MHz 20MHz
CHARACTERISTIC
UNIT Clks Clks Clks Clks Clks Clks
LDS, Negated Data-In Invalid (Hold Time Read) LDS, Negated Data-In High Impedance (Read) LDS, Negated BERR Negated DTACK Asserted Data-In Valid (Setup Time Read) HALT RESET Input Transition Time Clock High Asserted Clock High Negated Asserted Asserted Negated Negated 482,3
Asserted Control, Address, Data High Impedance Negated) Width Negated LDS, Negated AVEC Negated Asynchronous Input Setup Time BERR Asserted DTACK Asserted Data-In Hold from Clock High Data-Out Hold from Clock High (Write) Asserted Data Impedance Change (Write) HALT, RESET Pulse Width Negated LDS, UDS, Driven Negated Driven
Applies 3.3V
NOTES: loading capacitance less than equal subtract from value given maximum columns. Actual value depends clock period. satisfied both DTACK BERR, ignored. absence DTACK, BERR asynchronous input using asynchronous input setup time (#47). power-up, MC68SEC000 must held reset state allow stabilization on-chip circuitry. After system powered refers minimum pulse width required reset controller. asynchronous input setup time (#47) requirement satisfied DTACK, DTACK asserted data setup time (#31) requirement ignored. data must only satisfy data-in clock setup time (#27) following clock cycle. When equally loaded (±20%), subtract from values given these columns. minimum value must guarantee proper operation. maximum value exceeded, reasserted.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
FC2-FC0 A23-A0 DTACK DATA BERR (NOTE HALT RESET ASYNCHRONOUS INPUTS (NOTE
NOTES: Setup time asynchronous inputs IPL2-IPL0 AVEC (#47) guarantees their recognition next falling edge clock. need fall this time only insure being recognized cycle. Timing measurements referenced from voltage high voltage unless otherwise noted. voltage swing through this range should start outside pass through range such that rise fall linear between
Figure MC68SEC000 Read Cycle Timing Diagram M68000 USER'S MANUAL ADDENDUM MOTOROLA
FC2-FC0 A23-A0 DTACK DATA BERR (NOTE HALT RESET ASYNCHRONOUS INPUTS (NOTE
NOTES: Timing measurements referenced from voltage high voltage unless otherwise noted. voltage swing through this range should start outside pass through range such that rise fall linear between Because loading variations, valid after even though both initiated rising edge (specification #20A).
Figure MC68SEC000 Write Cycle Timing Diagram
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
MC68SEC000 ELECTRICAL SPECIFICATIONS ARBITRATION
following table Figure Section 10.17. (GND Vdc; refer Figure
10MHz 16MHz 20MHz
58A1
CHARACTERISTICp Clock High Address, Data High Impedance (Maximum) Clock High Control High Impedance Clock High Asserted Clock High Negated Asserted Asserted Negated Negated Asserted Control, Address, Data High Impedance Negated) Width Negated Asynchronous Input Setup Time Negated LDS, UDS, Driven Negated Driven
UNIT Clks Clks Clks Clks Clks
Applies 3.3V
minimum value must guarantee proper operation. maximum value exceeded, reasserted.
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
STROBES
NOTE: Setup time clock (#47) asynchronous inputs BERR, DTACK, IPL2-IPL0, guarantees their recognition next falling edge clock.
Figure Arbitration Timing
LDS/UDS FC2-FC0
A19-A0
D7-D0
NOTE: Waveform measurements inputs outputs specified logic high logic
Figure MC68SEC000 Arbitration Timing Diagram
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
FC2-FC0
A23-A0
D15-D0
NOTES: Waveform measurements inputs outputs specified logic high logic This diagram also applies 68EC000.
Figure Arbitration Timing-Idle Case
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
FC2-FC0 A23-A0
D15-D0
NOTE: Waveform measurements inputs outputs specified logic high logic This diagram also applies 68EC000.
Figure Arbitration Timing Active Case
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
FC2-FC0
A23-A0
D15-D0 NOTES: Waveform measurements inputs outputs specified logic high logic This diagram also applies 68EC000.
Figure Arbitration Multiple Request
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
MECHANICAL DATA
ASSIGNMENTS
Figure Section 11.1. following defines assignment package dimensions lead package) lead TQFP package) MC68SEC000. Note that pin-to-pin compatible with MC68EC000.
DTACK MODE HALT RESET AVEC BERR IPL2 IPL1 IPL0
MC68SEC000FU/PB
Figure 64-Lead Quad Flat Pack 64-Lead Thin Quad Flat Pack
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
10.0 PACKAGE DIMENSIONS SUFFIX
This diagram replaces Page 11-16 Lead Quad Flat Pack Case 840B-01
MILLIMETERS 16.95 13.90 16.95 13.90 0.30 0.80 2.15 0.13 2.00 12.00 12.00 2.45 0.23 2.40 0.085 0.005 0.79 17.45 14.10 17.45 14.10 0.45 0.667 0.547 0.667 0.547 0.012
INCHES 0.687 0.555 0.687 0.555 0.018 0.031 0.096 0.009 0.094 0.472 0.472
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
11.0 PACKAGE DIMENSIONS SUFFIX
following Section 11.2. Lead Thin Quad Flat Pack Case 840F-02
MILLIMETERS 12.00 6.00 10.00 5.00 12.00 6.00 10.00 5.00 0.17 0.27 0.50 -1.60 0.09 0.20 1.35 1.45
INCHES 0.472 0.236 0.394 0.197 0.472 0.236 0.394 0.197 0.007 0.020 -0.004 0.053 0.063 0.008 0.057 0.011
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
12.0 PACKAGE/FREQUENCY AVAILABILITY
Replaces Section 11.1 following tables identify packages operating frequencies available MC68HC000, MC68HC001, MC68EC000, MC68SEC000.
MC68SEC000 PACKAGE Quad Flat Pack (FU) FREQUENCY 20MHz 20MHz VOLTAGE
Thin Quad Flat Pack (PB)
MC68HC000 PACKAGE Plastic Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing)** Grid Array, Solder Lead Finish** Grid Array, Gold Lead Finish** Plastic Quad Pack (PLCC) MC68HC001** PACKAGE Plastic Quad Pack (PLCC) Plastic Quad (Gull Wing) Grid Array, Gold Lead Finish
FREQUENCY 8,10,12,16,20 8,10,12,16,20 8,10,12,16,20 8,10,12,16,20 8,10,12,16,20
VOLTAGE VOLTAGE
FREQUENCY 8,10,12,16 8,10,12,16 8,10,12,16 8,10,12,16
MC68EC000 PACKAGE Plastic Quad Pack (PLCC) Plastic Quad Flat Pack
FREQUENCY
VOLTAGE
NOTE recommended designs
M68000 USER'S MANUAL ADDENDUM
MOTOROLA
ORDERING INFORMATION
following Section following tables contains ordering information MC68SEC000. MC68SEC000 Ordering Information
PACKAGE TQFP BODY SIZE 14.0 14.0mm 10.0mm 10.0mm LEAD SPACING 0.8mm 10/16/20 0.5mm 3.3V 5.0V SPEED VOLTAGE SUFFIX TEMPERATURE RANGE +70C -40C +85C +70C -40C +85C
MC68HC000 Ordering Information
PACKAGE PLCC BODY SIZE 81.91mm 20.57mm 25.57mm 25.27mm LEAD SPACING 2.54mm 1.27mm SPEED MHZ) VOLTAGE 5.0V SUFFIX TEMPERATURE RANGE +70C +70C -40C +85C
MC68EC000 Ordering Information
PACKAGE PLCC PQFP BODY SIZE 25.57mm 25.27mm 14.1mm 14.1mm LEAD SPACING 1.27mm 0.8mm SPEED MHZ) 10,12, 10,12, VOLTAGE 5.0V SUFFIX TEMPERATURE RANGE +70C
DOCUMENTATION
Section documents listed following table contain detailed information that pertain MC68SEC000 processor. obtain these documents from Literature Distribution Centers listed last page this document. MC68SEC000 Documentation
MC68SEC000 DOCUMENTATION M68000 Family Programmer's Reference Manual M68000 User's Manual High Performance Embedded Systems Source Catalog`` MC68EC000 Product Brief MC68SEC000 Product Brief DOCUMENT NUMBER M68000PM/AD M68000UM/AD BR729/D MC68EC000/D MC68SEC000/D
MOTOROLA
M68000 USER'S MANUAL ADDENDUM
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. Motorola registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
Literature Distribution Centers: USA/EUROPE: Motorola Literature Distribution; P.O. 20912, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo Japan. ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, King Street, Industrial Estate, N.T., Hong Kong.
SEMICONDUCTOR PRODUCT INFORMATION

Communications Advanced Consumer Technologies Group M68000 A

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