Application Note 384: 2001 Multiply Your Sampling Rate with Time-

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Application Note 384: 2001 Multiply Your Sampling Rate with Time-

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CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING
Application Note 384: 2001
Multiply Your Sampling Rate with Time-Interleaved Data Converters Interleaving multiple analog-to-digital converters (ADCs) usually performed with intent increase converters effective sample rate, especially there only off-the-shelf ADCs available that fulfill desired sample, linearity requirements such applications. However, time-interleaving data converters easy task, because even with perfectly linear components, gain/offset mismatches timing errors cause undesired spurs output spectrum. following article provides valuable insight into theoretical approach time-interleaved analog-to-digital converters kind roadblocks (and compensate them) designer usually encounters when building time-interleaved system.
rapid changes today's data-acquisition systems pushing manufacturers semiconductor data converters provide ever-higher levels resolution, clock speed, dynamic performance. Because these requirements cannot always with single chip, they demand creativity from system designer. Time-interleaving existing group high-speed ADCs multiply sampling speed system, becomes tricky complex chore higher sampling speeds. following discussion lends insight into this technique, covers positive negative aspects such designs, provides valuable theory successful interleaving multiple ADCs high-speed data-acquisition system. What Time Interleaving? very-high-speed applications, time interleaving increases overall sampling speed system operating more data converters parallel. This sounds reasonable straightforward actually requires much more effort than just paralleling ADCs. Before discussing this arrangement detail, compare sampling rate time-interleaved system with that single converter. rule thumb, operating number ADCs parallel increases system's sampling rate approximately factor Thus, sampling (clock) frequency interleaved system that hosts ADCs1 described follows:
simplified block diagram Figure illustrates single-channel, time-interleaved system which ADCs double system's sampling rate. This rate (fSYSTEM_CLK) clock signal twice rate fCLK1 fCLK2. Because fCLK1 delayed with respect fCLK2 period fSYSTEM_CLK, ADCs sample analog input signal alternately, producing
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overall sample rate equal fSYSTEM_CLK. Each converter operates half sampling frequency.
Figure This simplified block diagram depicts two-step, time-interleaved system high-speed data acquisition.
Does Time Interleaving Work? typical time-interleaved system explained analyzing operation N-bit twostep flash converter. ADCs featuring clock speeds greater than several hundred megahertz often have multi-step2 time-interleaved architecture rather than single-step direct-conversion (pure flash) architecture (see appendix discussion flash conversion). increase sampling rate whose comparators already running maximum speed, number upper (coarse) lower (fine) quantizer blocks must extended. This achieved implementing N-bit, coarse time-interleaved, N-bit, fine ADCs (Figure coarse quantizer determines upper bits (MSBs), fine quantizers lower bits (LSBs) digital output.
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Figure Principle time-interleaved two-step flash converter
blocks both connected input terminal during first sampling step, only coarse quantizer samples digitizes that time. second step, information from coarse quantizer used generate reference levels that enable them perform fine quantization. LSBs digitized during time takes sample perform conversion with coarse quantizer, interleaving takes place when sampling second time. When first sampling-and-conversion process been completed, input sampled digitized FQ2. While processing second sample, sampling third time. When second sample quantization finished, third sample then converted FQ1. coarse quantizer always sampling converting, fine quantizers (FQ1 FQ2) sample digitize alternate cycles. Repeating over over again, this procedure roughly doubles overall sampling speed two-step system. What Should Considered When Time Interleaving? Pushing operational limits interleaved ADCs very attractive, various limitations considerations must taken into account before turning this method into successful experiment. Bandwidth Limitations: Applications that call higher sampling speeds usually deal with higher-frequency input tones, data converter with input bandwidth half sampling speed would suitable interleaving. Fortunately, most high-speed data converters include track/hold (T/H) amplifiers whose full-power small-signal bandwidths significantly higher than that called Nyquist (fSAMPLE/2) criteria. Offset Gain Errors: channel-to-channel matching offset gain separate ADCs trimmed, gain offset mismatches between ADCs parameters concern
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time-interleaved system. shows offset other gain error, digitized signal represents only original input signal also undesired error digital domain. offset discrepancy causes signal phase shift digitized signal, gain mismatches show differences signal amplitude. interleaving designs, should therefore choose ADCs with integrated gain offset correction include external circuitry that allows correct these mismatches. Nonlinearities: Integral nonlinearity (INL) described deviation actual transfer function from straight line, either LSBs percent full-scale range (%FSR). errors ±1LSB quite common individual ADCs, interleaving system such errors easily double, causing output-code errors that resemble offset gain problems discussed above. appearance nonlinearity introduces distortion into system, which degrades dynamic parameters such signal-to-noise distortion ratio (SINAD) effective number bits (ENOB). Clock Phase Jitter Noise: signal used system clock should have lowest possible phase noise. Introducing D-type flip-flop divide-by-two configuration reduces otherwise stringent requirement precise duty cycle. should choose clock circuit commensurate with signal source's frequency range, amplitude, slew rate. slew rate digitized signal relaxes jitter requirement clock. this slew rate large, however, clock jitter must minimized. full-scale-amplitude sinusoidal input signal, maximum suggested signal-to-noise ratio (SNR) clock jitter only
Most errors discussed above overcome using calibration procedures time domain, careful circuit design layout, suitable selection data converters, digital post-processing. Unfortunately, this approach complex entails extra cost, lengthy calibration, mathematical analysis. Application evaluating analyzing performance actual circuit, confirm theoretical approach presented here. test setup suggested Figure instance, based MAX1444 evaluation boards3 from Maxim. MAX1444 offers lowestspeed grade (40Msps) available Maxim's 10-bit +3.3V single-supply high-speed dataconverter family. Because highly unlikely that off-the-shelf test boards precisely matched, take care connecting signal sources (clock- analog-input signal generators) boards:
Analog clock inputs must impedance-matched specified evaluation kit. avoid further mismatch, cables from signal sources boards must same length. Termination resistors should matched closely avoid reflections.
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Clock- analog-input signal source generators must phase-locked proper operation.
Figure Possible setup test MAX1444 evaluation kits their suitability time-interleaved systems
Appendix Flash Conversion ADCs based direct-conversion, flash, architectures extremely fast perform their multi-bit conversion directly. Intensive analog design, however, necessary manage large number comparators reference voltages required. pure flash converter with N-bit resolution 2N-1 comparators connected parallel. reference voltages these comparators resistor network spaced 1LSB VFS/2N apart, where represents converter's full-scale input range resolution. change input voltage usually produces change state more than comparator output. These output changes combined encoder-logic unit (2N-1-to-N encoder) that produces parallel N-bit output from converter. Although flash converters fastest types available, their resolution4 usually constrained size, input capacitance, power consumption introduced large number internal high-speed comparators. Additionally, repetitive structure flash converters demands precise matching between parallel comparator sections, because mismatch cause static error (for example, increased input offset voltage).
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Flash ADCs also prone sporadic erratic outputs known "sparkle codes." Sparkle codes have major sources: metastability 2N-1 comparators "thermometer-code bubbles." Mismatched comparator delays turn logical into vice versa), causing appearance "bubbles" otherwise normal thermometer code. Because ADC's encoder unit cannot detect this error, generates out-of-sequence code that appears "sparkle" output. However, most data-converter designs minimize completely eliminate these problems supporting comparator arrays encoding logic with additional latches. Each operates same clock frequency (fCLK1 fCLK2 fCLKN) adjacent neighbors. simplification close-comparison purposes, consider example interleaved two-step architecture. Evaluation boards measure channel-to-channel lot-to-lot mismatches their effect performance time-interleaved system. 1-bit increase resolution requires doubling number comparators. Literature Sources MAX1444 data sheet, Rev. 8/00, Maxim Integrated Products. MAX1448EVKIT data sheet, Rev. 0/00, Maxim Integrated Products. Analog Integrated Circuit Design, Johns Martin, John Wiley Sons Inc., 1997. Integrated Analog-to-Digital Digital-to-Analog Converters, Plasche, Kluwer Academic Publishers, 1994. Mixed-Signal Design Techniques, Engineering Staff Analog Devices Inc., printed Analog Devices, 2000. Pipeline ADCs Come
similar version this article appeared February 2001 issue Sensors magazine.
MORE INFORMATION MAX1444: QuickView Full (PDF) Data Sheet (384k) Free Sample MAX1446: QuickView Full (PDF) Data Sheet (296k) Free Sample MAX1448: QuickView Full (PDF) Data Sheet (368k) Free Sample MAX1449: QuickView Full (PDF) Data Sheet (616k) Free Sample
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Application Note 384: 2001 Multiply Your Sampling Rate with Time-

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