2003 High-Speed Sets Input Common-Mode Range following appli

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2003 High-Speed Sets Input Common-Mode Range following appli

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CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING WIRELESS, CABLE
2003
High-Speed Sets Input Common-Mode Range
following application note discusses common-mode output level digital receiver communications system simply utilizing common-mode output high-speed ADC. circuit features DC-coupled input configuration MAX1196 through quadrature demodulator front-end circuit. Input common-mode voltage range (Vcm) important design communication receivers that include baseband-sampling, high-speed ADCs. It's especially important single-supply, low-voltage circuits with dc-coupled inputs. single-supply circuits, input signal feeding drive amplifier should biased level well within range. This arrangement removes performance hurdle amplifier ADC, because they don't have maintain distortion linearity Differential, dc-coupled connections high-speed typically found radio receivers with direct down-conversion. Such circuits have Zero-IF (ZIF) architecture that features quadrature demodulator dual baseband ADC. circuits popular because they eliminate multiple down-conversions filters. DC-coupled connections desirable architecture several reasons: they accept inphase quadrature baseband data with information bandwidth extending close they eliminate bulky coupling capacitors between down-converter high-speed ADC, they eliminate power-sequencing delays caused coupling capacitor's discharge time. importance apparent when consider following:
With variation supply voltage (VDD), signals sourced quadrature demodulator present wide range common-mode voltages ADC. Input common-mode levels extending beyond ADC's range generate harmonic distortion that reduces dynamic range. proper bias therefore optimizes amplifier linearity, minimizing distortion improving bit-error rate (BER).
Figure helps simplify dc-coupled, differential analog interface between frontend, drive amplifier, ADC. circuit, comprising dual 8-bit 40Msps (U1) quad single-supply wideband amplifiers (U2-U3), accommodates wide range input common-
mode voltages analog interface between quadrature demodulator differential, dccoupled signal source) high-speed ADC. provides sufficient Signal Noise Plus Distortion (SINAD) Spurious-Free Dynamic Range (SFDR) demodulate 3.84MHz wideband QPSK communication link. should select adequate SFDR input common-mode range. draws 90mW from single supply.
Figure This high-speed (U1) uses output precise common-mode level. Simplifying translation U1's common mode output (COM, REFIN (pin 46), REFOUT (pin 45). provides output (VDD/2) that matches input commonmode range despite variations. REFIN REFOUT full-scale range resistor divider R23-R24, thereby optimizing input amplifier SFDR dynamic range. configured dc-coupled differential inputs outputs, with 14dB gain, which provides with full-scale (FS) input 1VP-P. preserve receiver's dynamic range, choose U2/U3 amplifiers that specify SFDR 10dB better than ADC's 48.7dB SINAD. U1's voltage R24:
R24/(R23+R24) REFOUT. (REFOUT 2.048V) voltage (pin equals Vdd/2, 1.5V when This voltage also equals input range Thus, changes with temperature supply-voltage tolerance, track each other ensure proper matching voltage levels. sources 5mA, used needed level other circuit elements system. Because internal buffers powered down during shutdown, this level-setting approach saves more power than does continuously 2-resistor voltage divider. typical application Figure circuit WCDMA receiver, which input signal each channel one-half 3.84Mcps chip rate. benefits follow when signal over-sampled four times chip rate (Fclk 15.36MHz). First, oversampling eases design anti-alias filter pushing image beyond octaves, 13.44MHz 17.28MHz Fa). Second, oversampling yields processing gain 6dB: log(Fs/2BW). UI's digital outputs supplied OVDD +1.8V, which helps minimize power consumption. +1.8V lowers digital signal swings, which reduces power according relation CV2F (once each line 8-bit buss). UI's digital outputs multiplexed, which allows dual 8-bit interface single 8-bit bus. multiplex feature also helps minimize digital count, save board space, reduce digital ASIC costs, improve system reliability. Other options: MAX1185 dual 10-bit ADC, pin-compatible with MAX1196. Both parts packaged 7x7mm 48-pin TQFP package with exposed paddle. MAX1192 ultra-low-power, miniature dual 8-bit that consumes less than 25mW comes 5x5mm, 28-pin Thin package.
More Information MAX1185: QuickView Full (PDF) Data Sheet Free Samples MAX1186: QuickView Full (PDF) Data Sheet Free Samples MAX1196: QuickView Full (PDF) Data Sheet Free Samples

2003 High-Speed Sets Input Common-Mode Range following appli

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