2003 Optimizing Graphics Update Rate MAX4455 on-screen video

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2003 Optimizing Graphics Update Rate MAX4455 on-screen video

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CONVERSION/SAMPLING CIRCUITS VIDEO CIRCUITS
2003
Optimizing Graphics Update Rate MAX4455
on-screen video display system character generator, desirable provide smooth transitions when changing displayed information. Applications which display time date need updated between frames, unambiguous record. MAX4455 arbitrary graphics onscreen display generator capable achieving these goals designers need account transfer large amounts data that occur when programming many pixels. This article offers ways make sure that your MAX4455-based system will have optimum graphics update rate.
Background
digital portion MAX4455-based display system consists microcontroller (host processor), SDRAM memory, MAX4455, which acts interface between host memory. This illustrated Figure
Figure MAX4455 Interface Signals. Graphics data displayed contained SDRAM memory. organization data
eight channels logical blocks 1024 each channel total 2Mbits channel total 16Mbits eight channels. visible pixels display into memory differently NTSC versus video formats. NTSC, bits bits dimension used represent visible video horizontal scan lines bits 1024 other dimension used represent total visible horizontal pixels line. format, bits used represent video horizontal scan lines with same visible horizontal pixels line resolution NTSC. both formats, each pixel 4-bit resolution represent brightness. interface between SDRAM memory host processor MAX4455. Data intended memory first written into MAX4455. MAX4455 turn, writes this data into external SDRAM. display channel enabled (not blanked), MAX4455 reads data from appropriate location external SDRAM, processes data, presents corresponding level OSDFIL associated timing OSDKEY drive control insertion external fast MUX. This memory read sequence operates continuously during active portion video signal. Because MAX4455 synchronizes incoming video, memory read cycles inherently asynchronous with respect host processor clock. Data written read from SDRAM writing address into address registers data into data registers, then writing command register MAX4455 execute write read) (from) memory. power-up MAX4455 automatically writes zero values into addressable locations external memory. interface between host controller MAX4455 parallel consisting data/address lines (AD0-AD7), with individual control lines address/data (ADDR/DATA), read (RD), write (WR), chip select (CS), ready/busy (RDY/BSY).
Optimizing Graphics Update Rate
graphics update rate MAX4455 affected following:
size graphic. microcontroller speed. BLANK control function. Monitoring RDY/BSY control line. auto-increment, multi-write shared memory functions. strategy creating graphic.
Every these issues affects graphics update rate MAX4455 different degrees. They listed roughly order their impact. Table shows different update times different conditions. variables that analyzed spreadsheet are: size graphic, processor speed, blanking, auto-increment. From table fastest update rate achieved with smallest graphic, fastest processor,
blanking auto-increment. Also shown equivalent number video horizontal lines vertical fields each condition. This useful determining visual impact update rate. change that occurs within horizontal lines invisible since this time vertical blanking interval. single graphic change display that occurs less than fields single video frame) normally imperceptible. Another saying this human eyebrain combination cannot typically perceive non-recurring event that shorter that time period video frame.
Larger Image. (PDF, 26KB) times Table calculated with following assumptions. Auto-increment mode channels blanked 2byte status bytes line (QPLH+QPLL+QPHORIZ) bytes four pixels (QPH+QPL+COMMAND) Individual address mode channels blanked 2byte status bytes four pixels (QPLH+QPLL+QPHORIZ) bytes four pixels (QPH+QPL+COMMAND) Note: QPLH, QPLL, QPHORIZ, QPH, QPL, COMMAND internal registers MAX4455 related writing reading from SDRAM. equations, values Table include times checking status RDY/BSY signal, computation time required processor prepare data. time required when channels enabled calculated using above equations then adding active video time each scan line. chart Figure using data from Table graphs time perform update versus
number pixels that need written memory. plotted data individual address mode with channels blanked. three different lines represent three different processor speeds.
Figure MAX4455 Update Time versus Number Pixels (Individual Address Mode with Channels Blanked). will take closer look each issues that affects update rate. Size graphic Obviously, larger graphic contains more pixels, which means that more data must written. simple suggestion make graphic small possible achieve fastest update rate, i.e. smaller font case text display. Increases size graphic causes proportionally larger increase number pixels. example: increase both dimensions given graphic causes increase number pixels. Microcontroller speed speed microcontroller direct effect graphics update rate seen from table important note that critical parameter speed port that communicating with MAX4455 processor clock speed. many processors takes more than clock cycle write read from port. BLANK function
BLANK function, controlled channel status registers, allows processor enable disable output channel basis. When individual channel disabled (blanked) OSDFIL OSDKEY outputs inactive, more importantly, reading data that channel suspended. This frees memory access bandwidth used host processor. BLANK function increase update rate factor about times. tradeoff BLANK function potential have flicker display. This happens when channel blanked long time. blanking time less than single frame noticeable occurs random basis. repetitive blanking noticeable viewed objectionable flicker depending repetition rate blanking. exact blanking rate achieve smooth display without perceptual flicker depends number system related factors with most important being human perception. Each system design should evaluated optimized desired visual performance. Ready/Busy output RDY/BSY output MAX4455 signals processor that MAX4455 ready accept another address data intended SDRAM memory. important restate here that this signal asynchronous with host processor, assertion de-assertion cannot predicted. only reasonable this output host monitor continuously, usually configured processor interrupt. RDY/BSY signal initially asserted power-up even though MAX4455 continuously reading from memory. host writes address data values into QPH, QPL, QPHORIZ, QPLINEH, QPLINEL registers. Once write command register MAX4455 checks availability memory interface. interface available MAX4455 writes values into memory. interface unavailable MAX4455 de-asserts RDY/BSY then waits write next available time slot. Once writes values then asserts RDY/BSY signal. auto-increment function, multi-write function, shared memory function auto-increment function, controlled single channel status register, used when sequential locations written into memory, which represents either horizontal vertical lines display. When VINC channel status set, vertical address automatically incremented after each read write operation. Similarly, when HINC channel status register set; horizontal address automatically incremented next quad-pixel location after each read write operation. this successive data written without having write corresponding addresses, thereby increasing update rate. multi-write function, controlled MWRITE command register, used special case where exact same graphic displayed more channels same location. channels that should receive same data selected setting appropriate bits MWRITE register. With these bit(s) set, MAX4455 automatically writes same data into selected channels' corresponding memory locations with single write command host processor. Using multi-write command will increase update rate compared
writing each channels separately also reduce burden processor. shared memory function, controlled group registers, also used special case where same exact data displayed more than channel. specifying beginning ending lines portion channel that should shared with many three other specified channels number pixels that must updated reduced factor four. Even numbered channels shared with even numbered channels numbered channels shared with numbered channels. limitation this function that whole lines must shared, individual pixels. extremes, possible share information between four unique pairs channels, same information eight channels. Strategy changing graphic Most graphic images have some amount spatial redundancy least recurring pattern. carefully crafting sequence drawing graphic, total amount pixels that must changed time reduced. Take case menu with solid background that occupies entire screen. more efficient fill entire background first taking advantage auto-increment function then individually change pixels related menu items. addition auto-increment, software also take advantage static nature register contents MAX4455. Data written into SDRAM memory first writing address data into register MAX4455. Software routines take advantage fact that data these registers static, that data given register does change until user writes data into that register. data does change series pixels does have written again until change brightness desired. Another improvement made when displaying text strings. Take simple example time stamp. fonts that represent numbers chosen mono-spaced, rather than proportional font, individual character updated without changing entire string text.
Summary
MAX4455 very versatile flexible on-screen display generator. Users avail themselves tips techniques contained this article achieve optimum update rate resulting smooth professional looking graphics.
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2003 Optimizing Graphics Update Rate MAX4455 on-screen video

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