Integrating analog-to-digital converters (ADCs) provide high resolutio

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Integrating analog-to-digital converters (ADCs) provide high resolutio

Datasheet Thumbnail

Top Searches for this datasheet

Understanding Integrating ADCs Integrating analog-to-digital converters (ADCs) provide high resolution analog-to-digital conversions, with good noise rejection. These ADCs ideal digitizing bandwidth signals, used applications such digital multi-meters panel meters. They often include drivers used stand alone without microcontroller host. following article explains integrating ADCs work. Discussions include single-, dual- multi-slope conversions. Also, in-depth analysis integrating architecture will discussed. Finally comparisons against other architectures will understanding selection integrating ADCs.
Integrating analog-to-digital converters (ADCs) provide high resolution provide good line frequency noise rejection. Having started with ubiquitous 7106, these converters have been around quite some time. integrating architecture provides novel straightforward approach converting bandwidth analog signal into digital representation. These type converters often include built-in drivers displays found many portable instrument applications, including digital panel meters digital multi-meters. Single-Slope Architecture simplest form integrating uses single-slope architecture (Figures 1b). Here, unknown input voltage integrated value compared against known reference value. time takes integrator trip comparator proportional unknown voltage (TINT/VIN). this case, known reference voltage must stable accurate guarantee accuracy measurement.
www.maxim-ic.com/an1041
Page
Figure Single-slope architecture
drawback this approach that accuracy also dependent tolerances integrator's values. Thus production environment, slight differences each component's value change conversion result make measurement repeatability quite difficult attain. overcome this sensitivity component values, dual-slope integrating architecture used. Dual-Slope Architecture dual-slope (DS-ADC) integrates unknown input voltage (VIN) fixed amount time (TINT), then "de-integrates" (TDEINT) using known reference voltage (VREF) variable amount time (see Figure
www.maxim-ic.com/an1041
Page
Figure Dual-slope integration
advantage this architecture over single-slope that final conversion result insensitive errors component values. That error introduced component value during integrate cycle will cancelled during de-integrate phase. equation form: TINT VREF TDEINT TDEINT TINT (VIN VREF) From this equation, that de-integrate time proportional ratio VREF. complete block diagram dual-slope converter shown Figure
Figure Dual-slope converter example, obtain 10-bit resolution, would integrate 1024 (210) clock cycles, then deintegrate 1024 clock cycles (giving maximum conversion cycles). more resolution, increase number clock cycles. This tradeoff between conversion time resolution inherent this implementation. possible speed conversion time given resolution with moderate circuit changes. Unfortunately, improvements shift some accuracy matching, external components, charge injection, etc. other words, speed-up techniques have larger error budgets. Even simple converter Figure there many potential error sources consider (power-supply rejection [PSR], common-mode rejection [CMR], finite gain, over-voltage concerns, integrator saturation, comparator speed, comparator oscillation, "rollover", dielectric absorption, capacitor leakage current, parasitic capacitance, charge injection, etc). Multi-Slope Integrating ADCs normal limit resolution dual-slope architecture based speed error comparator (this assumes errors system have been minimized designing
www.maxim-ic.com/an1041
Page
high gain, high buffer, integrator comparator). 20-bit converter (approximately part million) 1MHz clock, conversion time would about seconds. ramp rate seen error comparator about 2V/106 divided microsecond. This about microvolts/microsecond. With such small slew rate, error comparator would allow integrator well beyond trip point considerable amount. This overshoot (measured integrator output) called "residue". This brute force technique likely achieve 20-bit converter. Instead, could convert first most significant bits (one integrate/de-integrate cycle), then amplify residue then deintegrate again, then amplify residue then deintegrate last time. residue correctly amplified (i.e., charge injection other errors small), this technique quite powerful increasing resolution reducing conversion time. Note actual reading (Sum first deintegrate time minus (sum second deintegrate time plus (sum third deintegrate time In-Depth Architecture Analysis Auto-Zero previous analysis, assumed ideal converter. actual practice, circuit will have offset that drifts over time temperature. minimize this affect, dual-slope converters employ auto-zero phase. During autozeroing, offset voltage buffer integrator comparator measured stored external capacitor. Thus, integrate cycle effectively begins with zeroed offset. Line Rejection most attractive attributes DS-ADC rejection unwanted 50/60Hz signals. integrate cycle lasts exactly time frequencies completely rejected (theoretically). 100ms, multiples 10Hz rejected. actual limitation this rejection finite swing integrator (since don't want saturate) inevitable "wobble" 50/60Hz frequency itself. Over long period time, 50/60Hz averaged extremely accurate time bases. Over short time however, jitters Hertz. This will limit actual line rejection about 40-60dB. Error Budget Analysis DS-ADC's have several terms error budget. This primarily high accuracy which they targeted. amplifiers must have high common-mode rejection (CMR), power supply rejection (PSR) high finite gain buffer adequately drive resistive load integrator capacitive load). full-scale integrate current [VIN(max) RINT] typically 20-100 microamps. This value tradeoff between power overcoming effects board leakage current. Some engineers have tried class amplifiers these amps save supply current. However, inevitable crossover distortion must carefully analyzed, easily larger than other errors.
www.maxim-ic.com/an1041
Page
comparator needs respond within fraction clock cycle fairly small signal. signal dependent slew rate during deintegrate VREF (RINT CINT)). resolution goes this signal millivolt/microsecond. Unintentional hysteresis must minimized this causes "rollover". Rollover defined difference between near positive full-scale reading near negative full-scale reading. parameter usually specified data sheet electrical specifications tested simply applying fullscale positive voltage, then applying full-scale negative voltage, then adding results. most useful techniques error reduction accomplished shorting input terminals taking measurement. design uses up/down counters accumulators, then measurement error easily subtracted from input signal (VIN) conversion result. This technique always acceptable doubles conversion time calibration done prior every conversion. However, correct many more errors than just offset error (such delay internal comparator(s), charge injection, etc.). External Components user supply with resistor (for converting input voltage current), integrator capacitor autozero capacitor. Both capacitors needed exceptional (dielectric absorption). model integrator capacitor shown Figure shows capacitor made high value, series R'C' components (caused relaxation dielectric) parallel with main capacitor. These series elements cause capacitor behave "memory". example, suppose capacitor charged 1.000 Volts indefinite time, then shorted time constants (SW1 moved position When switch moved position capacitor "relaxes" voltage other than zero volts "memory" effect. This phenomenon ultimately limits accuracy, resolution step response converter.
Figure Model integrating capacitor
Versus Other Architectures will look integrating versus sigma-delta ADC. flash pipeline architectures will ignored since they rarely ever) compete against slower speed integrating architecture. Versus Successive Approximate Register (SAR)
www.maxim-ic.com/an1041
Page
Both integrating architectures work well with bandwidth signals. much wider bandwidth range, they easily convert signals speeds range, while integrating architecture limited about samples/sec. Both architectures have power consumption. Since ADCs shut down between conversions, effective power consumption similar integrating first order). biggest difference between converters common mode rejection number external components required. Because user sets integration time, unwanted frequencies, such 50Hz 60Hz effectively notched out. does allow this. addition, since integration basically method averaging, integrating typically will have better noise performance. code-edge noise spurious noise that converted will have more adverse affect with than with integrating ADC. integrating easily converts low-level signals. Since integrator ramp value integrating resistor, fairly easy match input signal range ADC. Most SARs expect large signal input. Thus small (i.e., signals, front-end signal conditioning circuitry required. integrating needs more external components than SAR. typically needs couple bypass capacitors. integrating requires good integrating reference capacitors also low-drift integrating resistor. addition, reference voltage often non-standard value (like 100mV 409.6mV) reference voltage divider circuit often used. Versus Sigma-Delta sigma-delta uses oversampling obtain very high resolution. also allows input bandwidths range. Like integrating ADC, this architecture have excellent line rejection. also provides very low-power solution allows level signals converted. Unlike integrating ADC, sigma-delta does require external components. addition, requires trimming calibration digital architecture. oversampling nature fact that sigma delta includes digital filter, anti-aliasing filter often required front end. Sigma-delta converters typically available 16-bit 24-bit resolutions while integrating ADCs target 12bit 16-bit range. straightforward architecture maturity, integrating ADCs fairly inexpensive especially 12-bit level. However, 16-bits, sigma-delta also provides cost solution.
www.maxim-ic.com/an1041
Page
MORE INFORMATION ICL7106: QuickView Full (PDF) Data Sheet (552k) Free Sample ICL7107: QuickView Full (PDF) Data Sheet (552k) Free Sample ICL7109: QuickView Full (PDF) Data Sheet (864k) Free Sample ICL7116: QuickView Full (PDF) Data Sheet (208k) Free Sample ICL7117: QuickView Full (PDF) Data Sheet (208k) Free Sample ICL7126: QuickView Full (PDF) Data Sheet (392k) Free Sample ICL7136: QuickView Full (PDF) Data Sheet (688k) Free Sample ICL7137: QuickView Full (PDF) Data Sheet (176k) Free Sample
www.maxim-ic.com/an1041
Page

Integrating analog-to-digital converters (ADCs) provide high resolutio

Top Searches for this datasheet

Other recent searches