MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7428 NOISE) Al

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MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7428 NOISE) Al

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3D7428
MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7428 NOISE)
All-silicon, low-power CMOS technology TTL/CMOS compatible inputs outputs Vapor phase, wave solderable Auto-insertable (DIP pkg.) Leading- trailing-edge accuracy Programmable serial parallel interface Increment range: 0.25 through 20.0ns Delay tolerance: 0.5% (See Table Supply current: typical Temperature stability: r1.5% (-40C 85C) stability: r0.5% (4.75V 5.25V)
SO/P0
data delay devices, inc.
PACKAGES
3D7428Z-xx SOIC
SO/P0
3D7428-xx
3D7428S-xx
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D7428 device versatile 8-bit programmable monolithic delay line. input (IN) reproduced output (OUT) without inversion, shifted time user selection. Delay values, programmed either serial parallel interface, varied over equal steps according formula: Ti,nom Tinh Tinc where programmed address, Tinc delay increment (equal device dash number), Tinh inherent (address zero) delay. device features both rising- falling-edge accuracy.
DESCRIPTIONS
P0-P7 Signal Input Signal Output Mode Select Address Enable Parallel Data Input Serial Clock Serial Data Input Serial Data Output Volts Ground
all-CMOS 3D7428 integrated circuit been designed reliable, economic alternative hybrid programmable delay lines. offered standard 16-pin auto-insertable surface mount 16-pin SOL. 8-pin SOIC package available applications where parallel interface needed.
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7428-0.25 3D7428-0.5 3D7428-1 3D7428-1.5 3D7428-2 3D7428-2.5 3D7428-4 3D7428-5 3D7428-7.5 3D7428-10 3D7428-15 3D7428-20
DELAYS TOLERANCES
Inherent Delay (ns) 10.5 10.5 10.5 10.5 10.5 10.5 13.0 15.0 20.0 23.5 33.0 42.0 Delay Range (ns) 63.75 127.5 255.0 382.5 510.0 637.5 1020 1275 1912.5 2550 3825 5100 Delay Step (ns) 0.25 0.12 0.50 0.25 1.00 0.50 1.50 0.75 2.00 1.00 2.50 1.25 4.00 2.00 5.00 2.50 7.50 3.75 10.0 5.00 15.0 9.00 20.0 12.0 Rec'd Frequency 6.25 3.12 1.56 1.04
INPUT RESTRICTIONS
Absolute Frequency Rec'd Pulse Width 80.0 160.0 320.0 480.0 640.0 800.0 1280.0 1600.0 2400.0 3200.0 4800.0 6400.0 Absolute Pulse Width 11.0 22.0 33.0 44.0 55.0 88.0 110.0 165.0 220.0 330.0 440.0
NOTES: delay increment between 0.25 shown also available standard. application notes section more details
"2004 Data Delay Devices
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7428
APPLICATION NOTES
GENERAL INFORMATION
8-bit programmable 3D7428 delay line architecture comprised number delay cells connected series with their respective outputs multiplexed onto Delay (OUT) user-selected programming data (the address). Each delay cell produces output replica signal present input, shifted time. change delay from address setting next called increment, LSB. nominally equal device dash number. minimum delay, achieved setting address zero, called inherent delay. best performance, essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred. Also, signal traces should kept short possible. inherent delay error deviation inherent delay from nominal value. limited whichever greater.
DELAY STABILITY
delay CMOS integrated circuits strongly dependent power supply temperature. 3D7428 utilizes novel compensation circuitry minimize delay variations induced fluctuations power supply and/or temperature. With regard stability, delay 3D7428 given address, split into components: inherent delay (T0) relative delay T0). These components exhibit very different stability coefficients, both which must considered very critical applications. thermal coefficient relative delay limited r250 PPM/C, which equivalent variation, over -40C operating range, r1.5% from room-temperature delay settings. This holds dash numbers. thermal coefficient inherent delay nominally +10ps/C dash numbers less than +15ps/C other dash numbers. power supply sensitivity relative delay r0.5% over 4.75V 5.25V operating range, with respect delay settings nominal 5.0V power supply. This holds dash numbers. sensitivity inherent delay nominally -1ps/mV dash numbers.
DELAY ACCURACY
There number ways characterizing delay accuracy programmable line. first differential nonlinearity (DNL), also referred increment error. defined deviation increment given address from nominal value. most dash numbers, within every address (see Table Delay Step). integrated nonlinearity (INL) determined first constructing least-squares best straight line through delay-versus-address data. then deviation given delay from this line. dash numbers, within every address. relative error defined follows: erel Tinc where address, measured delay i'th address, measured inherent delay, Tinc nominal increment. very similar INL, simpler calculate. most dash numbers, relative error less than every address (see Table Delay Range). absolute error defined follows: eabs (Tinh Tinc) where Tinh nominal inherent delay. absolute error limited whichever greater, every address.
INPUT SIGNAL CHARACTERISTICS
frequency and/or pulse width (high low) operation adversely impact specified delay increment accuracy particular device. reasons dependency output delay accuracy input signal characteristics varied complex. Therefore recommended maximum absolute maximum operating input frequency recommended minimum absolute minimum operating pulse width have been specified. OPERATING FREQUENCY absolute maximum operating frequency specification, tabulated Table determines highest frequency delay line input signal that reproduced, shifted time device output, with acceptable duty cycle
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7428
APPLICATION NOTES (CONT'D)
distortion. Exceeding this limit will generally result signal output. recommended maximum operating frequency specification determines highest frequency delay line input signal which output delay accuracy guaranteed. Exceeding this limit (while remaining within absolute limit) cause some delays shift with respect their values frequency. amount delay shift will depend degree which limit exceeded. guarantee possible) Table delay accuracy input frequencies higher than recommended maximum frequency, 3D7428 must tested user operating frequency. this case, facilitate production device identification, part number will include custom reference designator identifying intended frequency operation. programmed delay accuracy device guaranteed, therefore, only user specified input frequency. Small input frequency variation about selected frequency will only marginally impact programmed delay accuracy, all. Contact factory details. OPERATING PULSE WIDTH absolute minimum operating pulse width (high low) specification, tabulated Table determines smallest pulse width delay line input signal that reproduced, shifted time device output, with acceptable pulse width distortion. Exceeding this limit will generally result signal output. recommended minimum operating pulse width (high low) specification determines smallest pulse width delay line input signal which output delay accuracy tabulated Table guaranteed. Exceeding this limit (while remaining within absolute limit) cause some delays shift with respect their values long pulse width. amount delay shift will depend degree which limit exceeded. guarantee Table delay accuracy input pulse width smaller than recommended minimum operating pulse width, 3D7428 must tested user operating pulse width. this case, facilitate production device identification, part number will include custom reference designator identifying intended frequency duty cycle operation. programmed delay accuracy device guaranteed, therefore, only user specified input characteristics. Small input pulse width variation about selected pulse width will only marginally impact programmed delay accuracy, all.
PROGRAMMED DELAY UPDATE
delay line memory device. stores information present input time equal delay setting before presenting output with minimal distortion. 3D7428 8-bit programmable delay line represented serially connected delay elements (individually addressed programming data), each capable storing data time equal device increment (step time). delay line memory property, conjunction with operational requirement "instantaneously" connecting delay element addressed programming data output, inject spurious information onto output data stream. order ensure that spurious outputs occur, essential that input signal idle (held high low) short duration prior updating programmed delay. This duration given maximum programmable delay. Satisfying this requirement allows delay line "clear" itself spurious edges. When address loaded, input signal begin switch (and delay will valid) after time given tPDV tEDV (see section below).
PROGRAMMING INTERFACE
Figure illustrates main functional blocks 3D7428 delay program interface. Since 3D7428 CMOS design, unused input pins must returned well defined logic levels, Ground. TRANSPARENT PARALLEL MODE eight program pins directly control output delay. change more program pins will reflected output delay after time tPDV, shown Figure register required programming data bused.
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7428
APPLICATION NOTES (CONT'D)
LATCHED PARALLEL MODE PULSED) eight program pins loaded falling edge Enable pulse, shown Figure After each change delay value, settling time tEDV required before input accurately delayed. SERIAL MODE While observing data setup (tDSC) data hold (tDHC) requirements, timing data loaded MSB-to-LSB order rising edge clock (SC) while enable (AE) high, shown Figure falling edge enable (AE) activates delay value which reflected output after settling time tEDV. data shifted into serial data input (SI), previous contents 8-bit input register shifted serial output port (SO) MSB-to-LSB order, thus allowing cascading multiple devices connecting serial output (SO) preceding device serial data input (SI) succeeding device, illustrated Figure total number serial data bits cascade configuration must eight times number units, each group eight bits must transmitted MSB-to-LSB order. initiate serial read, enable (AE) driven high. After time tEQV (MSB) valid serial output port (SO). first rising edge serial clock (SC), loaded with value present serial data input (SI), while presented serial output (SO). retrieve remaining bits seven more rising edges must generated serial clock line. read operation destructive. Therefore, desired that original delay setting remain unchanged, read data must written back device(s) before enable (AE) brought low. pin, unused, must allowed float device configured serial programming mode. serial mode only mode available 8-pin version 3D7428.
SIGNAL
PROGRAMMABLE DELAY LINE
SIGNAL
ADDRESS ENABLE SERIAL INPUT SHIFT CLOCK
LATCH
SERIAL OUTPUT
8-BIT INPUT REGISTER
MODE SELECT
PARALLEL INPUTS
Figure1: Functional block diagram
PARALLEL INPUTS P0-P7 DELAY TIME
PREVIOUS
VALUE
tPDX
PREVIOUS
tPDV
VALUE
Figure Non-latched parallel mode (MD=1, AE=1)
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7428
APPLICATION NOTES (CONT'D)
ENABLE (AE)
tDSE
PARALLEL INPUTS P0-P7 DELAY TIME VALUE
tDHE
tEDX
PREVIOUS
tEDV
VALUE
Figure Latched parallel mode (MD=1)
ENABLE (AE)
CLOCK (SC)
tDSC
SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIME
tDHC
tEGV
tCQV
tCQX
tEQZ tEDV
VALUE
tEDX
PREVIOUS VALUE
Figure Serial mode (MD=0)
3D7428
3D7428
3D7428
FROM WRITING DEVICE
NEXT DEVICE
Figure Cascading Multiple Devices
TABLE DELAY PROGRAMMED ADDRESS
PARALLEL SERIAL STEP STEP STEP STEP STEP STEP STEP STEP STEP CHANGE
PROGRAMMED ADDRESS
NOMINAL DELAY (NS) 3D7428 DASH NUMBER -0.25 10.50 10.75 11.00 11.25 11.50 11.75 73.75 74.00 74.25 63.75 -0.5 10.5 11.0 11.5 12.0 12.5 13.0 137.0 137.5 138.0 127.5 10.5 11.5 12.5 13.5 14.5 15.5 263.5 264.5 265.5 255.0 10.5 12.5 14.5 16.5 18.5 20.5 516.5 518.5 520.5 510.0 1280 1285 1290 1275 23.5 33.5 43.5 53.5 63.5 73.5 2553.5 2563.5 2573.5 2550.0 5102 5122 5142 5100
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7428
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -4.0 UNITS NOTES
-35.0 15.0
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/line (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
(-40C 85C, 4.75V 5.25V) PARAMETER Clock Frequency Enable Width Clock Width Data Setup Clock Data Hold from Clock Data Setup Enable Data Hold from Enable Enable Serial Output Valid Enable Serial Output High-Z Clock Serial Output Valid Clock Serial Output Invalid Enable Setup Clock Enable Hold from Clock Parallel Input Valid Delay Valid Parallel Input Change Delay Invalid Enable Delay Valid Enable Delay Invalid Input Pulse Width Input Period Input Output Delay SYMBOL tDSC tDHC tDSE tDHE tEQV tEQZ tCQV tCQX tPDV tPDX tEDV tEDX Period tPLH, tPHL UNITS Total Delay Total Delay NOTES
Table Table Table
NOTES: Refer PROGRAMMED DELAY UPDATE section
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7428
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN 1.25 Total Delay Period: PERIN Total Delay OUTPUT: Rload: Cload: Threshold: 10K: 1.5V (Rising Falling)
Device Under Test
10K:
Digital Scope
470:
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
tFALL
tPHL
tPLH OUTPUT SIGNAL
Figure Timing Diagram
#03003
5/8/2006
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7428 NOISE) Al

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