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FN2815.3 16-Bit Numerically Controlled Oscillator Intersil H
Top Searches for this datasheetHSP45106/883 FN2815.3 16-Bit Numerically Controlled Oscillator Intersil HSP45106/883 high performance 16-bit quadrature Numerically Controlled Oscillator (NCO16). NCO16 simplifies applications requiring frequency phase agility such frequency-hopped modems, modems, spread spectrum communications, precision signal generators. shown Block Diagram, HSP45106/883 divided into Phase/Frequency Control Section (PFCS) Sine/Cosine Section. inputs Phase/Frequency Control Section consist microprocessor interface individual control lines. frequency resolution bits, which provides resolution better than 0.006Hz 25.6MHz. User programmable center frequency offset frequency registers give user capability perform phase coherent switching between sinusoids different frequencies. Further, programmable phase control register allows phase control better than 0.006o. applications requiring level PSK, three discrete inputs provided simplify implementation. output PFCS 32-bit phase argument which input Sine/Cosine Section conversion into sinusoidal amplitude. outputs Sine/Cosine Section 16-bit quadrature signals. spurious free dynamic range this complex vector greater than 90dBc. added flexibility when using NCO16 conjunction with DAC's, choice either parallel serial outputs with either two's complement offset binary encoding provided. addition, synchronization signal available which signals serial word boundaries. Features This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. 25.6MHz Clock Rate 32-Bit Center Offset Frequency Control 16-Bit Phase Control Level Supported Through Three Interface Simultaneous 16-Bit Sine Cosine Outputs Output Two's Complement Offset Binary <0.006Hz Tuning Resolution 25.6MHz Serial Parallel Outputs Spurious Frequency Components -90dBc 16-Bit Microprocessor Compatible Control Interface Applications Direct Digital Synthesis Quadrature Signal Generation Modulation FSK, (BPSK, QPSK, 8PSK) Precision Signal Generation Ordering Information PART NUMBER HSP45106GM-25/883 TEMP. RANGE PACKAGE PKG. G85.A Block Diagram MICROPROCESSOR INTERFACE DISCRETE CONTROL SIGNALS CLOCK SIN/COS ARGUMENT PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION SINE COSINE CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. Rights Reserved HSP45106/883 Absolute Maximum Ratings Supply Voltage +8.0V Input, Output Voltage Applied -0.5V +0.5V Classification Class Thermal Information Thermal Resistance (Typical, Note (oC/W) (oC/W) Package 36.0 Maximum Package Power Dissipation 125oC Package 1.39W Maximum Junction Temperature 175oC Maximum Storage Temperature Range. -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC Operating Conditions Temperature Range. -55oC 125oC Voltage Range +4.5V +5.5V Characteristics Gate Count. 18,750 CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied. NOTE: measured with component mounted evaluation board free air. TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed 100% Tested PARAMETER Logical Input Voltage Logical Zero Input Voltage Output HlGH Voltage SYMBOL VIHC ICCSB ICCOP TEST CONDITIONS 5.5V 4.5V -400µA 4.5V (Note +2.0mA 4.5V (Note 5.5V VOUT 5.5V 5.5V 4.5V 5.5V, (Note 25.6MHz 5.5V (Notes (Note GROUP SUBGROUPS TEMPERATURE +125 +125 +125 +125 +125 +125 +125 +125 +125 +125 +125 UNITS Output Voltage Input Leakage Current Output Leakage Current Clock lnput High Clock Input Standby Power Supply Current Operating Power Supply Current Functional Test NOTES: Interchanging force sense conditions permitted. Operating supply current proportional frequency, typical rating 8mA/MHz. Tested follows: 1MHz, 2.6, 0.4, 1.5V, 1.5V, VIHC 3.4V, VILC 0.4V. Loading specified test load circuit with 40pF. HSP45106/883 TABLE ELECTRICAL PERFORMANCE SPECIFICATIONS (25.6MHz) PARAMETER Period High Period High Setup Time A(2:0), Going High Hold Time A(2:0), from Going High Setup Time C(15:0) Going High Hold Time C(15:0) from Going High Setup Time High High Setup Time MOD(2:0) Going High Hold Time MOD(2:0) from Going High Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC Going High Setup Time ENPOREG, ENOFREG, ENCFREG, ENPHAC, ENTIREG, INHOFR, PMSEL, INITPAC, BINFMT, TEST, PAR/SER, PACI, INITTAC from Going High Output Delay SIN(15:0), COS(15:0), TICO Output Delay DACSTRB Output Enable Time NOTES: Testing: 4.5V 5.5V. Inputs driven 3.0V Logic 0.0V Logic "0". Input output timing measurements made 1.5V both Logic driven 4.0V measured 2.0V. Output load test load circuit with switch closed 40pF. Transition measured ±200mV from steady state voltage with loading specified test load circuit 40pF. ENOFRCTL, ENCFRACTL, ENTICTL, ENPHREG active, care must taken violate setup hold times these registers when writing data into chip C(15:0) port. SYMBOL tAWS tAWH tCWS tCWH tMCS tMCH tECS Note NOTES GROUP SUBGROUP TEMPERATURE UNITS tECH tDSO Note HSP45106/883 TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS (25MHz) PARAMETER Input Capacitance SYMBOL CONDITIONS Open, 1MHz, measurements referenced device GND. Open, 1MHz, measurements referenced device GND. NOTES TEMPERATURE (oC) UNITS Output Capacitance COUT tOEZ Output Disable Delay Output Rise Time Output Fall Time NOTES: From 0.8V 2.0V From 20.V 0.8V Parameters listed Table controlled design process parameters directly tested. These parameters characterized upon initial design after major process and/or design changes. Loading specified test load circuit with switch closed 40pF. TABLE ELECTRICAL TEST REQUIREMENTS CONFORMANCE GROUPS Initial Test Interim Test Final Test Group Groups METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS HSP45106/883 Burn-In Circuit HSP45106/833 (PGA) INIPAC ENTI ENCF SIN0 PAR/ PACI INITT ENPO TEST INHOF ENOF COS6 COS7 SIN1 SIN3 SIN2 SIN5 SIN6 SIN4 SIN8 SIN7 SIN9 SIN10 SIN11 SIN12 SIN13 SIN15 SIN14 COS2 COS4 COS8 STRB COSO COS1 COS3 COS5 "A1" COS11 COS10 COS9 COS12 MOD2 MOD0 MOD1 PMSEL INDEX COS15 COS13 TICO COS14 NOTES: NAME PMSEL COS14 TICO BURN-IN SIGNAL NAME MOD1 COS13 COS15 MOD0 MOD2 COS12 TEST COS9 COS10 COS11 COS8 COS7 BURN-IN SIGNAL NAME ENOFREG ENPOREG ENCFREQ COS5 COS4 COS6 INHOFR INITTAC ENTIREG COS3 COS2 PACI ENPHAC COS1 SIN11 SIN7 SIN6 PAR/SER INITPAC COS0 BURN-IN SIGNAL NAME SIN15 SIN10 SIN8 SIN2 BINFMT DACSTRB SIN14 SIN13 SIN12 SIN9 SIN4 SIN5 SIN3 SIN1 SIN0 BURN-IN SIGNAL (2.7V ±10%) used outputs only. (±20%) resistor connected pins except GND. 5.5V ±0.5V. 0.1µF (min) capacitor between position. 100kHz ±10%, F0/2, F1/2., F10/2, Duty Cycle. Input voltage limits: 0.8V max., 4.5V ±10%. HSP45106/883 Characteristics DIMENSIONS: mils mils ±1mils METALLIZATION: Type: Si-Al, Si-Al-Cu Thickness: GLASSIVATION: Type: Nitrox Thickness: WORST CASE CURRENT DENSITY: A/cm Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. 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