Evaluating ColdFire® Target System: MCF5307 MC68EC020 Gateway Ref
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Order Number: AN2008/D Rev. 7/2000
Evaluating ColdFire® Target System:
MCF5307 MC68EC020 Gateway Reference Design
Nigel Dick Motorola Ltd., East Kilbride, Scotland Motorola's family been market leader embedded applications many years. result this, there great wealth experience industry surrounding architecture. highly competitive nature embedded systems market compels designers strive find best trade-off between price performance microprocessors. Methods used microprocessor manufacturers improve processor performance such pipelining increasing on-chip cache very expensive with respect silicon area. overcome this problem minimize cost with maximum performance, necessary implement changes architecture. This result difficulties when designer wishes upgrade their design. There implications hardware software compatibility which would present architecture remained unmodified. ColdFire architecture been designed specifically high performance, cost sensitive embedded applications. doing this, architecture analyzed that embedded systems designers architecture examined. result, features architecture used less frequently embedded system design were removed. ColdFire architectures' foundation Motorola's 68000 architecture allows designers take advantage established tool support, code evolution, engineering expertise. uses variable length RISC instruction optimize both code density allow instruction issued every clock cycle where possible. ColdFire instruction subset instruction set, that compatible both assembler binary levels. programming model also identical 68K, with exception that simplified stack pointer exception stack frame.
This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice. Motorola, Inc., 2000. rights reserved.
Gateway reference design which will discussed integrated circuit board which will bridge existing MC68EC020 system ColdFire MCF5307 microprocessor, evaluate ease upgrading higher performance architecture. used evaluate system enhancements such on-chip instruction and/or data cache bursting external memory. also used port customer's system code ColdFire architecture situ opposed traditional method initially porting code evaluation platform. This paper intended describe operation Gateway board. using Gateway solution, processor initialization code configured internal register ColdFire processor. Although ColdFire architecture derived from 680x0 family with simplified instructions addressing modes, assembler programs while straightforward port ColdFire require some modification before they will run. help customers with this translation process, Motorola funded development assembler code converter PortASM/68K, written MicroAPL Ltd. U.K. (Consult more information.) This utility will either PC's (under DOS, Windows 3.x, Windows95/98 Windows Workstations (under SunOS Solaris) available free charge download from web. This converter only converts assembler code ColdFire assembler analyses original code operates allowing analyzer produce optimized ColdFire code passes, rather than just straight translation.
MCF5307 MC68EC020 Gateway Reference Design
Design Considerations
Design Considerations
MC68EC020 low-cost, (high performance) embedded derivative popular 32-bit MC68020 Microprocessor. major differences between MC68020 MC68EC020 that MC68EC020 24-bit address does implement /ECS, /OCS, /DBEN, /IPEND /BGACK signals.
Sequencer Control Control store Stage Instruction Pipe Stage Stage
Cache holding register (CAHR)
Control logic Instruction address Address 24-bit Address pads Program counter section Address Write pending buffer Prefetch pending buffer Address section Data section Size Multiplexer Instruction cache Execution Unit Data pads
Internal data 32-bit
Data
Misalignment multiplexer
Microbus control logic Controller control signals
Figure MC68EC020 Block Diagram
MCF5307 MC68EC020 Gateway Reference Design
Design Considerations
Clock input JTAG interface
Clock multiplied JTAG System controller
DRAM controller Chip selects Interrupt controller External interface
DRAM control Chip selects Interrupt support External
Master arbitration
module byte SRAM cache interface Debug module ColdFire core module Dual UART Timers
interface Serial interface Timer support Parallel interface M-Bus interface
MCF5307
General purpose M-Bus module
Figure MCF5307 Block Diagram
feature required debugging microprocessor system memory. This allows designer download code. ColdFire MCF5307 microprocessor 4Kbytes on-chip Static (SRAM) DRAM control module built onto silicon from which both asynchronous synchronous external memory "gluelessly" interfaced. DRAM controller offers designer clear cost saving reducing component count system. This module also provides flexibility interface multiple memory configurations. addition requiring DRAM SRAM memory debugging software, many designers require non-volatile storage form FLASH memory store boot code data that been collected system. Data code stored FLASH memory accessed, modified erased port. With this mind, MC68EC020 MCF5307 Gateway Reference Module designed with Mbytes Fast Static RAM, Mbyte FLASH additional RS-232 compatible serial communications port. consists printed circuit boards, interconnect board that connects target which derives 3.3V supply needed MCF5307 from target hardware supply microprocessor memory board which contains ColdFire processor. This second board provides additional hardware performing many tasks such control processing from external hardware, pulling active control signals high logic level decoupling power supplies suppress noise. Given modules incorporated into design, reference module considered self-contained ColdFire sub-system
MCF5307 MC68EC020 Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
This section includes following subsections: MCF5307 CPU, Clock, RESET Circuit RS232 Communications Port MC5307FT Microprocessor Connection FSRAM Flash Memory Connections Initialization MCF5307 Reset Test Points, Decoupling Pull-Up Resistors
1.2.1 MCF5307 CPU, Clock, RESET Circuit
Figure shows main circuit diagram ColdFire MCF5307 including selectable clock, RESET circuitry connectivity.
1.2.1.1 Clock Circuit
clock supply MCF5307 Microprocessor selectable jumper JP1. Clock source either from local 45MHz crystal oscillator (SMT), (jumper position externally from CLKIN input pin, (jumper position target hardware. crystal oscillator uses same 3.3V supply MCF5307 microprocessor.
1.2.1.2 Reset Circuit
main reset signal, RSTI, controlled MAX708TCSA chip illustrated Figure MAX708TCSA chip provides circuit with guaranteed reset output during power down brownout conditions. (Brownout term given abnormally power supply voltages). reset threshold voltage this device 3.08V additional 1.25V threshold detection circuit included on-chip indicate power fail battery conditions. added advantage using this type device that does require additional components. MAX708TCSA chip powered 3.3V supply activated bridging RESET jumper JP2. RESET line pulled logic high level 4.7K-ohm resistor (R2). attached reset line indicate that reset taken place either through MAX708TCSA chip from port. Switch connected MAX708TCSA chip, provides user with ability manually reset system required.
1.2.1.3 Background Debug Mode (BDM) Connector
allow full debug capabilities MCF5307 microprocessor, 26-way connector been included Gateway Reference Board. connector, Reset, connected 3.3V through 4.7K resistor prevent false switching.
1.2.1.4 Pull-up Resistors, LED's Miscellaneous Connections
green surface mount LED, which connected 3.3V supply current limited 470-ohm resistor, indicates power supply onto Gateway board. LED, indicates that RESET been asserted either MAX708TCSA external device through target connector.
MCF5307 MC68EC020 Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
test mode signals MCF5307 microprocessor determine whether device operates JTAG test mode. MTMOD0 signal that determines this selection MTMOD[3:1] signals should tied ground. ensure that MCF5307 microprocessor assumes control bus, grant (/BG) signal must tied ground through 4.7K resistor. Similarly, test clock signal must tied ground (again through 4.7K resistor) when being used. MCF5307 microprocessor should powered 3.3V supply connected appropriate ground connections indicated circuit diagram.
1.2.2 RS232 Communications Port
schematic shows standard tolerant RS232 communications port created using Motorola MC145407DW driver receiver. MC145407DW combines three drivers receivers meet electrical standards EIA-232-E CCITT V28. drivers MC145407 designed guarantee charge pump output while operating from single power supply. RS232 logic levels obtained internal voltage doubler inverter arrangement that converts RS232 control signals into Gateway board through connector CON8 that powered supply. Capacitors C20-23 provide high /low frequency bypass minimize noise system. Capacitors charge pump capacitors that determine slew rate charge pump therefore governing overall operation MC145407DW chip. Setting value 10uF, gives same slew rate output characteristics MC145407DW chip that given electrical specification section data sheet. Note, correct polarity electrolytic capacitors must observed when constructing gateway board! (Consult more information this device.)
1.2.3 MC5307FT Microprocessor Connection
diagram Appendix shows jumper connections MC5307 Microprocessor. Four 50-way connectors used breakout signals from chip into dual line connectors (DIL). Connectors J3-2, J4-2, J5-2 J6-2 allow MC68EC020 target hardware control signals connect directly control signals MCF5307 Gateway Reference board. This diagram also shows jumper JP16 which used connect reset target device ColdFire reset.
1.2.4 FSRAM Flash Memory Connections
schematic shown Appendix illustrates connections on-board FLASH (MBM29F800A3BT80) 128Kx8 Asynchronous Fast SRAM (MCM6926AWJ8). This configuration provides Mbyte Flash MBytes FSRAM memory. MCM6926A 1,048,576 static random access memory organized 131,072 words bits. static design this part eliminates need external clocks timing strobes only requires three control signals operation output enable (/G), chip enable (/E) write enable (/W). Chip select (/CS5) controls chip selects FSRAM chips output enable signal (/OE) MCF5307 microprocessor controls output enable memory chips both FLASH FSRAM. Write enable FSRAM chips independently controlled through (Byte) Write Enable signals (/WE[0:3]) directly from MCF5307 microprocessor. Chip select chosen FSRAM allow lower order chip selects used interfacing devices target hardware.
MCF5307 MC68EC020 Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
Pull-up resistors R5-R8 (10K) required stable FLASH operation these connected /BYTE, RY/BY, active pins chip. pull-up resistor attached /BYTE FLASH device sets mode 16-bit data mode. this pulled mode 8-bit. Chip select used control access FLASH memory block selectable jumper (See Appendix This jumper included design allow /CS0 used boot from target hardware, rather than local FLASH ROM. ready busy line FLASH memory block sensed directly using Address MCF5307 Microprocessor. configuring appropriate Assignment Register MCF5307 ColdFire, Address general purpose I/O.] Both memory chips (FLASH FSRAM) connected MCF5307 data (D0.31) address (A0.27).
1.2.5 Initialization MCF5307 Reset
When Gateway board first powered MCF5307 microprocessor must configured into known initial state. This achieved using eight jumpers (JP5-JP12) MC74LCX541T low-voltage CMOS Octal Buffer. Jumpers used divide ratio BCLK/PSTCLK that sampled during reset. similar fashion, jumpers used frequency range CLKIN therefore range which MCF5307 will operating. Jumper controls configuration assignment register. system configured wide parallel port PP[15:0] this logic zero (jumper position). However, this logic (jumper position alternative multiplexed functions setup when corresponding assignment register one. (PP[15:8] general purpose multiplexed with A[31:24]. PP[7:0] multiplexed with /DREQ[1:0], /TIP, TM[2:0] TT[1:0] signals). Jumpers JP10 JP11 used define size /CS0 port immediately after reset. Jumper JP12 sets automatic acknowledge chip select zero. PVDD, power supply on-chip PLL, supplied main 3.3V power supply. This power source smoothed 470nH inductor high frequency noise removed using bypass capacitors C17. reset, inputs from different jumper switches (JP5-JP8) latched directly onto signals D0-D7 MCF5307 microprocessor's data bus. high impedance inputs MC74LCX541 significantly reduce current loading input drivers allow inputs safely driven from devices. This makes MC74LCX541 particularly suitable memory address driving level oriented transceiver applications.
1.2.5.1 Control Equations-U10
arbiter required arbitrate between buses MC68EC020 target hardware MCF5307 microprocessor. performs this function. logic equations assume that system held RESET. direct memory acknowledge (DMACK) signal generated from transfer type pins (TT1 TT0) MCF5307. signal asserted signal asserted, cycle encoded emulator access DMACK signal becomes asserted. transfer type pins (TT[1:0]) transfer modifier pins (TM[2:0]) both used determine type access additionally address space that accessed. both transfer type pins asserted then access MC68EC020 normal mode access. transfers made space then transfer modifier pins asserted. Hence, both transfer type modifier pins asserted, cycles MC68EC020 must access normal space.
MCF5307 MC68EC020 Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
Alternatively, both transfer type modifier pins de-asserted, transfer modifier pins carry interrupt level being acknowledged. Thus this case, interrupt level would acknowledged. granted target hardware when request from target asserted already granted MCF5307 microprocessor. Similarly, granted MCF5307 microprocessor soon possible after receipt valid request signal. will granted MCF5307 when either MCF5307 requested when target hardware requesting being driven. Appendix illustrates relevant control equations simulation setups coding U10.
1.2.5.2 Control Equations-U11
transfer acknowledge sizing control signals controlled U11. MC68EC020 dynamically interpret port size addressed device during each cycle. Unfortunately, MCF5307 Microprocessor cannot perform this type dynamic sizing. When MCF5307 master, however, size pins (SIZ[1:0]) indicate requested transfer size cycle encoding. When MC68EC020 master size pins will inputs. SIZ0 MCF5307 Microprocessor asserted when DSACK0 signal asserted DSACK1 signal asserted. Similarly, SIZ1 signal asserted when DSACK1 signal asserted DSACK0 signal asserted. (The DASCK0/1 signals MC68EC020 logically opposite SIZ0/1 signals MCF5307). output pins connected hardware test pads. Example logic coding output been given Appendix example code asserts signal "SPARE" (Pin when both DSACK signals asserted indicating that Data port size encoded bits. (The could coded similar fashion other user specific functions.) target device driving asserts DSACK signals then transfer acknowledge signal MCF5307 asserted. Note that this control line requires pull-up resistance 1Kohms ensure fast negation this signal, which turn prevents false cycles bus. SIZ0 SIZ1 signals generated tied high internally prevent glitches during reset. signal default data size bits reset using "SPARE" control line DSACK0 signals. Appendix illustrates corresponding control equations generating sizing test control signals.
1.2.6 Test Points, Decoupling Pull-Up Resistors
schematic shown Appendix detail signals that accessed through test points positioned throughout board debugging. basic signals that accessible /TS, /AS, /CS5, /TA, R/W, (3.3V). Also listed this schematic page signals that must pulled-up high logic level avoid false signaling. Each signal that requires pull-up tied 3.3V using 4.7Kohm resistor. Jumper schematic selects debug operation JTAG operation test module MCF5307 microprocessor. jumper placed position operation will selected. Similarly, jumper placed position Gateway board will select JTAG operation. This signal then into MCF5307 microprocessor test mode MTMOD0. schematic also shows decoupling capacitors that need connected power ground pins on-board chips minimise effects noise system. Note both 0.1uF capacitors inhibit both high frequency noise system.
MCF5307 MC68EC020 Gateway Reference Design
MC68EC020 PGA-MCF5307FT, Gateway Reference Design
Jumper used select either on-module FLASH chip select off-module user chip select. jumper position off-module user chip select activated local FLASH chip select jumper position purposes debugging, three surface mount LED's (D3, connected onto spare MCF5307 ColdFire address lines A[29:31] resistors (R11-13). detailed previously, these spare address lines configured general pins setting appropriate values assignment register MCF5307 microprocessor.
MCF5307 MC68EC020 Gateway Reference Design
PALASM Control Equations
Appendix PALASM Control Equations
TITLE PATTERN REVISION DATE AUTHOR COMPANY U10_BUS_ARBITRATION P00001 March 1998 Pete Highton Motorola 1998
CHIP
PALCE16V8 /RESET /TT0 /TT1 /BR_TGT /TM0 /TM1 /BG_TGT /TM2 /DMACK COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL
COMBINATORIAL COMBINATORIAL COMBINATORIAL; COMBINATORIAL; COMBINATORIAL COMBINATORIAL; COMBINATORIAL; COMBINATORIAL;
EQUATIONS
/BR_TGT)) /RESET BG_TGT BR_TGT /RESET grant target /TT0 /TT1 /TM0 /TM1 /TM2 /RESET; FC1=1 ;interrupt level ack. DMACK /TT0 /RESET More info. settings! Delay write cycle clock.
MCF5307 MC68EC020 Gateway Reference Design
PALASM Control Equations
Appendix PALASM Control Equations
TITLE PATTERN REVISION DATE AUTHOR COMPANY CHIP U11_TA_BUS_SIZING P00002 March 1998 Pete Highton Motorola 1998 PALCE16V8 /DSACK0 /DSACK1 /CS0 /CS1 /CS2 /CS3 /CS4 /CS5 /CS6 /CS7 SPARE1 SIZ1 SIZ0 COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL Input Input Input Input Input Input Input Input Input
COMBINATORIAL Input COMBINATORIAL Input
COMBINATORIAL COMBINATORIAL COMBINATORIAL COMBINATORIAL
Output Output Output Input
EQUATIONS SIZ1 DSACK1 /DSACK0 SIZ1.TRST SIZ0 /DSACK1 DSACK0 SIZ0.TRST (DSACK0 DSACK1) SPARE1 (DSACK0 DSACK1) TA.TRST SPARE1 generated either DSACKx signal asserts while master. Asserted byte transfer master. Asserted word transfer master.
MCF5307 MC68EC020 Gateway Reference Design
Appendix C-Schematics
Simulation Segment -SIMULATION
TRACE_ON DSACK0 DSACK1
SETF
/DSACK0 /DSACK1
CLOCKF CLOCKF
SETF DSACK0 CLOCKF CLOCKF
SETF
/DSACK0 /DSACK1
CLOCKF CLOCKF SETF DSACK1 CLOCKF CLOCKF SETF /DSACK0 /DSACK1
CLOCKF CLOCKF
TRACE_OFF
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure MCF5307 CPU, RESET Connections
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure RS232 Serial Communications Port
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure FLASH Memory
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure Flash Memory
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure Arbitration Control Signals
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
Figure Decoupling
Appendix C-Schematics
MCF5307 MC68EC020 Gateway Reference Design
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AN2008/D
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