MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444) Fou
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3D7444
MONOLITHIC QUAD 4-BIT PROGRAMMABLE DELAY LINE (SERIES 3D7444)
Four indep't programmable lines single chip All-silicon CMOS technology quiescent current (1mA typical) Leading- trailing-edge accuracy Vapor phase, wave solderable Auto-insertable (DIP pkg.) Increment range: 1.5ns through 25ns Delay tolerance: (See Table Temperature stability: typical (0C-70C) stability: typical Minimum input pulse width: total delay
PACKAGES
DIP-14 3D7444-xx
SOIC-14 3D7444D-xx
mechanical dimensions, click here. package marking details, click here.
FUNCTIONAL DESCRIPTION
3D7444 device small, versatile, quad 4-bit programmable monolithic delay line. Delay values, programmed serial interface, independently varied over equal steps. step size determined device dash number. Each input reproduced corresponding output without inversion, shifted time user selection. each line, delay time given
DESCRIPTIONS
I1-I4 O1-O4 Signal Inputs Signal Outputs Address Latch Serial Clock Serial Data Serial Data 5.0V Ground
where inherent delay, delay address n-th line delay increment (dash number). desired addresses shifted into device inputs, addresses latched using input. serial interface also used enable/disable each delay line. 3D7444 operates volts typical 6ns. 3D7444 CMOS-compatible, capable sourcing sinking loads, features both rising- falling-edge accuracy. device offered standard 14-pin auto-insertable space saving surface mount 14-pin SOIC.
TABLE PART NUMBER SPECIFICATIONS
PART NUMBER
3D7444-1.5 3D7444-2 3D7444-4 3D7444-5 3D7444-8 3D7444-10 3D7444-15 3D7444-20 3D7444-25
DELAYS TOLERANCES (ns)
Delay Increment 1.00 1.50 2.00 2.25 3.00 3.00 4.00 6.00 7.00 Total Delay 22.5 30.0 60.0 75.0 Inherent Delay
INPUT RESTRICTIONS
Freq. (MHz) Recommended Absolute 20.0 13.8 7.57 83.3 6.17 66.6 3.96 41.6 3.20 33.3 2.16 22.2 1.63 16.6 1.31 13.3 P.W. (ns) Recommended Absolute 25.0 36.0 66.0 81.0 126.0 12.0 156.0 15.0 231.0 22.5 306.0 30.0 381.0 37.5 "2003 Data Delay Devices
NOTES: increment between shown also available standard Total delay given delay address minus delay address
#03006
12/8/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7444
APPLICATION NOTES
THEORY OPERATION
quad 4-bit programmable 3D7444 delay line architecture comprised number delay cells connected series with their respective outputs multiplexed onto Delay (O1O4) user-selected programming data. Each delay cell produces output replica signal present input, shifted time. Each four lines controlled independently, serial interface. line normal operation. device contains output, which used cascade multiple devices, shown Figure
TABLE SEQUENCE
Delay Line Function Output Enable Output Enable Output Enable Output Enable Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address Address
PROGRAMMED DELAY (ADDRESS) INTERFACE
Figure illustrates main functional blocks 3D7444 device. Since device CMOS design, unused input pins must returned well defined logic levels (VDD GND). delays adjusted first shifting 20-bit programming word into device pins, then strobing signal latch values. sequence shown Table associated timing diagram shown Figure Each line associated with enable bit. Setting this will force corresponding delay line output high impedance state, while setting high returns
DELAY LINE
DELAY LINE
DELAY LINE
DELAY LINE
ADDR4 ADDR3 ADDR2 ADDR1 ENABLES
20-BIT LATCH 20-BIT SHIFT REGISTER Figure Functional block diagram
#03006
12/8/03
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7444 PROGRAMMED DELAY (ADDRESS) UPDATE
delay line memory device. stores information present input time equal delay setting before presenting output with minimal distortion. Each 4-bit delay line 3D7444 represented serially connected delay elements (individually addressed programming data), each capable storing data time equal device increment (step time). delay line memory property, conjunction with operational requirement "instantaneously" connecting delay element addressed programming data output, inject spurious information onto output data stream. order ensure that spurious outputs occur, essential that input signal idle (held high low) short duration prior updating programmed delay. This duration given maximum programmable delay. Satisfying this requirement allows delay line "clear" itself spurious edges. When address loaded, input signal begin switch (and delay will valid) after time given tPDV tEDV (see section below).
POWER SUPPLY TEMPERATURE CONSIDERATIONS
delay CMOS integrated circuits strongly dependent power supply temperature. monolithic 3D7444 programmable delay line utilizes novel innovative compensation circuitry minimize delay variations induced fluctuations power supply and/or temperature. thermal coefficient reduced PPM/C, which equivalent variation, over 0C-70 operating range, from room-temperature delay settings. power supply coefficient reduced, over 4.75V5.25V operating range, r1.5% delay settings nominal 5VDC power supply and/or r2ns, whichever greater. essential that power supply adequately bypassed filtered. addition, power should impedance construction possible. Power planes preferred.
LATCH (AL) CLOCK (SC)
tCSL
tDSC
SERIAL INPUT (SI) SERIAL OUTPUT (SO) DELAY TIMES
tDHC
tPCQ
tLDX
PREVIOUS VALUES
tLDV
VALUES
Figure Serial interface timing diagram
3D7444
3D7444
3D7444
FROM WRITING DEVICE
NEXT DEVICE
Figure Cascading Multiple Devices
#03006
12/8/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7444 INPUT SIGNAL CONSIDERATIONS
Frequency and/or Pulse Width (high low) operation adversely impact specified delay increment accuracy particular device. reasons dependency output delay accuracy input signal characteristics varied complex. Therefore Recommended Absolute Maximum operating input frequency Recommended Absolute Minimum operating pulse width have been specified.
will increase absolute maximum frequency approached. However, input frequency pulse width remain constant, device will exhibit same delays from period next (ie, appreciable jitter).
OPERATING PULSE WIDTH
Absolute Minimum Operating Pulse Width (high low) specification, tabulated Table determines smallest pulse width delay line input signal that reproduced, shifted time device output, with acceptable pulse width distortion. Minimum Operating Pulse Width (high low) specification determines smallest Pulse Width delay line input signal which output delay accuracy tabulated Table guaranteed. Operation below recommended minimum pulse width will cause delays shift slighty with respect their values long-pulse-width operation. magnitudes these deviations will increase absolute minimum pulse width approached. However, input pulse width frequency remain constant, device will exhibit same delays from period next (ie, appreciable jitter).
OPERATING FREQUENCY
Absolute Maximum Operating Frequency specification, tabulated Table determines highest frequency delay line input signal that reproduced, shifted time device output, with acceptable duty cycle distortion. Recommended Maximum Operating Frequency specification determines highest frequency delay line input signal which output delay accuracy guaranteed. Operation above recommended maximum frequency will cause delays shift slighty with respect their values low-frequency operation. magnitudes these deviations
#03006
12/8/03
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
3D7444
DEVICE SPECIFICATIONS
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Input Current Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Static Supply Current* High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Current Level Output Current Output Rise Fall Time SYMBOL -0.1 -0.1 -8.0 -6.0 UNITS NOTES 5.25V
4.75V 2.4V 4.75V 0.4V
*IDD(Dynamic) where: Average capacitance load/line (pf) Input frequency (GHz)
Input Capacitance typical Output Load Capacitance (CLD)
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER Latch Width Data Setup Clock Data Hold from Clock Clock Width (High Low) Clock Setup Latch Clock Serial Output Latch Delay Valid Latch Delay Invalid Input Pulse Width Input Period Input Output Delay SYMBOL tDSC tDHC tCSL tPCQ tLDV tLDX Period tPLH, tPHL UNITS Total Delay Total Delay NOTES
Table Table Text
NOTES: Refer PROGRAMMED DELAY (ADDRESS) UPDATE section
#03006
12/8/03
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
3D7444
SILICON DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: 25oC Supply Voltage (VDD): 5.0V 0.1V Input Pulse: High 3.3V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.7V Pulse Width: PWIN 1.25 Total Delay Period: PERIN Total Delay OUTPUT: Rload: Cload: Threshold: 10K: 1.65V (Rising Falling)
Device Under Test
10K:
Digital Scope
470:
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) OUT1 OUT2 OUT3 OUT4 TRIG DIGITAL SCOPE/ TIME INTERVAL COUNTER
Figure Test Setup
PERIN tRISE INPUT SIGNAL
2.7V 1.65V 0.6V
tFALL
2.7V 1.65V 0.6V
tPHL
tPLH OUTPUT SIGNAL
1.65V
1.65V
Figure Timing Diagram
#03006
12/8/03
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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