Lynne Kelly TECD Applications Controller Area Network (CAN) proto

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Lynne Kelly TECD Applications Controller Area Network (CAN) proto

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AN2320/D Rev. 0.1, 8/2002 Interfacing MCF5272 Standalone Controller
Lynne Kelly TECD Applications
Controller Area Network (CAN) protocol serial communications protocol developed early 1980's Robert Bosch GmbH automotive sector currently vehicle Local Area Network (LAN) standard Europe. main attributes cost, real-time capability, ability function harsh electrical environments with high degree reliability safety (making suitable only automotive applications other cost sensitive, safety critical, real-time applications such industrial control, building control, building automation, embedded networks, medical equipment). ColdFire® microprocessor established cost-sensitive solution industrial embedded network applications today. Interfacing MCF5272 ColdFire processor standalone controller, with intention integrating later ColdFire derivative with embedded Ethernet, will provide solution increasing number industrial applications requiring only field communication peripherals Ethernet connectivity also. These applications field carry time-critical routine data between central system controller remote units such motion controllers sensors require Ethernet link transfer data which processed larger blocks irregular basis. Ethernet link facilitates communication with standard PCs, typically running email, database applications, browsers. extreme, internet capability would potentially allow plants monitored from anywhere globe. real-time requirements field layer, would required. Ethernet probabilistic that often uncertain when device network will able communicate there typically guarantee message transfer prioritisation. more deterministic hence more reliable cyclical routine transfer data interface units that require reliable timely control (such motors, robotics, PLCs). This application note details hardware design software development reference design which interfaces MCF5272 microprocessor Infineon 82C900 standalone controller. recognised that integrated solution would undoubtedly more cost effective, would make design PCBs simpler, would result smaller space requirements, could reduce loading half. However, majority today's 32-bit integrated products focussed automotive markets none offer both embedded Ethernet CAN. This two-chip ColdFire solution intended provide migration path first ColdFire product with on-chip first 32-bit microprocessor with both on-chip on-chip Ethernet. Standalone controllers still tend ship large numbers which helps drive cost device down. This, coupled with cost/performance ratio ColdFire microprocessors general, makes two-chip solution viable alternative interim.
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MCF5272 Microprocessor
reference design based M5272C3 development board using daughter card provide standalone controller circuitry. This application note details design process, starting with overview MCF5272 processor 82C900 controller, reasons choosing them. followed more detailed look both hardware design software development. Full schematics basic example application software downloaded from M5272C3 webpage Motorola's ColdFire website. Motorola websites referred this document accessed from
Design Overview
object this section outline principles MCF5272 reference design, give overview MCF5272 microprocessor 82C900 controller, explain reasons choosing them this design. additional more detailed information MCF5272 82C900 themselves, please refer MCF5272 webpage, 82C900 user's manual, Figure shows basics reference design. MCF5272 microprocessor interfaced Infineon 82C900 controller using Queued Serial Peripheral Interface (QSPI). controller implements protocol while external transceiver, Philips PCA82C250, provides physical connection bus. transceivers shown here, Infineon controller twin device with dual nodes allowing connection independent buses. There need second transceiver only node required.
ColdFire MCF5272 Infineon Controller 82C900
QSPI_Clk QSPI_CSn QSPI_Din QSPI_Dout
SCLK MRST MTSR
Philips Transceiver PCA82C250
Philips Transceiver PCA82C250
Figure MCF5272 Reference Design Overview
MCF5272 Microprocessor
MCF5272 32-bit embedded processor based ColdFire core. This most application-specific ColdFire processor date, targeted low-end communications market. On-chip peripherals include Fast Ethernet Controller, slave device, Physical Layer Interface Channel
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Controller
with four ports, software HDLC module, QSPI module, support channel PWM. addition, retains System Integration Module, Chip-Select Module, hardware divide unit, General Purpose Timers, real-time interface standard ColdFire devices. decision MCF5272 ColdFire microprocessor based peripheral set, ease interface, overall system cost. There increasing demand Ethernet integrated chip; while ColdFire product will offer both until 2003, MCF5272 does have on-chip Ethernet, which reduces additional peripherals required. There also other MCF5272-specific peripherals, including QSPI, which required industrial markets. Also, majority available standalone controllers offer multiplexed interface serial peripheral interface (SPI); they rarely offer non-multiplexed parallel interface that gluelessly interfaced ColdFire processor. Using MCF5272 with on-chip increases choices suitable controllers market avoids increasing complexity cost design using interface glue logic.
Lastly, applications, both industrial automotive, often cost critical; therefore, imperative that overall system cost kept minimum. applications requiring both Ethernet, this solution will still competitively priced because aggressive price/performance ratio MCF5272. standalone solution cost more than some 32-bit integrated solutions, these solutions typically targeted different markets offer Ethernet connectivity.
Controller
Infineon 82C900 TwinCAN controller standalone controller with dual nodes allowing connection independent buses. interfaced host controller using either multiplexed interface interface, interfaced EEPROM interface initialisation when external host required. 82C900 supports message objects which assigned both nodes node. built-in, scalable FIFO mechanism message reception transmission built-in gateway functionality transferring messages between nodes. There also timestamp/frame counter indicate when message last transmitted received indicate many times message been transmitted received) Analyser monitoring activity bus. There number standalone controller modules market that adhere different specifications, support variable data rates, require different levels intervention. Infineon 82C900 standalone controller chosen because supports 2.0B protocol, because provides interface glueless connection MCF5272, because will support data rates 1Mbit/s, because level message transmission acceptance filtering supports. There currently three protocols, 2.0A, 2.0B, 2.0B passive. Infineon device supports 2.0B. difference between these protocols lies length message identifier they transmit receive message frame. 2.0A controller handle standard frames with 11-bit identifier while 2.0B controller transmit standard frames extended frames with 29-bit identifiers. Finally, 2.0B passive controllers transmit only standard frames receive both standard extended frames. majority today's applications 2.0B considered standard, with system designers often requiring extended 29-bit identifier relieve them from compromises with respect defining well-structured naming schemes. majority, all, integrated solutions market support 2.0B. backward-compatible nature protocol ensures Infineon device also handle messages with standard frame format.
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Transceiver
Regarding interface, this been touched before. standalone controllers market today have non-multiplexed interfaces none offer glueless interface MCF5272 external bus. Design complexity additional cost using parallel interface resulted being preferred choice. terms data rate support, data rates vary between 10kbit/s 1Mbit/s, depending length line degree fault tolerance required. length less than makes 1Mbit/s achievable. controllers vary data rates they support; most support 0.5Mbit/s 1Mbit/s. Infineon controller handle 1Mbit/s which desirable many today's real-time industrial applications. Finally, standalone controllers vary extent which required take over message transmission. simplest controller, known formerly BasicCAN, hardware logic dedicated creating verifying bitstream according protocol. Administration data sets sent received comprehensive acceptance filtering carried CPU, placing increased overhead processor. Full controllers, like Infineon 82C900, include extra logic provide object storage, support additional prioritisation capabilities, implement comprehensive acceptance filtering. This, along with additional on-chip FIFO gateway mechanisms, ensures overhead kept minimum. end, this means real-time performance optimised, which often most important criteria types industrial-control automation applications which this intended.
Transceiver
Philips PCA82C250 high-speed transceiver chosen interface between controller physical because supports data rates maximum 1Mbps. Alternate transceivers such fault-tolerant single-wire transceivers limit maximum data rate kbit/s 33.33 kbit/s, respectively. High-speed transceivers typically support data rates excess kbit/s.
Hardware Design
MCF5272 reference design developed around M5272C3 evaluation board using daughter card circuitry. daughter card connects evaluation board using expansion connectors already provided. M5272C3 board provides 10/100 Ethernet interface, RS232 interface, interface, SDRAM, Flash system development. additional detailed information evaluation board, including full schematics, refer M5272C3 user's manual M5272C3 webpage. Figure outlines hardware design daughtercard. main features issues (interface, reset, clocking, power supply, more) explained remainder this section. Full schematics schematic summary downloaded from ColdFire website.
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Interface
QSPI_CLK
QSPI_DOUT
QSPI_CS0
QSPI_DIN
-RST0
-INT1
+3.3V
MAX682
Charge Pump
ACT1100
24MHz Clock
82C900
Controller
-INT3
PCA82C250
Transceiver
PCA82C250
Transceiver
P[0.7]
CANH
CANL
Figure Daughter-Card Circuitry
Interface
MCF5272 QSPI module provides glueless interface 82C900's synchronous serial channel (SSC). QSPI hardware interfaces detailed here.
2.1.1
MCF5272 QSPI Module
QSPI module MCF5272 provides serial peripheral interface with queued transfer capability, which allows data transfers with intervention. QSPI interface will support data transfers, first, anywhere between bits. will support baud rates from 129.4Kbps MBps interfaced maximum devices using four peripheral chip-select lines. module total seven signals: QSPI_Dout, which serial data output from QSPI module, QSPI_Din, which serial data input QSPI module, QSPI_CLK, which QSPI clock output, QSPI_CS[0:3], which four peripheral chip-select output signals. Four signals used interface 82C900: QSPI_Dout, QSPI_Din, QSPI_CLK QSPI_CS0. clock phase, clock polarity, chip select active logic level, delays before after transfer highlighted Figure programmable QSPI registers. This flexibility clocking data transfer eliminates need additional glue logic meet 82C900 timing requirements accommodate polarity phase clock, which internally configured. data transfer baud rate also programmable; this explained more detail Section 2.2, "Clocking."
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Interface
QSPI clock delay. Determines length delay from assertion chip-select valid QSPI_CLK delay. Programmed QSPI delay register (QDLYR). Delay after transfer. Determines length delay after serial transfer. Programmed QSPI delay register (QDLYR). Clock polarity making inactive state QSPI_CLK logic level Clock phase have data changed leading edge captured following edge.
Figure QSPI Clocking Data Transfer Parameters
2.1.2
82C900 Synchronous Serial Channel
82C900 Synchronous Serial Channel (SSC) SPI-compatible serial interface, which used connect controller external host. Transfers single-read single -write accesses although channel itself optimised multiple transfers consecutive addresses. example consecutive read access consecutive write access shown Figure When chip select activated, first byte transferred should always address byte. address itself bits wide with bit, used indicate whether access read write. consecutive access requested, then transfers following address data transfers. internally increments register addresses during transfer. chip-select signal must remain active duration. 82C900 configured internally 8-bit data transfers with first. Clock polarity inactive high; clock phase configured data shift leading edge data capture following edge clock. MCF5272 also fixed msb-first transfer while data transfer size, clock polarity, clock phase programmable detailed Section 2.1.1, "MCF5272 QSPI Module." Mode pins 82C900 used configure interface, choose between 8-bit multiplexed SSC, select master when external host used slave when this design, MCF5272 external host acting master system, mode input pins interface slave operation. MCF5272 QSPI signals connected four control pins 82C900, functions which multiplexed mode inputs. When interface used slave mode, control (the 82C900 chip-select) configured input, control configured serial clock input, control configured serial data input (Master Transmit Slave Receive), control configured serial data output (Master Receive Slave Transmit).
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Interface
Infineon added optional fifth signal, ready signal (RDY), standard interface. This handshake signal, which used indicate when serial interface accessed host. However this signal required provided timings detailed Section 2.1.3, "Timing" adhered While would simple case connecting ready input signal GPIO MCF5272 reading level before accessing controller, MCF5272 QSPI programmable delays before after transfer means timing specifications without using signal.
2.1.3
Timing
Figure gives 82C900 timing requirements that must absence ready signal that indicates host when transfer allowed. consecutive-read access consecutive-write access shown. first byte transferred address subsequent transfers data bytes which read written consecutive addresses starting address defined. this mode, chip-select signal must remain active until transfer data that access complete. timing requirements, except minimum delay after reset (see Section 2.3, "Reset"), programming QSPI clock delay QSPI delay after transfer MCF5272. QSPI clock delay determines delay between chip-select assertion first valid serial clock transition, QSPI delay after transfer determines delay after each serial transfer. Figure clock delay programmed meet specification (A), while delay after transfer programmed meet other timing requirements. delay after transfer inserted only negation chip-select signal also between data transfers following final data transfer consecutive reads writes. QSPI clock delay (SCLKDELAY) delay after transfer (TxRxDELAY) defined following equations:
SCLK DELAY -CLKIN TxRx DELAY -CLKIN
range 1-127, range 1-255 CLKIN system clock frequency. 66MHz system clock, QSPI clock delay programmable between 15ns 1.9µs, delay after transfer programmable between 485ns 124µs (with option using standard delay 258ns). (90ns delay) (970ns) were chosen meet worst case specifications shown Figure
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Clocking
Read Access READ ACCESS
Serial Data Data CLKS Addr Data Data Data CLKS CLKS CLKS
Write Access WRITE ACCESS
CLKS Addr CLKS Data CLKS Data
Name
Parameter active SerialClk active Address transfer data byte transfer, read access Data byte transfer data byte transfer, read access Last data byte transfer inactive inactive active Address transfer data byte transfer, write access Data byte transfer data byte transfer, write access
Time, fCAN 84ns 584ns 584ns 459ns 167ns 209ns 209ns
Figure 82C900 Timing Specification
2.2.1
Clocking
Controller Clock Input
24-MHz external oscillator used clock controller. This ensures that protocol handled both nodes 1Mbps when controller interfaced external host using maximum access rate. This assumes built-in gateway FIFO functions being used. systems that require these additional data handling capabilities, higher frequency required unless external host-access rate reduced. worst case, data handling capability would reduced 500kbps each node when both FIFO gateway functions running with 24-MHz clock input. Using 24-MHz clock input also means oscillator chip replaced directly clock clock divider with software modification interface timing implications preferred. integrated controller MCF5272 requires 48-Mhz oscillator which provided externally M5272C3 board.
2.2.2
Baud Rate
82C900 controller serial interface baud rate limited where input clock frequency. this gives maximum possible baud rate Mbps. MCF5272 QSPI programmable baud field QSPI mode register (QMR) follows:
CLKIN BAUDRATE
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Reset
where CLKIN system clock frequency here) represents value baud field register lies between 255. baud rate 6MBps would require maximum achievable baud rate will MBps, with
Reset
reset output signal from MCF5272 processor (-RSTO) used drive reset 82C900 controller. reset signal controller need only asserted clock cycles which equates MCF5272 clocks when running MHz, MCF5272 reset will reset controller. four MCF5272 resets master reset, normal reset, soft reset, software watchdog timer reset. Master reset will reset entire processor including SDRAM, normal reset will terminate activity except SDRAM refresh cycles ensuring data stored SDRAM lost during reset, soft reset will reset external devices internal peripherals excluding SIM, chip-select controller, interrupt controller, GPIO module SDRAM controller, software watchdog timer will generate reset periodically accessed software programmed. -RSTO driven clocks during soft reset clocks when input level applied -RSTI during master normal reset when software watchdog timer times out. should noted that there must delay 1100 clock cycles following negation -RSTO before accessing controller. Reset exception processing which follows negation -RSTO will provide required delay system initialisation process should.
Power
M5272C3 board which daughter card connected supplies 3.3V power only. input required controller, transceivers, oscillator chip provided Maxim charge pump daughter card itself. MAX682 chosen because capable delivering 250mA required meet maximum possible combined load from 82C900, PCA82C250, ACT1100 oscillator chips.
Interrupts
82C900 interrupt request sources total. These sources assigned interrupt nodes which then driven output pins OUT0 OUT1. interrupt sources divided follows. Each message objects have interrupt request sources indicating when message been received when message been transmitted. Each node also four global interrupt requests which include TxRx OK-Indicates when message, assigned that node, been transmitted received okay Last Error Code-Indicates last error occur (stuff/format/CRC/bus arbitration) Error-Indicates when number errors exceeds predefined limit Frame Counter-Indicates transfer sequence message objects time instant frame last transmitted received.
Each message object assigned node source these errors. Mask registers used determine which interrupts within each message should recognised ignored generation node global interrupt request.
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82C900 Extended
Both message-specific node specific global interrupts distributed among eight interrupt nodes, interrupt nodes Message Configuration Global Interrupt Node Pointer registers. Each node then assigned interrupt request outputs, OUT0 OUT1. Requests received from interrupt node only from interrupt nodes combined output OUT1, requests from interrupt node only from nodes again combined, output OUT0. should noted that OUT0 dual functionality. 82C900 on-chip oscillator that used generate system clock. With on-chip clock divider, OUT0 used provide reduced-clock output external devices which need slower clock. OUT0 configurable Global Device Control Register.
82C900 Extended
When using 82C900, pins parallel (P0:P7) configured with extended functionality. logic state each recorded registers device which accessed bus. They used initiate message transfer GPIO where state written read from device registers status monitor monitor internal status controller during message transfer including which part data/remote/error frame currently being transferred which value been read node (A,B) associated bus. There also output clock lines which asserted high once during each time.
These pins taken header daughtercard.
Software Development
This section outlines software basic application example that sets 82C900 controller transmit message, receive message, interrupt MCF5272 when message received. begins with overview code required send receive byte over MCF5272 QSPI, illustrating data written read from 82C900 registers. followed description 82C900 register details registers addressed when using 82C900 interface. initialisation both nodes then covered finally, Section 3.4, "CAN Transmit Receive," message objects assigned node transmit assigned node receive. software verified initially connecting transceivers daughtercard externally. transmit receive message objects assigned each node were given same node would receive message transmitted node generate interrupt. M5272C3 board daughter card were then connected MPC555 development board test MCF5272 reference design fully. code been developed using Wind River's Diab compiler visionClick debugger downloaded from MCF5272C3CAN webpage modification another tool chain used template further development.
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Transmitting Receiving over MCF5272 QSPI Interface
Transmitting Receiving over MCF5272 QSPI Interface
QSPI module standard interface with queuing capabilities. Using 80-byte block static RAM, QSPI module queue transfers without intervention. divided into receive data which initial destination received data, transmit data which buffer out-bound data, command which holds command data each QSPI command executed (including which chip-select activate, whether enable delays, many bits transfer etc.). organised entries where byte command data, word transmit data, word receive data comprise queue entry. cannot accessed directly must accessed QSPI address register (QAR) QSPI data register (QDR). write results data being written entry specified address read from results data stored address specified being written QDR. address stored automatically increments after read from write QDR. QSPI operation initiated writing queue commands command RAM, writing transmit data into transmit RAM, then enabling QSPI begin transfer. QSPI begins execution command queue entry pointed queue pointer transmit data same entry transmitted. Data that simultaneously received stored this entry before queue pointer incremented. When commands executed QSPI finished flag interrupt generated. Queue pointers used begin transfer entry queue determine which command last completed. flowchart Figure outlines process sending byte data reading byte data from 82C900 controller. This explains initialisation mechanics MCF5272 QSPI interface only. Accessing registers Infineon device, particular addressing, described detail Section 3.2, "Accessing 82C900 Register." initialisation, send byte, receive byte software routines also given. Refer MCF5272 user's manual MCF5272 webpage QSPI module register level detail.
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Transmitting Receiving over MCF5272 QSPI Interface
Point Command Point Command 0x20 point first queue entry command 0x20 point first queue entry command
Write Command Write Command data transfer data transfer /CS0, assert between transfers /CS0, assert between transfers Enable programmable clock transfer delays Enable programmable clock transfer delays
Clear QSPI Interrupt Register Clear QSPI Interrupt Register Clear QSPI finish, abort write collision flags Clear QSPI finish, abort write collision flags Clear interrupts interrupts Clear
Point Transmit Point Transmit 0x00 point first queue entry command 0x00 point first queue entry command
Point Transmit Point Transmit 0x00 point first queue entry 0x00 point first queue entry
Load Transmit Load Transmit Write with address 82C900 register Write with address 82C900 register Write with data byte 82C900 register with data byte 82C900 register Write
QSPI Delay Register QSPI Delay Register Delay after transfer 970ns Delay after transfer 970ns QSPI clock delay 91ns clock delay 91ns QSPI
QSPI Wrap Register QSPI Wrap Register start queue pointer transmit RAM. start queue pointer transmit RAM. queue pointer bytes queue pointer bytes chip select inactive level chip select inactive level
Enable Transfer Enable Transfer field QSPI delay register enable field QSPI delay register enable
Poll Completion Poll Completion Poll finish flag QIR. Poll finish flag QIR.
Figure MCF5272 QSPI: Reading Writing 82C900
QSPI initialisation software example code used baud rate, clock phase, clock polarity, clock delay, delay after transfer. also used here command RAM. entries command have programmable delays enabled. timing specifications 82C900
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Load Transmit Load Transmit Write with address 82C900 register Write with address 82C900 register Write with dummy addr 82C900 register with dummy addr 82C900 register Write QSPI Wrap Register QSPI Wrap Register start queue pointer transmit RAM. start queue pointer transmit RAM. queue pointer bytes queue pointer bytes chip select inactive level chip select inactive level Enable Transfer Enable Transfer field QSPI delay register enable field QSPI delay register enable Poll Completion Poll Completion Poll finish flag QIR. Poll finish flag QIR. Point Receive Point Receive 0x10 point first entry RAM. 0x10 point first entry RAM. Read Receive Read Receive Read dummy byte. Read dummy byte. Read byte from 82C900 register access. Read byte from 82C900 register access.
QSPI Mode Register QSPI Mode Register Mbit/s baud rate, data transfer Mbit/s baud rate, data transfer Data change leading, capture following Data change leading, capture following Clock idle high Clock idle high
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Transmitting Receiving over MCF5272 QSPI Interface
vary between different accesses (for example, minimum time read access three times much write access), desirable change command entries when switching between read transfer write transfer. QSPI initialisation code:
void MCF5272_IMM *imm mcf5272_get_immp(); /*Set QSPI mode register, 5.5Mbit/s, bit, data change leading, clock idle high*/ /*Set delay after transfer clock delay*/ /*Clear flags interrupts*/ mcf5272_qspi_init()
/*Point command RAM*/ /*Set each entry continuous transfer, transfer, /CS0 delays*/
Writing 82C900 register:
/*The address 82C900 register data written passed*/ void QSPI_SendByte(uint16 CanRegAddr, uint8 Data) MCF5272_IMM *imm mcf5272_get_immp(); /*Determine 82C900 register address*/ /*Point RAM*/
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Transmitting Receiving over MCF5272 QSPI Interface
MCF5272_WR_QSPI_QAR(imm, MCF5272_QSPI_QAR_Tx);
/*Write 82C900 register address into indicating write*/ /*Write data 82C900 register into Transmit QDR*/ MCF5272_WR_QSPI_QDR(imm,Data); /*Set Wrap register byte transfer bytes), starting RAM*/ /*Set flag Delay register enable transfer*/ /*Poll QSPI finish flag completion*/ while (!(MCF5272_RD_QSPI_QIR(imm) MCF5272_QSPI_QIR_QSPIFinish))
Reading 82C900 register:
/*The address 82C900 register read passed*/ uint8 QSPI_ReadByte(uint16 CanRegAddr) MCF5272_IMM *imm mcf5272_get_immp(); /*Determine 82C900 register address*/ /*Point RAM*/ /*Write 82C900 register address read into QDR*/ /*Dummy transmission ensure QSPI clock enable receiving byte*/ /*Set Wrap register byte read transfer bytes) starting RAM*/ /*Set flag Delay register enable transfer*/ /*Poll QSPI finish flag completion*/ while (!(MCF5272_RD_QSPI_QIR(imm) MCF5272_QSPI_QIR_QSPIFinish)) /*Point RAM*/ /*Read dummy byte received address being transmitted*/ dummy
/*Read data received from 82C900 register*/ RxByte
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Accessing 82C900 Register
Accessing 82C900 Register
82C900 register divided between global control shell message buffer unit. global control shell registers known standalone shell registers, they control initialisation process after power-on reset, provide status information message transfers pending transfer interrupts, responsible condensing interrupt sources distributed among available interrupt nodes. registers assigned message buffer unit known TwinCAN registers. These registers used buffers message objects also managers FIFO, transfer messages between nodes internally in-built gateway logic being used, provide interrupt requests transmission reception message object. overview memory given below Figure register-specific information refer Infineon 82C900 user's manual,
+0000H +0080H +0200H +02C0H +0300H +0320H
Standalone Registers Reserved TwinCAN Registers (CAN node Control) Reserved TwinCAN Registers (Message Object TwinCAN Registers (Message Object
+06E0H
TwinCAN Registers (Message Object
Figure 82C900 Register
Accessing registers memory requires 11-bit addressing. Referring Figure first byte transmitted host during access contains address information. other transfers during same access data transfers. first byte transferred, only lower seven bits used define register address. eighth bit, used indicate whether access read write transfer. upper four bits register address provided PAGE register standalone shell register set. PAGE register itself accessed addresses xx7CH xxFCH hence independently value stored register. 82C900 register address therefore split illustrated code below. This highlights setting register address write access. upper four bits address written PAGE register lower bits concatenated with read write command transmitted over SPI.
void QSPI_SendByte(uint16 CanRegAddr, uint8 Data) MCF5272_IMM *imm mcf5272_get_immp();
/*Pass upper bits 82C900 register address accessed MCF5272_WR_QSPI_QAR(imm, MCF5272_QSPI_QAR_Tx); /*First byte over QSPI. indicate write operation*/ lower bits address force
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82C900 Initialisation
MCF5272_WR_QSPI_QDR(imm,Data); while (!(MCF5272_RD_QSPI_QIR(imm) MCF5272_QSPI_QIR_QSPIFinish)) /*The upper bits register address passed.*/ void CAN_SetPageReg(uint8 PageNumber) MCF5272_IMM *imm mcf5272_get_immp();
/*Page register address. accessed regardless contents*/ /*Write upper four bits PAGE register enable auto increment*/
while (!(MCF5272_RD_QSPI_QIR(imm) MCF5272_QSPI_QIR_QSPIFinish))
optimise data transfer between host 82C900, transfer data stream upon transmission single address. This illustrated Figure control incrementing address during these consecutive-read consecutive-write accesses contained PAGE register. When set, contents address register automatically incremented after each data-byte transfer. Incrementing stopped boundaries between message objects prevent unintended corruption messages. Accidentally overwriting PAGE register also prevented.
82C900 Initialisation
82C900 initialisation software logically connects nodes allows them participate message transfer. Initialisation required after controller reset MCF5272 processor after occurrence `bus off' event, both which will logically disconnect node from associated bus. code used configure nodes given below. During initialisation node must disconnected from bus; interrupts must reset baud rate must defined. This involves updating node control registers (ACR/BCR) timing registers (ABTR, BBTR) both nodes configuring interrupt mask register node generate interrupt when message received. node control registers control initialisation process, control node-specific interrupts, define operating mode. field descriptions lower bits register given Figure below.
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82C900 Initialisation
LECIE
INIT
Figure Node Control Registers (ACR/BCR)-Lower 16-bits Table Node Control Registers (ACR/BCR)-Lower 16-bits Field Descriptions
Bits 15-8 Name Reserved Node used communication over analyser monitor activity Description
timing register error counter access enable Reserved
LECIE Last error code interrupt enable. INIT Error interrupt enable. Status change interrupt enable. Reserved Connect disconnect node from bus.
timing register controls data transfer rate bus. field descriptions given below followed explanation values these fields define baud rate.
DIV8
TSEG2
TSEG1
Figure Node Timing Registers (ABTR, BBTR) Table Node Control Registers (ACR/BCR)-Lower 16-bits Field Descriptions
Bits 14-12 11-8 Name DIV8 Description Baud rate prescaler clock source (CAN clock clock/8)
TSEG2 Time segment after sample point. TSEG1 Time segment before sample point. Resynchronisation jump width Baud rate prescaler.
time divided into different segments (according ISO-DIS 11898 standard) each segment multiple time quantum. segments shown below. synchronisation segment (Tsync) allows phase synchronisation between receiver transmitter; propagation time segment (Tprop) allows physical propagation delay transceiver circuit; buffer segments (Tbuff1 Tbuff2) provide delay before after data sample point compensate phase difference between receiver transmitter detected during synchronisation.
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Transmit Receive
time
Tsync
Tprop
Tbuff1
Tbuff2
Sample
Transmit
Figure Time Segments
time, therefore, equates (Tsync Tprop Tbuff Tbuff tquantum period time quantum.
where tquantum
TSEG1, SJW, TSEG2 fields timing register used define different segments DIV8 time quantum period follows:
Tsync Tprop Tbuff TSEG1 Tbuff2 TSEG2
quantum
register settings example code below, TSEG1 TSEG2 This results time baud rate 0.5Mbit/s. baud rate prescaler used; therefore, DIV8 ignored these calculations. Initialisation code both nodes almost identical, only difference being initialisation node interrupt mask register generate interrupt when message received. Message object assigned node message object assigned node initialisation code shown node
/*Node control register QSPI_SendByte(CAN_BCR, 0x41); reset interrupts, stop initialise*/
/*Bit timing register kbit/s ((0+1)+(6+1)+(7+1))* 0.125us)*/ QSPI_SendByte(CAN_BBTR, 0x02); QSPI_SendByte(CAN_BBTR+1, 0x67); /*Enable considered interrupt source*/ QSPI_SendByte(CAN_BIMR0, 0x02); /*synchronise node enable*/ QSPI_SendByte(CAN_BCR, 0x00);
Transmit Receive
application example code, node used transmit data node used receive data. When data received, interrupt generated, data retrieved, data transmitted. receive transmit data, each node must assigned message object. This message object must configured using message object control, configuration, arbitration, data registers. message object control register used enable interrupts transmitting receiving message, message
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Transmit Receive
valid invalid, signal update message. configuration register determines which node message object assigned defines message identifier length number data bytes transmitted received, sets object transmit receive, selects interrupt node message object configured generate interrupt transmitting receivng message. data register used store data transmission store data received. There data bytes message; therefore, each message object 32-bit data registers. Finally, arbitration register holds message identifier. bit-level specific information, refer 82C900 user manual, example code message objects initialised function main(), following initialisation QSPI module intialisation 82C900 controller detailed above. function main() listed below. Message object assigned node configured transmit bytes data, message object assigned node configured receive bytes data. Both message objects assigned same that, when both nodes connected externally transceivers, node will receive data transmitted node interrupt service routine, also listed below, data received retrieved output over terminal UART M5272C3 board. interrupt then reset data transmitted.
void main mcf5272_wr_sr (MCF5200_SR_IPL_0);
/*Initialise QSPI module*/ mcf5272_qspi_init();
/*CAN node initialisation*/ CAN_Node_Init();
/*Assign Msg0 node transmit bytes data, CAN_MsgObj_Init(A, Msg0, Stand,
with standard
/*Assign Msg1 node receive bytes data, with standard CAN_MsgObj_Init(B, Msg1, Stand, /*Load Msg0 transmit data*/ CAN_MsgObj_TxData(Msg0, 0xAA55AA55, 0x55AA55AA); /*Enable Msg1 receive interrupt, assign interrupt node /OUT1*/ /*Enable Msg1 receive*/ CAN_MsgObjRx_Enable(Msg1); /*Enable Msg0 begin transmitting*/ CAN_MsgObjTx_Start(Msg0);
while
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Transmit Receive
_interrupt_
void ext_irq1_handler (void) MCF5272_IMM *imm mcf5272_get_immp(); printf("ext_irq1_handler\n"); /*Read received data output over M5272C3 terminal uart*/ CAN_MsgObj_RxData(Msg1,8); /*Set Int1 /Out1*/ /*Msg interrupt pending flag reset*/ CAN_MsgObj_IntReset(Msg1);
/*Reset transmission message object, inhibit transmission*/ CAN_MsgObjTx_Reset(Msg0); /*Alternate message object data*/ (toggle) CAN_MsgObj_TxData(Msg0, 0x55AA55AA, 0x11001100); toggle else CAN_MsgObj_TxData(Msg0, 0x11001100, 0x55AA55AA); toggle /*Set message object start transmission*/ CAN_MsgObjTx_Start(Msg0);
functions called main interrupt service routine have been made generic possible allowing message object assigned node, allowing message object configured transmit object receive object, allowing number bytes transmission reception, allowing message changed easily, ensuring interrupts enabled disabled easily.
CAN_MsgObj_Init assigns message object node, defines number bytes transfer, sets message During initialisation update, message object must invalid prevent controller from using request flags must reset, data flag must reset show update data occurred yet, case transmit message object, automatic transmission must disabled. Once flags reset, message object inoperable automatic transmission disabled. When message object configured receive then data lost flag must reset. void CAN_MsgObj_Init(uint8 Node, uint8 Msg, uint8 TxRx, uint8 NoBytes, uint8 uint32 IDnum) /*Msg tagged invalid allow update*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0x7F);
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/*Msg interrupt pending flag reset*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xFD); /*Msg remote request flag reset*/ QSPI_SendByte(CAN_MSG_CTRL+ (Msg*0x20),0x7F); /*Msg transmission request flag reset*/ QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xDF); /*Inhibit transmission reset data lost flag (TxRx QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xFD); else (TxRx QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xF7);
/*Reset data flag QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xFB); /*Assign Node, bytes*/ QSPI_SendByte(CAN_MSG_CONFIG (Msg*0x20), /*Set ID*/ Stand) IDnum IDnum QSPI_SendByte(CAN_MSG_ARB (Msg*0x20), (uint8)(IDnum));
QSPI_SendByte(CAN_MSG_ARB+1 (Msg*0x20), (uint8)(IDnum>>8)); QSPI_SendByte(CAN_MSG_ARB+2 (Msg*0x20), (uint8)(IDnum>>16)); QSPI_SendByte(CAN_MSG_ARB+3 (Msg*0x20), (uint8)(IDnum>>24)); CAN_MsgObj_TxData
loads message data register with data transmitted. Each message object 32-bit data registers which loaded with bytes data transmission store bytes data when configured receive object.
void CAN_MsgObj_TxData(uint8 Msg, uint8 NoBytes, uint32 data1, uint32 data2) uint16
/*Split data into bytes load into 2x32 data register*/ (n=0; NoBytes; n++) ((NoBytes>4)&&(n>=4)) QSPI_SendByte(CAN_MSG_DAT (Msg*0x20), (uint8)(data2>>(n-4)*8)); else QSPI_SendByte(CAN_MSG_DAT (Msg*0x20), (uint8)(data1>>n*8));
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CAN_MsgObj_IntEnable enables message object generate interrupt successful transmission
reception data. selects interrupt node pointer used which then routed external interrupt request signals, OUT1 OUT0, using 82C900 global control register.
void CAN_MsgObj_IntEnable(uint8 Msg, uint8 TxRx, uint8 IntNode) (TxRx /*Set receive interrupt node pointer*/ QSPI_SendByte(CAN_MSG_CONFIG+2 (Msg*0x20), IntNode); /*Msg interrupt enable*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xFB);
else /*Set transmit interrupt node pointer*/ QSPI_SendByte(CAN_MSG_CONFIG+2 (Msg*0x20), (uint8)(IntNode<<4)); /*Msg interrupt enable*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xEF);
CAN_MsgObjRx_Enable enables receive message object receive data bus.
void CAN_MsgObjRx_Enable(uint8 Msg) /*Msg valid QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xBF);
CAN_MsgObjTx_Start sets message object begin transmission. addition validating
message object receive above), data flag must set, update flag must signal completion, transmit request flag must set.
void CAN_MsgObjTx_Start(uint8 Msg) /*Msg update complete, automatically*/ QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xF7); /*Msg data*/
QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xFE); /*Msg valid*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xBF); /*Msg request flag set*/ QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xEF);
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Revision History
CAN_MsgObjTx_Reset resets message object after transmission must called anytime transmit data updated.
void CAN_MsgObjTx_Reset(uint8 Msg) /*Msg tagged invalid allow update*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0x7F); /*Msg data*/ QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xFD); /*Msg Update, inhibited*/ QSPI_SendByte(CAN_MSG_CTRL+1 (Msg*0x20), 0xFB);
CAN_MsgObj_IntReset resets
message object interrupt.
void CAN_MsgObj_IntReset(uint8 Msg) /*Reset interrupt pending flag*/ QSPI_SendByte(CAN_MSG_CTRL (Msg*0x20), 0xFD);
Summary
This application note detailed hardware design software development MCF5272 reference design, ColdFire solution that provides migration path first ColdFire product with on-chip first 32-bit microprocessor with both on-chip on-chip Ethernet. Design schematics, application example software, additional reference material downloaded from M5272C3 webpage.
Revision History
Table Revision History
Revision Level Original. Updated Motorola URLs minor changes language. Description
Table describes revision history this document.
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AN2320/D
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Lynne Kelly TECD Applications Controller Area Network (CAN) proto

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