Frank Mortan Mark Frimann ABSTRACT TI's 56-ball MicroStar package, reg
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16-Bit Widebus Logic Families 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch (VFBGA) Packages
Frank Mortan Mark Frimann ABSTRACT TI's 56-ball MicroStar package, registered under JEDEC MO-225, demonstrated through modeling experimentation that optimal solution reducing inductance capacitance, improving thermal performance, minimizing board area usage integrated functions. Multiple functions released 56-ball MicroStar package have superior performance characteristics, compared same functions 48-pin 56-pin TSSOP TVSOP packages. Standard Linear Logic
Contents Introduction Application Examples Industry Requirements Customer Requirements Comparison Alternative Solutions
Physical Description Package Characteristics 3.1.1 MicroStar Package Dimensions 3.1.2 MicroStar Package Pinouts 3.1.3 Package Reliability 3.1.4 Power Dissipation Electrical Performance 3.2.1 Package Parasitics 3.2.2 Simultaneous-Switching Behavior 3.2.3 Simultaneous-Switching Procedure Graphs 3.2.4 Propagation Delay JEDEC Definition Benefits Evaluation Units MicroStar Package Marking Packing Marking Tape Reel Sockets Socket Ordering Information Conclusion
Trademarks property their respective owners.
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List Figures MicroStar Package Cross Section 56-Ball MicroStar Package Profile 56-Ball MicroStar Package, Bottom Views 48-Pin Function Assignment, View 56-Pin Function Assignment, View MicroStar Package Thermal Comparisons Multilayer JEDEC 1S2P Test Board, Thermal Vias Zero Airflow MicroStar Package Thermal Performance Multilayer JEDEC 1S2P Test Board Thermal Vias Various Airflow Velocities Effect Thermal Vias MicroStar Package Thermal Performance Using JEDEC 1S2P Test Board Various Airflow Velocities Area-Normalized Power Dissipation 25°C Ambient Temperature Using JEDEC 1S2P Test Board Simultaneous-Switching Measurement Setup Simultaneous-Switching Parameters Measured Simultaneous-Switching Ground Bounce, 48-Pin TVSOP Package Measured Simultaneous-Switching Ground Bounce, 48-Pin TSSOP Package Measured Simultaneous-Switching Ground Bounce, 48-Pin SSOP Package Measured Simultaneous-Switching Ground Bounce, 56-Ball VFBGA Package Measured Simultaneous-Switching High Bounce, 48-Pin TVSOP Package Measured Simultaneous-Switching High Bounce, 48-Pin TSSOP Package Measured Simultaneous-Switching High Bounce, 48-Pin SSOP Package Measured Simultaneous-Switching High Bounce, 56-Ball VFBGA Package Simultaneous-Switching Ground Bounce, 48-Pin TVSOP (top), 48-Pin TSSOP (bottom) Simultaneous-Switching Ground Bounce, 48-Pin SSOP (top), 56-Ball VFBGA (bottom) Simultaneous-Switching High Bounce, 48-Pin TVSOP (top), 48-Pin TSSOP (bottom) Simultaneous-Switching High Bounce, 48-Pin SSOP (top), 56-Ball VFBGA (bottom) Rising Edge Propagation Delay Time Relative Number Simultaneously Switching Outputs SSOP, TSSOP, TVSOP, VFBGA Packages Falling Edge Propagation Delay Time Relative Number Simultaneously Switching Outputs SSOP, TSSOP, TVSOP, VFBGA Packages Device Marking Example Tape Dimensions Reel Dimensions
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List Tables 56-Ball MicroStar Package Releases Date Area Savings From 56-Ball MicroStar Package Comparison Area/Bit Ratios Weights MicroStar Package Attributes Package Reliability Qualification Results Board-Level Reliability Results 56-Ball (VFBGA) MicroStar Package Thermal Performance Effect Thermal Vias Various Airflows Electrical Characteristics 56-Ball MicroStar Package Comparison 56-Ball MicroStar Package 56-Pin Function Alternative Packaging Comparison 56-Ball MicroStar Package 48-Pin Function Alternative Packaging Name Markings Various MicroStar Package VFBGA Offerings Tape Dimensions
Introduction
system circuit complexity increases, competitive pressures force reduction system prices, requirement cost-effective bus-interface technology creates necessity solutions system needs. Today, major challenge digital-processing industry reduction overall system costs complexity functionality increase. These marketplace forces have resulted circuit integration board miniaturization becoming necessary trend. address these rapidly evolving customer requirements, defined very thin fine-pitch (VFBGA) package solution, known MicroStar package, best serve customers' needs. Modeling experimentation show that MicroStar package optimal solution reducing inductance capacitance, improving thermal performance, minimizing board area support integrated functions. objective provide significant improvements over existing packages, well cost savings manufacturing process. purpose this document introduce first VFBGA solution, 56-ball MicroStar package. Thirty-one devices 56-ball MicroStar package have been released production. Additional products will released, depending market interest customer demand. Both 48-pin 56-pin functions have been released 56-ball MicroStar package. Functions both counts have identical physical dimensions, differ only pin-to-ball assignment substrate design, allowing no-connects 48-pin functions serve enhancement board-level reliability. definition 56-ball VFBGA package discussed this application report. definition MicroStar package terms standardization, both physical mechanical, developed provide industry with compatible package solutions. products released date listed Table include bus-hold options.
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Table 56-Ball MicroStar Package Releases Date
FAMILY ALVC ALVT Advanced low-voltage CMOS technology Advanced low-voltage BiCMOS technology Advanced very low-voltage CMOS logic Crossbar technology Low-voltage CMOS technology Low-voltage BiCMOS technology 16244, 16373, 16374 16244, 16373, 16374 16211, 16212 16244, 16245, 16373, 16374, 16543 16244, 16245, 16373, 16374 RELEASED FUNCTIONS 16244, 16834, 16835, 16245, 16269, 16373, 16374, 16501, 16835
Application Examples
Industry Requirements
requirement reduce board area usage necessitates package solution that integrates logic addresses improved electrical thermal characteristics package. selection 56-ball MicroStar package addresses these issues with improved performance standardized pinouts. 1999, initial study OEMs worldwide subcontractors revealed that customers desired solutions with identified both bottom sides, pinout with ground balls located inside matrix, signal balls peripheral areas package. MicroStar packages provide this with single-layer routing pins. found that 0.65-mm pitch 0.117-mm (4.6-mil) trace width/spacing 0.381-mm finished mil) both desired OEMs feasible manufacture. technology progressed point that 10-mil drill economical technology 1.5748-mm (62-mil) boards, micro-via technology employing lasers reduced costs vias 0.2032-mm (8-mil) diameter less. More recently, been established that current technology progressed even further with respect trace width spacing. Many offshore printed circuit board (PCB) manufacturing companies currently produce 0.0559-mm (2.2-mil) boards with via-in-pad interconnect. However, this capability more expensive must balanced with production volumes payback considerations. Because these reduced-pitch efforts, 0.117-mm (4.6-mil) capabilities have experienced increased yields through similar process material innovations, have become even more common. Informal discussions with United States manufacturers reveal that majority domestic industry process capabilities down 0.107-mm (4.4-mil) level. percentage even higher Asian market. imposing unrealistic requirements vendors, have determined that 0.65-mm pitch optimal choice this time, given current technology board yields. MicroStar package offered supports customer requirements enables easier, more economical design/layout, along with improved solder-joint reliability based life cycle studies, while reducing consumption valuable board area. Experiments modeling also have shown improvement board-level reliability over land grid array (LGA) packages increased seating height. VFBGA also provides significant improvements parasitic capacitance inductance compared 48-pin 56-pin TSSOP TVSOP packages. Improved thermal performance overall height less than makes MicroStar package ideal height-constrained applications such PCMCIA. more detailed package comparison provided other subsections this application report.
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Customer Requirements
Each customer unique requirements; however, there common issues across industry addressed, TI's goal provide targeted solution these needs. Within personal computer (PC) industry, trend integrate much logic possible into smaller packages save space motherboards peripheral cards. space constraints, cards require dense integration small footprints, with improved electrical thermal performance. Commonality package types clocks, registers, memory chips dual inline memory modules (DIMMs) achieved using MicroStar package, thus creating cost-effective common manufacturing processes OEMs. telecommunications industry, base stations becoming small ubiquitous, requiring repackaging many circuits into denser boards. Also, within telecommunications industry, new, complex, smaller equipment must interface with legacy systems provide cost-effective upgrade solutions existing capabilities.
Comparison Alternative Solutions
Footprint areas 56-ball MicroStar packages show space savings compared 56-pin TSSOP, compared very thin small-outline package (TVSOP). Table provides comparison physical dimensions area savings 56-ball MicroStar package alternative packages. Table Area Savings From 56-Ball MicroStar Package
COUNT PACKAGE TYPE MicroStar TVSOP TSSOP TVSOP TSSOP PITCH (mm) 0.65 PACKAGE DIMENSION (mm) 12.5 11.3 14.0 FOOTPRINT (mm2) 31.5 62.1 101.3 72.3 113.4 MAXIMUM HEIGHT (mm) AREA SAVINGS 49.3 68.9 56.4 72.2
MicroStar package offers significant area savings over alternative packaging technologies available today's market, well superior area/bit ratios less than mm2/bit. Weight savings (see Table Table Comparison Area/Bit Ratios Weights
COUNT PACKAGE TYPE MicroStar TVSOP TSSOP TVSOP TSSOP FOOTPRINT (mm2) 31.5 62.1 101.3 72.3 113.4 AREA/BIT (mm2) 1.9688 3.8813 6.3313 4.5188 7.0875 WEIGHT 0.057 0.118 0.191 0.135 0.235
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Physical Description
Package Characteristics
Figure shows cross-section view MicroStar package.
Epoxy Molding
Silicon
Gold Bond Wire
Tape Substrate
Copper Trace
Figure MicroStar Package Cross Section Table summarizes package attributes 56-ball MicroStar package. Table MicroStar Package Attributes
ATTRIBUTE Ball count Ball configuration (rows, columns) Ball-to-ball pitch (mm) Square/rectangular Ball diameter (mm) Package body width (mm) Package body length (mm) Package thickness (total height, Package weight (mg) Shipping media, tape reel (units/reel) MicroStar depopulated 0.65 Rectangular 0.35 minimum maximum 56.9
1000 Desiccant packing Level Package qualified JEDEC Level moisture condition, 220°C reflow
3.1.1
MicroStar Package Dimensions
Figures show physical dimensions 56-ball MicroStar package. missing hole identifies quadrant.
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Figure 56-Ball MicroStar Package Profile
VIEW BOTTOM VIEW
Figure 56-Ball MicroStar Package, Bottom Views
3.1.2
MicroStar Package Pinouts
pinout configuration Figure adopts same naming convention applied industry logic devices 48-pin TSSOP, TVSOP, SSOP packages.
Control Ground Connection
Figure 48-Pin Function Assignment, View
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pinout configuration Figure adopts same naming convention applied industry logic devices 56-pin TSSOP, TVSOP, SSOP packages.
Control Ground Connection
Figure 56-Pin Function Assignment, View
3.1.3
Package Reliability
56-ball MicroStar package qualified Joint Electronics Device Engineering Council (JEDEC) Moisture Level released Level optimum reliability, reflow(s) should completed soon practical after removing components from pack; however, JEDEC Level allows four weeks before baking required (assuming ambient conditions 30°C relative humidity). Table summarizes package reliability data obtained from qualification testing. test chip ALVCH16501, revision, mils, preconditioned JEDEC Level [85°C relative humidity three infrared (IR) reflows 220°C]. Table Package Reliability Qualification Results
RELIABILITY QUALIFICATION TEST SAMPLE SIZE/FAILS QUALIFICATION 39/0 39/0 77/0 77/0 26/0 15/0 Pass 45/0 QUALIFICATION 39/0 39/0 77/0 77/0 26/0 15/0 Pass 45/0 QUALIFICATION 39/0 39/0 77/0 77/0 26/0 15/0 Pass 45/0
Steady-state life test (150°C, hours) Highly Accelerated Stress Test (HAST) (130°C relative humidity) Temperature cycle (-65 150°C, 1000 hours) Autoclave (121°C, hours) Solderability hours steam age) Flammability
Thermal shock (-65°C 150°C, 1000 cycles) X-ray Physical dimensions Manufacturability High-temperature storage (150°C, 1000 hours)
Board Level Reliability (BLR) testing conducted using daisy-chained package soldered with eutectic solder nonsolder-mask defined (NSMD) single-sided, 0.7874-mm (31-mil) thick board with organic solder preservative (OSP) finished copper pads 0.40-mm diameter. temperature-cycling parameters were -40° +125°C, with 10-minute dwell extremes 5-minute transition time. sample population tested characteristic life, which 63.2% samples experiencing continuity failure. Table summarizes results.
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Table Board-Level Reliability Results
CYCLES FIRST FAILURE 1847 CYCLES POPULATION FAILURE 1808 CYCLES 63.2% POPULATION FAILURE 2833
Table cycles-to-1%-population-failure value statistically derived from failure distribution, while cycles-to-first-failure value experimentally derived data point.
3.1.4
Power Dissipation
Because small size, convective cooling unit area more efficient with 56-ball MicroStar package than larger packages. However, conduction still dominant mode transfer, with minor contribution from radiation. conduction mode, balls serve sink path PCB. number weight metal layers, plus component layout proximity other power sources have significant effect dissipation. Thermal performance also significantly influenced size because conduction efficiency depends number balls overlapped chip. However, design largest effect, models show that introduction thermal vias 0.30-mm (12-mils) diameter ground balls improve performance additional multimetal-layered PCBs. Performance data modeled using JEDEC 1S2P test board with thermal conductivity approximately W/mK. must emphasized that system-level performance extremely dependent upon design, component layout proximity other power sources, airflow, orientation, board-to-board spacing system's upper level assembly. Values thermal impedance should used only guidelines further system-level modeling, indication total system thermal performance. Figures through compare 56-ball MicroStar package thermal performance alternative packages, illustrate effect forced-air cooling power dissipation, both with without thermal vias (see Tables
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Power Dissipation
Ambient Temperature Note Power dissipation calculated using junction temperature 125°C size
Figure MicroStar Package Thermal Comparisons Multilayer JEDEC 1S2P Test Board, Thermal Vias Zero Airflow Table 56-Ball (VFBGA) MicroStar Package Thermal Performance
VELOCITY (ft/min) 37.9 36.5 34.7
(°C/W) (°C/W) (°C/W)
41.5 21.6 10.0
Power Dissipation
Ambient Temperature Note Power dissipation calculated using junction temperature 125°C size
Figure MicroStar Package Thermal Performance Multilayer JEDEC 1S2P Test Board, Thermal Vias Various Airflow Velocities
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Power Dissipation
Ambient Temperature Note Power dissipation calculated using junction temperature 125°C thermal vias ground pins
Figure Effect Thermal Vias MicroStar Package Thermal Performance Using JEDEC 1S2P Test Board Various Airflow Velocities Table Effect Thermal Vias Various Airflows
VELOCITY (ft/min) 34.5 33.4 8.5% 7.8%
(°C/W) with vias
effectiveness
10.8%
comparison area-normalized thermal dissipation TSSOP, TVSOP, 56-ball MicroStar packages shows that 56-ball VFBGA package 25°C, with thermal vias zero airflow, exceeds TVSOP package exceeds TSSOP package (see Figure
Area-Normalized Power Dissipation 25°C mW/mm2 14.10 56-Ball MicroStar 48-Pin TSSOP 56-Pin TSSOP 48-Pin TVSOP 56-Pin TVSOP 13.82 27.76 28.76 76.50
Figure Area-Normalized Power Dissipation 25°C Ambient Temperature Using JEDEC 1S2P Test Board
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3.2.1
Electrical Performance Package Parasitics
Table summarizes parasitic inductance capacitance characteristics 56-ball MicroStar package. Minimum, mean, maximum values given balls package. Table Electrical Characteristics 56-Ball MicroStar Package
56-PIN FUNCTIONS (nH) Minimum Mean Maximum 1.000 1.952 3.191 (pF) 0.162 0.283 0.434 48-PIN FUNCTIONS (nH) 1.398 2.264 2.722 (pF) 0.117 0.306 0.404
Tables summarize differences between 56-ball MicroStar package 48-pin 56-pin TSSOP TVSOP packages. 56-ball MicroStar package offers less inductance less capacitance than 56-pin TSSOP. Resistance values, which were virtually unchanged, omitted. Table Comparison 56-Ball MicroStar Package 56-Pin Function Alternative Packaging
PACKAGE 56-Ball MicroStar package (56-pin function) 56-pin TVSOP 56-pin TSSOP INDUCTANCE (mh) 1.952 2.945 3.324 CAPACITANCE (pF) 0.283 0.391 0.564 33.72 41.28 27.62 49.82
Table Comparison 56-Ball MicroStar Package 48-Pin Function Alternative Packaging
PACKAGE 56-Ball MicroStar package (48-pin function) 48-pin TVSOP 48-pin TSSOP INDUCTANCE (mh) 2.264 3.013 3.019 CAPACITANCE (pF) 0.306 0.371 0.507 24.86 25.01 17.52 39.64
3.2.2
Simultaneous-Switching Behavior
Figure shows simultaneous-switching measurement setup position outputs examined using LVCH16244A device.
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3.2.3
Simultaneous-Switching Procedure Graphs
Figure Simultaneous-Switching Measurement Setup this measurement procedure, input connected fixed state, high state, while other inputs switched simultaneously. Figure test setup. outputs connecting driver react changes various inputs with certain delay, while nonswitched output should maintain constant high state. However, three factors lead reaction nonconnected input:
Crosstalk between neighboring pins brief notch supply voltage, measurable from outside, caused inductance lead brief increase grounding level, measurable from outside, caused ground lead
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Figure sets parameters definitions significance this measurement procedure. Points curve defined
PARAMETER VOHP (voltage output high peak) VOHV (voltage output high valley) VOLP (voltage output peak) VOLV (voltage output valley) (voltage input high) (voltage input low) High bounce High bounce Ground bounce Ground bounce Threshold Threshold DEFINITION Peak output voltage value during static high nonswitched output Minimum output voltage during static high nonswitched output Peak output voltage value during static nonswitched output Minimum output voltage value during static nonswitched output Minimum input voltage value, ensuring high output state Maximum input voltage value, ensuring output state
critical parameters VOLP static state VOHV high static state because their worst case switching thresholds exceed maximum minimum levels.
Volts -1.0 -2.0 Time VOHP Unswitched Output High State VOHV Threshold
VOLP Threshold VOLV Unswitched Output State
Figure Simultaneous-Switching Parameters ground-bounce high-bounce measurements simultaneous switching several outputs shown Figures through 48-pin TVSOP, TSSOP, SSOP, 56-ball VFBGA packages investigated this application report.
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Ground Bounce, 48-Pin TVSOP Package, Bits Switching, Static State
Unswitched Output Input Signal
Input Signal(s)
Volts
Threshold
-0.5
Measured Unswitched Output State
-1.0 Time
Figure Measured Simultaneous-Switching Ground Bounce, 48-Pin TVSOP Package
Ground Bounce, 48-Pin TSSOP Package, Bits Switching, Static State
Unswitched Output Input Signal
Input Signal(s) Volts -0.5 -1.0 Time Measured Unswitched Output State
Threshold
Figure Measured Simultaneous-Switching Ground Bounce, 48-Pin TSSOP Package
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Ground Bounce, 48-Pin SSOP Package, Bits Switching, Static State
Unswitched Output Input Signal
Input Signal(s)
Volts
ILThreshold
Measured Unswitched Output State
-0.5
-1.0 Time
Figure Measured Simultaneous-Switching Ground Bounce, 48-Pin SSOP Package
Ground Bounce, 56-Ball VFBGA Package, Bits Switching, Static State
Unswitched Output Input Signal
Input Signal(s)
Volts
ILThreshold
Measured Unswitched Output State
-0.5
-1.0 Time
Figure Measured Simultaneous-Switching Ground Bounce, 56-Ball VFBGA Package
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High Bounce, 48-Pin TVSOP Package, Bits Switching, Static High State Volts Threshold Input Signal(s) Time Measured Unswitched Output High State
Unswitched Output Input Signal
Figure Measured Simultaneous-Switching High Bounce, 48-Pin TVSOP Package
High Bounce, 48-Pin TSSOP Package, Bits Switching, Static High State Volts Threshold Input Signal(s) Time Measured Unswitched Output High State
Unswitched Output Input Signal
Figure Measured Simultaneous-Switching High Bounce, 48-Pin TSSOP Package
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High Bounce, 48-Pin SSOP Package, Bits Switching, Static High State
Unswitched Output Input Signal
Input Signal(s) Time Threshold Measured Unswitched Output High State
Volts
Figure Measured Simultaneous-Switching High Bounce, 48-Pin SSOP Package
High Bounce, 56-Ball VFBGA Package, Bits Switching, Static High State
Unswitched Output Input Signal
Measured Unswitched Output High State
Volts
Input Signal(s) Time
Threshold
Figure Measured Simultaneous-Switching High Bounce, 56-Ball VFBGA Package
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Additional data taken show results switching noise caused number pins increased from resulting graphs Figures through Figures show graphs both VOLP VOLV voltage levels number output pins increases. Figures show graphs both VOHP VOHV voltage levels number output pins increases.
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LVCH16244A 48-Pin TVSOP Package VOLP Linear (VOLP) VOLP /VOLV Unswitched Output VOLP (Number Switching) VOLV Linear (VOLV)
-0.5 VOLV (Number Switching)
-1.0
-1.5 Number Simultaneous-Switching Outputs LVCH16244A 48-Pin TSSOP Package VOLP Linear (VOLP) VOLP /VOLV Unswitched Output VOLP (Number Switching) VOLV Linear (VOLV)
-0.5 VOLV (Number Switching) -1.0
-1.5 Number Simultaneous-Switching Outputs
Figure Simultaneous-Switching Ground Bounce, 48-Pin TVSOP (top), 48-Pin TSSOP (bottom)
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LVCH16244A 48-Pin SSOP Package VOLP Linear (VOLP) VOLV Linear (VOLV)
VOLP /VOLV Unswitched Output
VOLP (Number Switching)
-0.5
VOLV (Number Switching)
-1.0
-1.5
Number Simultaneous-Switching Outputs LVCH16244A 56-Ball VFBGA Package VOLP Linear (VOLP) VOLV Linear (VOLV)
VOLP /VOLV Unswitched Output
VOLP (Number Switching)
VOLV (Number Switching) -0.5
-1.0
-1.5
Number Simultaneous-Switching Outputs
Figure Simultaneous-Switching Ground Bounce, 48-Pin SSOP (top), 56-Ball VFBGA (bottom)
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LVCH16244A 48-Pin TVSOP Package
VOHP (Number Switching) VOHP /VOHV Unswitched Output Static Condition
VOHV (Number Switching)
VOHP Linear (VOHP) VOHV Linear (VOHV)
Number Simultaneous-Switching Outputs
LVCH16244A 48-Pin TSSOP Package
VOHP (Number Switching)
VOHP /VOHV Unswitched Output
Static Condition
VOHV (Number Switching)
VOHP Linear (VOHP) VOHV Linear (VOHV)
Number Simultaneous-Switching Outputs
Figure Simultaneous-Switching High Bounce, 48-Pin TVSOP (top), 48-Pin TSSOP (bottom)
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LVCH16244A 48-Pin SSOP Package VOHP /VOHV Unswitched Output Static Condition Number Simultaneous-Switching Outputs LVCH16244A 56-Ball VFBGA Package VOHP Linear (VOHP) VOHV Linear (VOHV) VOHV (Number Switching) VOHP (Number Switching)
VOHP (Number Switching) VOHP /VOHV Unswitched Output Static Condition
VOHV (Number Switching)
VOHP Linear (VOHP)
VOHV Linear (VOHV)
Number Simultaneous-Switching Outputs
Figure Simultaneous-Switching High Bounce, 48-Pin SSOP (top), 56-Ball VFBGA (bottom)
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ground-bounce high-bounce interference voltages produced simultaneous switching must exceed threshold-voltage range subsequent input stage (1.4 package types investigated meet this requirement investigated SN74LVCH16244A logic function. Although components SSOP TSSOP packages slightly exceed input voltage threshold relevant logic states, switching subsequent stage expected because typical threshold voltage reached under circumstances. best result obtained this investigation ball grid array package. positive effect favorable ball arrangement, with additional balls, evident. small part differences measured could component spread rather than being exclusively result package being measured. process technology involved also decisive effect interference level. However, results here give idea general tendencies that apply other logic families.
3.2.4
Propagation Delay
package type also influences increase propagation delay that occurs when several outputs switch simultaneously. inductance supply ground leads decisive factor. measure this behavior various packages, relation between propagation delay number outputs switching measured. (see Figures 25). cases, outputs were, accordance with data sheet, loaded with SN74LVCH16244A Widebus packages. Y-axis shows increase propagation delay time (additional switching time required) X-axis shows number outputs switching. representation increase propagation delay time selected eliminate fluctuations absolute switching speed that occur result variations component tolerances. Because absolute increase propagation delay time rising edges 1.65 0.03 1.15 falling edge, measurements upper limits achievable measurement accuracy given measurement setup measuring instruments used. This reason nonlinearities data curves.
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Rising Edge, Low-to-High Transition Additional Propagation Delay Number Outputs Switching TVSOP VFBGA SSOP TSSOP
Figure Rising Edge Propagation Delay Time Relative Number Simultaneously Switching Outputs SSOP, TSSOP, TVSOP, VFBGA Packages
Falling Edge, High-to-Low Transition Additional Propagation Delay Number Outputs Switching VFBGA Ball TVSOP TSSOP SSOP
Figure Falling Edge Propagation Delay Time Relative Number Simultaneously Switching Outputs SSOP, TSSOP, TVSOP, VFBGA Packages
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JEDEC Definition
56-ball VFBGA variation received final registration from JEDEC JC-11 under semiconductor package standard MO-225. device pinout submitted JC-40 Council, passed final council vote March 2001.
Benefits
features corresponding advantages logic products assembled 56-ball MicroStar (VFBGA) package are:
Minimum footprint industry: Allows smallest board space among industry standard packages. Required trace width spacing capability well defined major manufacturers. MicroStar package VFBGA packages have vastly improved parasitic capacitance inductance, providing better high-speed performance. JEDEC standard package, under MO-225, meets worldwide mechanical pinout specifications. external components required, other than decoupling capacitors. Translates lower cost, lower maintenance, higher reliability. Improved thermal dissipation improves device reliability. Lower ground bounce provides more noise margin. Minimized skew pattern provides additional design margin high-speed buses. High board assembly yields, with documented defect levels PPM.
Evaluation Units
evaluation units, contact authorized distributors more information, refer http://www.ti.com/sc/msjunior
MicroStar Package Marking Packing
Marking
uses laser mark product number, year month manufactured, trace code, manufacturing site, pin-1 location. device marking example ALVCH16373 shown Figure
LOGO Part number: ALVCH16373 Year, Month, Code, Site location YMLLLS VH373
Figure Device Marking Example
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namerule 56-ball MicroStar package rule with characters maximum. Table shows namerule logic each marking derived. naming convention first note alphanumeric code under namerule This code under namerule condensed into codes under namerules remaining function numbers added place asterisks. example, mark LVC16244A VFBGA device, note that code under namerule SN74LVC16***. Namerule applies VFBGA, therefore, SN74LVC16 replaced code found under namerule remaining function numbers (244A) added onto LD244A. Table Name Markings Various MicroStar Package VFBGA Offerings
DEVICE NAME LVC16244A LVCH16245A ALVC16244A LVTH16245A CBT16211A NAMERULE SN74LVC16*** SN74LVCH162*** SN74ALVC162*** SN74LVTH162*** SN74CBT16*** NAMERULE LVC16*** LVCH162*** ALVC162*** LVTH162*** CBT16*** NAMERULE LD*** LN2*** VC2*** LL2*** CY*** MARKING LD244A LN245A VC244A LL245A CY211A
Tape Reel
Embossed-tape-and-reel feed preferred method automatic pick place machines. offers tape-and-reel packaging 56-ball MicroStar package. standard quantity 1000 units reel. Packaging materials used include carrier tape, cover tape, reel. materials used meet industry guidelines protection, comply fully with Standard 481-A, Taping Surface Mount Components Automatic Placement. dimensions interest end-user tape width (W), pocket pitch (P), quantity reel. Figure Table give tape dimensions 56-ball MicroStar package packing.
NOTE dimensions
Figure Tape Dimensions
16-Bit WidebusE Logic Families 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch (VFBGA) Packages
SZZA029B
Table Carrier Tape Dimensions
CARRIER TAPE WIDTH POCKET PITCH (P1) POCKET WIDTH (A0) POCKET LENGTH (B0) 7.30 POCKET DEPTH (K0) 1.50 HOLE-TOPOCKET CENTERLINE (P2) HOLE-TOPOCKET CENTERLINE 7.50 SPROCKET HOLE PITCH (P0) QUANTITY REEL 1000
16.00 8.00 4.80 dimensions millimeters.
Reel Diameter Reel Width Cover Tape Width
REEL WIDTH 16.4 +2.0/-0
REEL DIAMETER
NOTES: dimensions millimeters. Standard quantity 1000 devices reel; however, this subject change market demand.
Figure Reel Dimensions
Sockets Socket Ordering Information
Yamaichi Socket number: VFBGA-56 IC280-056-237 Yamaichi Electronics Inc. 2235 Zanker Road Jose, 95131 Tel: (408) 456-0797
16-Bit WidebusE Logic Families 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch (VFBGA) Packages
SZZA029B
Conclusion
This application report shows that 56-ball MicroStar package optimal solution addressing performance economic issues such
area savings over TSSOP Minimized skew reducing pin-to-pin inductance, thereby enabling support high-speed applications with greater bandwidth Improved thermal dissipation Improved board-mount assembly yields beneficial characteristics inherent processes.
spacing between balls this 0.65-mm VFBGA package equal that other 0.8-mm-pitch packages, therefore, defect rates solder bridging similar those larger pitch packages. simultaneous-switching data graphs clearly show this smaller package, with lower capacitance inductance, both speed noise advantages over SSOP, TSSOP, TVSOP packages. Designers using MicroStar (VFBGA) package take advantage win-win combination electrical physical properties offered. With introduction MicroStar package OEMs assured standardized JEDEC package, pinout, availability previously stated product families functions. More device families functions will included MicroStar package market interest dictates.
16-Bit WidebusE Logic Families 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch (VFBGA) Packages
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