74HC/HCT4515 4-to-16 line decoder/demultiplexer with input latches; in
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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4515 4-to-16 line decoder/demultiplexer with input latches; inverting
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
FEATURES Inverting outputs Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4515 high-speed Si-gate CMOS devices compatible with "4515" "4000B" series. They specified compliance with JEDEC standard
74HC/HCT4515
74HC/HCT4515 4-to-16 line decoders/demultiplexers having four binary weighted address inputs with latches, latch enable input (LE), active enable input (E). inverting outputs Q15) mutually exclusive active LOW. When HIGH, selected output determined data When goes LOW, last data present stored latches outputs remain stable. When LOW, selected output, determined contents latch, LOW. When HIGH, outputs HIGH. enable input does affect state latch. When "4515" used demultiplexer, data input address inputs.
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/ tPLH Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay input capacitance power dissipation capacitance package notes CONDITIONS UNIT
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
DESCRIPTION SYMBOL
74HC/HCT4515
NAME FUNCTION latch enable input (active HIGH) address inputs multiplexer outputs (active LOW) ground enable input (active LOW) positive supply voltage
4,18,
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC/HCT4515
APPLICATIONS Digital multiplexing Address decoding Hexadecimal/BCD decoding
Fig.4 Functional diagram.
FUNCTION TABLE INPUTS Notes HIGH HIGH voltage level voltage level don't care OUTPUTS
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
74HC/HCT4515
Fig.5 Logic diagram.
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay propagation delay output transition time typ. max. min. max. +125 min. max.
74HC/HCT4515
TEST CONDITIONS UNIT WAVEFORMS Fig.6
tPHL/ tPLH
Fig.6
tPHL/ tPLH
Fig.6
tTHL/ tTLH
Fig.6
latch enable pulse width HIGH set-up time hold time
Fig.7
Fig.7
Fig.7
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category:
74HC/HCT4515
Note types value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below. INPUT UNIT LOAD COEFFICIENT 0.65 1.40 1.00
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER min. typ. tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay propagation delay propagation delay output transition time latch enable pulse width HIGH set-up time hold time max. to+85 min. max. +125 min. max. Fig.6 Fig.6 Fig.6 Fig.6 Fig.7 Fig.7 Fig.7 UNIT WAVEFORMS TEST CONDITIONS
September 1993
Philips Semiconductors
Product specification
4-to-16 line decoder/demultiplexer with input latches; inverting
WAVEFORMS
74HC/HCT4515
50%; VCC. HCT:
Fig.6
Waveforms showing input (An, output (Qn) propagation delays output transition times.
shaded areas indicate when input permitted change predictable output performance. 50%; VCC. HCT:
Fig.7
Waveforms showing minimum pulse width latch enable input (LE) set-up hold times Set-up hold times shown positive values specified negative values.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
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