What maximum frequency NCP5331 operate without overheating, internal g

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What maximum frequency NCP5331 operate without overheating, internal g

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AND8152/D Using NCP5331 2-Phase Controller NVIDIA Video Card Applications (NV38)
What maximum frequency NCP5331 operate without overheating, internal gate driver power dissipation? ratio indicates good synchronous because will resist dv/dt turn-on switch node.
VGS, GATE-TO-SOURCE VOLTAGE
minimize cost area, assume
using upper lower FET. Both FETs DPAK package. This depends voltage, gate charge Vgs, number upper lower FETs used. Upper FET: Choose NTD60N02 because gate charge. VCCH then gate drive pins will approximately
Phase: V-5.0 Phase: V-3.3 VGS, GATE-TO-SOURCE
25°C TOTAL GATE CHARGE (nC)
Figure
Qgd/Qgs1 nC-5.0 nC)/3.0 3.6:1
What maximum power dissipation
25°C TOTAL GATE CHARGE (nC)
LQFP-32 package particular temperature? Tj_max 125°C Tpcb 80°C (this assumed temperature with minimal airflow) Rqja 52°C/W (from data sheet dated June 2003) (125°C-80°C)/(52°C/W) 0.865 maximum total power dissipation losses NCP5331: Losses Losses VCCH Losses VCCL1 VCCL2 V*22 V*6.4 2.0*12 V*5.0 0.461 quiescent currents losses available switching without overheating controller: 0.865 W-0.461 0.404
Figure Gate-to-Source Drain-to-Source Voltage Total Charge
10.3 12.9
Lower FET: Choose NTD110N02 because
RDSon ratio Qgd/Qgs1. gate drain charge Qgs1 pre-turn-on threshold gate source charge (see PCIM 2000 publication).
Semiconductor Components Industries, LLC, 2004
April, 2004 Rev.
Publication Order Number: AND8152/D
AND8152/D switching losses equate them
losses available switching: Upper losses Upper losses 2.0*Lower losses 10.3 nC*6.0 V*fsw 12.9 nC*7.7 V*fsw 2.0*10 V*46 nC*fsw 0.404 Solving results maximum switching frequency with these FETs. Select operating frequency less than this maximum kHz. should less this should conservative design. Also, choose nominal output voltage such design. Assume 2-phases must balanced maximize available power without violating current limitations pin. reference design from NVIDIA appears draw more current from phase than from phase. However, conversion from phase current will certainly less efficient than conversion from phase current. Using efficiency phase from phase will distribute currents account differences efficiency. Efficiencies: I_5.0 V/I_3.3 [80% [90% Currents: I_5.0 I_3.3 Solve first equation I_5.0 substitute into second equation: 1.34 I_3.3 I_3.3 then I_3.3 12.8 I_5.0 A-12.8 17.2 Calculate power dissipated upper mosfet. Losses upper mosfet will dominated switching losses and, depending RDSon duty-cycle, conduction losses. Neglect secondary losses upper lower mosfet output charge (Qoss) reverse recovery time (trr) lower mosfet. Igate gate driver output current NCP5331 Qswitch post gate threshold charge plus gate source charge 60N02
Check minimum pulse width with
minimum output voltage (0.8 maximum input voltage (13.2 maximum frequency (+20%): V/5.5 V/(1.2*225 kHz) 538.7 This much higher than worst case minimum pulse width specified NCP5331 data sheet. switching frequency were high then minimum pulse width would become very important. high switching frequency would result pulse skipping (voltage jitter) lowest settings and/or highest input voltages. What power being dissipated FETs?
Assume total output current from 2-phase
converter maximum. Based NVIDIA's choice FETS reference design continuous rating), actual current requirement
Phase Upper MosFET RDSon 60N02 Vgs, 125°C 14.9 DV/L (5.0 V-1.2 V)/875 (1.2 V/5.0 V)/225 4.63 peak-to-peak (APP) Irms 17.2 A2]1/2 [(1.2 V/5.0 295.8]1/2 8.42 Arms Irms2*RDSon Io_peak*tswitch*Vin*fsw Irms2*RDSon (Io_avg DIo/2) *(Qswitch/Igate)*Vin*fsw 8.422 Arms*14.9 (17.2 4.63 APP/2) *(6.5 nC/1.0 A)*5.0 V*225 1.06 0.14 1.20
Phase Upper MosFET RDSon 60N02 Vgs, 125°C 13.7 DV/L (3.3 V-1.2 V)/875 (1.2 V/3.3 V)/225 3.88 peak-to-peak (APP) Irms 12.8 A2]1/2 [(1.2 V/3.3 163.8]1/2 7.72 Arms Irms2*RDSon Io_peak*tswitch*Vin*fsw Irms2*RDSon (Io_avg DIo/2) *(Qswitch/Igate)*Vin*fsw 7.722 Arms*13.7 (12.8 3.88 APP/2) *(6.5 nC/1.0 A)*3.3 V*225 0.82 0.071 0.89
exact thermal solution left customer.
derive effective heatsink design, each application must consider airflow, mechanical requirements, case operating temperature goals, ambient operating temperatures, cost.
Calculate power dissipated lower mosfets.
Losses lower mosfets dominated conduction losses diode losses during non-overlap time.
AND8152/D
Phase Lower MosFET RDSon 110N02 Vgs, 125°C T_nonoverlap NCP5331 gate drivers diode voltage 110N02 0.78 Irms [(1.0-D) 17.2 A2]1/2 [(1.0-1.2 V/5.0 295.8]1/2 14.99 Arms Irms2*RDSon Vf*Io*t_nonoverlap*fsw 14.992 A*6.0 0.78 V*17.2 A*65 ns*225 1.35 0.196 1.55 Phase Lower MosFET RDSon 110N02 Vgs, 125°C T_nonoverlap NCP5331 gate drivers diode voltage 110N02 0.78 Irms [(1.0-D) 12.8 A2]1/2 [(1.0-1.2 V/3.3 163.8]1/2 10.2 Arms Irms2*RDSon Vf*Io*t_nonoverlap*fsw 10.22 A*6.0 0.78 V*12.8 A*65 ns*225 0.624 0.146 0.770
exact thermal solution left customer.
derive effective heatsink design, each application must consider airflow, mechanical requirements, case operating temperature goals, ambient operating temperatures, cost. Determine passive components around NCP5331. following requirements: Output voltage range: V-1.5 Maximum output current: Output Inductors nH-1.0 (use average), Switching frequency (fsw) (derived pages this paper) Voltage droop Adaptive Voltage Positioning (AVP) full-load shall No-Load offset voltage (AVP) above shall 0.2% setting First, determine value Rosc switching frequency using Figure from NCP5331 data sheet:
FREQUENCY (kHz) ROSC
Next, must choose value feedback resistor,
RFB. Before calculating value, must know feedback bias current. feedback bias current found from Figure from NCP5331 data sheet once value Rosc (42.2 known:
BIAS CURRENT,
Assume NV38 video card application
ROSC VALUE,
Rosc 42.2
Figure Current ROSC Value
Rosc 42.2 obtain
Figure Oscillator Frequency ROSC Value
typical multi-phase application, value determine No-Load voltage above setting. graphic card application, want minimal no-load deviation above (<0.2% setting). This will accomplished applying external bias current resistor (Rbias) from Reference output (pin (pin shown application schematic. value this bias resistor calculated with following equation: Rbias (Vref-DAC)/IFB (5.0 V-1.2 V)/7.5 506.6 (511 standard value) Adding this bias current allows more flexibility choosing value provides better transient response. Without bias current, would need very (<<1.0 minimize no-load setting. value desirable because load transients
AND8152/D
will demand more current from error amplifier maintain closed loop operation. low, error amplifier will current limit during output transients error amplifier will able maintain control node (i.e. error amplifier will open loop output voltage unregulated). value least recommended will choose this application. value Rbias optimized when (the nominal design point). other settings external bias current will change error output voltage. following table shows that this additional error less than 0.2% minimum maximum settings.
Table
Setting 0.80 1.20 1.50 Ext. Bias w/511 (mA) 8.21 7.43 6.85 Output Error w/RFB (mV) -1.40 +0.14 +1.30 Percent Error 0.175% 0.012% 0.087%
Determine Error Amplifier Compensation
components: good compensation scheme must provide robust stability acceptable transient response. following graphs demonstrate stability documenting transient response bode plot. transient response shows instability ringing. bode plot indicates system will have bandwidth, degrees phase margin, least gain margin.
4.02
Current
10e6
ZERO droop full-load, "droop resistor"
from VDRP must unpopulated.
vdbo vpho
Figure NCP5331 Error Amplifier Compensation
50.0
(dB)
30.0 Gain Phase vdbo db(volts)
vpho degrees
10.0
PHASE (deg)
-10.0
6.45KHz
-30.0 90.0
295KHz
100k
1Meg
10Meg
frequency hertz
Figure Error Amplifier Gain Phase Plots
AND8152/D
PHASE (deg)
GAIN (dB)
Figure System Bode Plot
vcore
i(i1)
80.0
1.30
Vcore
60.0 Transient Response i(i1) amperes
1.20
vcore volts
40.0
1.10
20.0
1.00 Iout
900m
6.00m
6.10m
6.20m time seconds
6.30m
6.40m
Figure System Transient Response: Steps from Back
AND8152/D
Determine current sense components predict current distribution. output inductor specified between 1000 will median value these calculations. Also, series resistance output inductor (RL) specified NV38 reference design uses current balance resistors Intersil ISL6569 controller. This forces phase operating from conduct more current then phase operating from will ratio derived previously that considers input/output conversion efficiencies: 17.2 A/12.8 1.34. this application, want accurately balance phase currents full load according specific ratio. This could accomplished methods. method, resistor divider could used current sense input reduce "gain" that phase which would force more current into that phase. However, external current signals usually very magnitude (typically less than full load) reduction small signals invites noise problems recommended. better method steer currents increase signal (external ramp) phase shorten pulse width reduce current that phase. This method that will used here. Also, accuracy current balance improved increasing external ramp both phases using slightly faster time constant than what normally selected. Typically, recommend choosing current sense components according L/RL. this application, will choose L/RL/3 improve accuracy. drawback choosing faster current sense time constant that transient response will optimal but, luckily, graphics processor does demand same level transient response today's Pentium processors. There components ramp that must considered: external ramp plus offset sensed across output inductor fixed internal ramp controller required duty-cycle. comparator, internal external signals combined according [I_avg G*DIL/2]*RL*GCSA mV*(Vo/Vi) COMP COMP steady state voltage from error amplifier. I_avg average output current phase. peak-to-peak current output inductor. resistance inductor (plus resistance from PCB). magnitude NCP5331's internal ramp 100% duty-cycle. GCSA gain current sense amps (specified NCP5331 data sheet). gain" external current sense ramp sense components equal L/RL). Substitute values previously derived this report obtain: [17.2 4.63 APP/2] (1.2 V/5.0 COMP, phase. [12.8 3.88 APP/2] (1.2 V/3.3 COMP, phase. must equations equal each other solve G3V. best accuracy (see above), increase magnitude external ramp setting produce three times normal external ramp) solve G5V. 90.3 G5V*12.2 97.8 90.9 solving results 38.4 mV/12.2 3.15 time constant output inductors L/RL nH/2.5mW current sense phase needs time constant ms/3 116.7 R3.3VC 116.7 choose 0.01 then R3.3V 11.7 (11.8 standard value) current sense phase needs time constant ms/3.15 111.1 R5VC 111.1 choose 0.01 then 11.1 (11.0 standard value) ICAPs (Spice based) simulation 2-phase DC/DC converter with previously derived current sense components performed investigate current distribution between phases Vout load. output currents from phases match predicted values within full load shown following graph. output voltage ripple less than mVpp this simulation.
AND8152/D
i_3v i_5v
23.0
Output Current: 17.1Arms
SIMULATION RESULT Io=30A, Vo=1.2V Lo=875nH, ESR=2.5m CS_5V: 0.01uF, 11.0K CS_3.3V: 0.01uF, 11.8K
Output Currents Io=30A i_3v, i_5v amperes
19.0 15.0
11.0
7.00
3.3V Output Current: 12.9Arms
6.172m
6.176m
6.180m time seconds
6.184m
6.188m
Figure
vcore
1.208
RIPPLE 3.8mVpp
1.204
Voltage Ripple vcore volts
1.200
1.196
1.192
6.746m
6.750m
6.754m time seconds
6.758m
6.762m
Figure
AND8152/D Many factors effect current sharing: layout,
inductor saturation, inductor ESR, current sense component tolerances, resistances. Final current sharing should carefully examined fine tuned adequate sample PCBs. phase consistently conducts more less) current than desired then current sensing components modified produce correct level current. general, reducing current sense resistor (increasing external ramp) phase will reduce current that phase. Similarly, increasing current sense resistor phase will increase current that phase. Finally, must over current shutdown threshold. power section design performed continuous. Considering current ripple, gain tolerances, inductor change temperature rise choose over current shutdown threshold
V_REF RLIM1 7.87 ILIM RLIM2 3.92
Figure
What current that input capacitors must support? many input capacitors does each phase need?
Assume input current components:
negative average current when upper (Iavg) peak positive current equal converter's maximum output current when upper Compute these currents. Assume converter's efficiency full load will from phase from phase.
Phase Iavg Iout D/Efficiency 12.8 (1.2 V/3.3 V)/0.90 5.17 Irms [Iout2 D]1/2 [Iavg2 (1-D)]1/2 12.82 (1.2 V/3.3 V)]1/2 [5.172 (1.0-1.2 V/3.3 V)]1/2 7.71 Arms 4.12 Arms 11.83 Arms
ILIM (Io_DC Imax_AC/2) G_ILIM 4.63 APP/2) 1.65 voltage divider from VREF ILIM must produce this value. This easily done shown:
Phase Iavg Iout D/Efficiency 17.2 (1.2 V/5.0 V)/0.80 5.16 Irms [Iout2 D]1/2 [Iavg2 (1-D)]1/2 17.22 (1.2 V/5.0 V)]1/2 [5.162 (1.0-1.2 V/5.0 V)]1/2 8.42 Arms 4.49 Arms 12.91 Arms
capacitors used inputs must
support 12.91 Arms 11.83 Arms over entire expected temperature range. Sanyo Oscon series capacitors excellent choice this application because they offer highest ripple ratings smallest packages. Oscons input capacitors will much less expensive then ceramics shown NVIDIA's reference design. very important understand interaction between input currents. full load, phase will conduct more current then phase both phases will sourcing current. However, light loading no-load operation both phases will sourcing current. converter loading less than A-7.0 then phase will conduct virtually load current phase will probably sinking current. current load power supply, other components system, extremely (less than then "negative" current being delivered phase will charge input capacitors.
this reason, recommended that input capacitors phase rated schottky diode shown schematic protects input capacitors clamping voltage approximately Also, testing purposes necessary temporarily populate load supply shown Application schematic power supply shut down because overvoltage negative currents from phase. thru-hole capacitor acceptable then Sanyo's series used: Phase: 6SP680M (680 4.84 Arms, 10.0 11.5 mm). This phase requires 12.91 Arms/ 4.84 Arms 2.67 capacitors input conservative design. Phase: 6SP680M (680 4.84 Arms, 10.0 11.5 mm). This phase requires 11.83 Arms/ 4.84 Arms 2.44 capacitors input conservative design.
AND8152/D surface mount capacitor acceptable then Sanyo's
series used: Phase: 6SVP820M (820 5.44 Arms, 10.0 12.7 mm). This phase requires 12.91 Arms/ 5.44 Arms 2.37 capacitors input conservative design. Phase: 6SVP820M (820 5.44 Arms, 10.0 12.7 mm). This phase requires 11.83 Arms/ 5.44 Arms 2.17 capacitors input conservative design. Place components associated with Error Amplifier minimize trace lengths pins VFB, VDRP, COMP. Place current sense components near CS1, CS2, CSREF pins. Place frequency setting resistor (Rosc) close possible ROSC pin. CSREF trace should routed independently remote output voltage sensing trace that connects NVVDD should used CSREF connection. bypass capacitor should placed very close VREF (#8). snubbers used, they should placed very close lower MosFETs. bypass capacitor should placed very close each upper MosFETs. signal ground (LGND) should only connect ground plane point. LGND connections (shown schematic) should single point "star" connection LGND shown below.
This design done converter with
continuous output. actual output current lower then number output capacitors reduced. Layout Considerations Place ceramic power supply bypass capacitors close their associated pins: VCCL, VCCH, VCCL1. Place MosFETs minimize length gate traces.
SIGNAL (LGND)
RLIM2 CPGD CVCC
RGND
LGND
CONNECTS PLANE POINT
NCP5331
CFFB
CREF
ROSC
Figure
AND8152/D
CSREF connection must placed between output inductors current sharing will accurate. resistance from CSREF each output inductor should equal. This easily accomplished output copper symmetrical around CSREF sense point shown below.
MOSFETS SWNODE2
MOSFETS SWNODE2
SWNODE1
SWNODE1
INDUCTOR1
INDUCTOR2
INDUCTOR1
INDUCTOR2
RPCB1 CSREF CONNECTION POINT
RPCB2
RPCB1 RPCB2
CSREF CONNECTION POINT
RPCB1 RPCB2
RPCB1 RPCB2
CORRECT LAYOUT RPCB1 RPCB2 Phases will share current correctly.
INCORRECT LAYOUT RPCB1 RPCB2 Phase current will higher than expected.
Figure
Test Results NCP5331 demo board AMD's Hammer processor modified operate simultaneously from output inductors were modified produce input capacitors were changed Oscons (three phase) Error Amplifier compensation changed values shown Page this report. output capacitors were changed single Oscon, ceramics, ceramics. current sharing, efficiency, startup results shown below.
Table Input Currents, Input Voltages, Efficiencies
Vout 1.22 1.22 1.22 1.22 1.22 1.22 Iout 5.00 10.00 15.00 20.00 25.00 30.00 5.07 5.04 5.02 5.00 4.98 4.95 I_5.0 1.48 2.31 3.09 3.88 4.66 5.49
Table Output Current Sharing Load
Iout I_5.0 Vout 2.21 8.53 13.6 18.2 I_3.3 Vout -2.48 1.40 6.48 11.3
3.34 3.33 3.32 3.31 3.29 3.28
I_3.3 0.24 0.52 1.48 2.58 3.72 4.98
P_in 8.29 13.37 20.39 27.90 35.40 43.49
P_out 6.11 12.22 18.33 24.44 30.55 36.66
73.73 91.37 89.92 87.61 86.30 84.30
AND8152/D
mV/DIV): Output Voltage (bottom trace) (5.0 A/DIV): Output Current Load (top trace) Note measured average 11.32 V/DIV): SWNODE Phase (middle trace)
Figure Output Current Loading
mV/DIV): Output Voltage (bottom trace) (5.0 A/DIV): Output Current Load (top trace) Note measured average 18.2 (2.0 V/DIV): SWNODE Phase (middle trace)
Figure Output Current Loading
AND8152/D
(5.0 A/DIV): Input Current (top trace) (5.0 A/DIV): Input Current (2nd trace) (0.5 V/DIV): Output Voltage (3rd trace) (5.0 V/DIV): POWERGOOD (bottom trace)
Figure Startup Loading
NV_PHASE1_IN 10/1 Cin3 6SP680M Cin1 6SP680M Cin2 6SP680M
TESTING PURPOSES ONLY
MBRA120LT3
10/1
V_EXT NV_PHASE2_IN RPGD Cin6 6SP680M Cin4 6SP680M Cin5 6SP680M
Iout Vout Tpgd
NV_PGOOD
CVCC NV_PHASE1_IN CPGD
NVVDD_EN
ENABLE NVVDD
MC74VHC1G135
NTD60N02
NVVDD
SWN_3.0 NTD11N02 CBout VCCH GND2 -SEN VID1 VID2 VID3 VID4 ROSC VID0 NTD60N02 NV_PHASE2_IN 4700
REMOTE SENSE
ILIM 5VSB Cpgd VCCL VDRP LGND CSREF VFFB 5VREF GND1 RBIAS 3.74 7.87 CREF RBIAS2 ROSC 42.2 CFFB 0.01 RLIM1 COMP Covc VCCL1
4.02
NVVDD_SENSE
mF/4.0
AND8152/D
Figure NCP5331 Schematic NV38 GPU: V-1.5
NCP5331
RLIM2 3.92
OVER CURRENT
0.01 CONNECT BETWEEN OUTPUT INDUCTORS
NVVDD_GND_SENSE
NVVDD
OPEN
SWN_5.0 NTD11N02 4700
OPEN
LOCAL SENSE
LGND TIES PGND POINT
RGND
OPEN
11.8
0.01
OPEN
NV_VID0 NV_VID1 NV_VID2 NV_VID3 NV_VID4
RVID0
AND8152/D
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AND8152/D

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