INTRODUCTION Power converters using secondary side controllers provide

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INTRODUCTION Power converters using secondary side controllers provide

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AND8119/D Design Isolated Bias Supply Telecom Systems Using NCP1030
INTRODUCTION Power converters using secondary side controllers provide better transient response, higher efficiency usually require less components than their primary side referenced counterparts. However, secondary side controllers require primary side referenced bias supply start operation. After start-up, controller power provided from secondary side. NCP1030 incorporates single active power, control logic protection circuitry required implementing, with minimum external components, highly integrated isolated bias supply. features included NCP1030 result footprint area reduction compared solution implemented using discrete components. NCP1030 Power Switch Circuit rated making ideal Telecom automotive applications. addition, this operate from existing supply. NCP1030 includes extensive features including: Board Power Switch: Eliminates need external switch. Power Switch characteristics well known gate drive tailored control switching transitions help reduce electromagnetic interference (EMI). Internal Start-up Regulator: Provides power NCP1030 during start-up. After start-up, regulator disabled, thus reducing power consumption. regulator powered directly from input line. Internal Error Amplifier: Allows implementation isolated supply using primary side regulation without need optocoupler. Internal Cycle Cycle Current Limit: Eliminates need external sensing components. programmed current limit
Proprietary Active Leading Edge Blanking (LEB)
Circuit: Provides better current limit control compared fixed blanking period. active circuit masks current signal during Power Switch turn transition. Individual Line Undervoltage Overvoltage (UV/OV) Detectors with Hysteresis: Eliminate need external supervisory function. UV/OV detectors disabled needed. Single Capacitor Oscillator: Eliminates traditional timing resistor. Oscillator optimized operation MHz. Internal Voltage Reference: Eliminates need external bypass capacitor. Thermal Shutdown Circuit: Protects device event maximum junction temperature exceeded. DESIGN SPECIFICATIONS isolated bias supply telecom system designed implemented using NCP1030. supply delivers converter specifications listed Table
Table Bias Supply Specifications
Parameter Input Voltage Frequency Peak Efficiency Output Voltage Output Current Output Power Vout Iout Pout Symbol 10.8 0.017 13.2 0.17
Flyback topology operating discontinuous mode selected because simplicity part count.
Semiconductor Components Industries, LLC, 2003
July, 2003 Rev.
Publication Order Number: AND8119/D
AND8119/D
FLYBACK CONVERTER dual output Flyback converter shown Figure OUTPUT regulated means OUTPUT providing isolated OUTPUT without need optocoupler.
where, forward voltage drop across RDS(on) Power Switch resistance. Equation relates on-time volt-second product reset volt-second product adds dead time insure converter operates discontinuous mode. Solving Equation assuming drop across
(0.4 (0.8 0.4)
(eq.
Cout
Vout (OUTPUT1)
Snubber
(OUTPUT2)
Controller
turns ratio greater than 2.58 required. turns ratio 2.78 selected. maximum stress voltage across primary switch during turn period calculated using Equation
Vstress Vin(max) (Vout VfD1) (eq.
Current flows primary side when Power Switch, transformer primary side becomes positive with respect non-dot end. While Power Switch energy stored transformer reverse biased. When turns OFF, transformer winding polarities reversed, forward biasing Energy transferred secondary outputs during this period. secondary current decays zero before switch turns again, converter operates discontinuous mode. Otherwise, operates continuous mode. converter regulates output sampling output voltage comparing reference voltage. signal proportional their difference generated used adjust time such that voltage difference reduced. Snubber limits voltage across Power Switch helps reduce noise. DESIGN PROCEDURE converter designed operate maximum duty cycle (DC) primary peak current (IPPK) required primary inductance, calculated using Equation
in(min) IPPK
(eq.
Solving Equation primary inductance required. transformer turns ratio using Equation
(Vin (IPPK RDS(on))) (Vout VfD1) (0.8
(eq.
Figure Isolated Flyback Converter
VREF
voltage significantly below maximum rating NCP1030 internal Power Switch. transformer winding arrangement includes split primary with bifilar secondaries. transformer ordered from Coilcraft under part number B0226-E. Table summarizes specifications transformer.
Table Transformer Specifications
Parameter Magnetizing Inductance Leakage Inductance Resistance Terminals 1,2-3,4 1,2-3,4 0.955 0.655 0.82 0.248 0.248
Resonant Frequency
(typ.)
MAIN OUTPUT main factors, voltage ripple frequency compensation, considered selection output capacitor, Cout. This section will focus voltage ripple, while frequency compensation covered latter section. output capacitor provides load current during switch time. target voltage droop known, Cout calculated using Equation
Cout Iout Vdroop
(eq.
calculated
Solving Equation maximum voltage droop requires capacitor. However, Cout increased facilitate frequency compensation. secondary peak current, ISPK, diode blocking voltage, Vblock, determine selection rectification diodes, primary peak current transformer turns ratio determine secondary peak current given Equation
ISPK IPPK
(eq.
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AND8119/D
voltage across rectification diode given Equation
Vblock Vout Vin(max)
(eq.
Cout
Rout Vout
RESR Cout(eq) Controller
Solving Equations rectification diode needs handle 1.11 39.34 addition voltage calculated using equation voltage spikes during switching transitions need considered when selecting blocking voltage rating. Schottky diode selected reduce forward voltage drop, thus reducing power dissipation. Semiconductor's MBRA160 selected meets requirements. AUXILIARY SUPPLY REGULATOR auxiliary supply (OUTPUT provides means regulate main output (OUTPUT addition, auxiliary winding disables internal start-up circuit provides power NCP1030 after initial power same turns ratio rectification diode used main output used auxiliary winding improve voltage tracking between outputs. auxiliary winding capacitor, CCC, selected such that voltage greater than maintained while output reaches regulation. time output reaches regulation measured Once start-up time known, calculated using Equation
(eq.
Rout(eq)
Rbias
VREF
NCP1030
Figure Flyback Converters
open loop frequency response system (from approximated modulator gain output network frequency response. Additional high frequency components present considered analysis they beyond crossover frequency. modulator gain, GMOD, approximated Equation
GMOD Rout(eq)
(eq.
where, includes NCP1030 bias current (ICC3) additional current supplied CCC. Assuming ICC3 bias current feedback sensing resistors, calculated capacitor Please note that increased match Cout, transient response converter will suffer. This because capacitance current ratio auxiliary winding significantly greater then output winding, taking longer follow Cout during transient condition. FEEDBACK LOOP feedback loop stable, converter will oscillate. insure loop stable, open loop frequency response needs cross slope dB/dec, with phase margin above under line load conditions. This accomplished shaping loop response using internal error amplifier (EA). block diagram shown Figure used evaluate converter open loop response.
output network block comprised Cout, RESR Rout. frequency response output network given Equation
H(f) sRESRCout(eq) sCout(eq) (RESR Rout(eq))
(eq.
total open loop frequency response product Equations Please note that Cout(eq) includes Cout reflected auxiliary winding transformer turns ratio. same turns ratio used both auxiliary output windings, Cout adds directly CCC. output network zero pole they given Equations respectively.
Cout RESR Rout Cout
(eq. (eq.
modulator gain response depends Vin. extreme conditions, both minimum Rout input voltage (GMOD1) well both maximum Rout input voltage (GMOD2) considered frequency compensation. order facilitate frequency compensation, Cout increased simulated open loop frequency responses GMOD1 GMOD2 shown Figures respectively.
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AND8119/D
Magnitude (dB) Frequency (Hz) Magnitude Phase Angle (degrees) -100
poles, fp2, origin. frequency remaining pole zero given Equations respectively.
2pR7C2
(eq.
2pR7C2C6
(eq.
Figure Open Loop Frequency Response GMOD1
Magnitude (dB) Frequency (Hz) Magnitude Phase Angle (degrees) -100
poles zero locations selected achieve desired crossover frequency, fCO. system crossover frequency selected GMOD1. modulator gain depends input voltage, higher obtained maximum input voltage condition with equivalent output load. selection compensation components begins noting that voltage should equal (VREF) when output regulation feedback sensing resistor network bias current (Ibias1) known, calculated using Equations respectively.
Ibias1 Ibias1
(eq.
(eq.
Figure Open Loop Frequency Response GMOD2
Using bias current calculated 4.99 1.30 respectively. Resistor provides test point measure open loop frequency response. avoid disrupting bias point. error amplifier gain, GEA, calculated using Equation 6.03 achieve gain GMOD1.
(eq.
frequency compensation achieved using type error amplifier (EA) shown Figure
Input Ibias1
error amplifier zero, fz2, placed before system response crosses Pole, fp3, placed after attenuate high frequency components. Table summarizes system gain, poles zeros. Figure shows frequency response.
Table System Gain, Poles Zeros
Rbias
(R5)
VREF
Figure Type Error Amplifier
type error amplifier poles zero. transfer function given Equation
H(f) sR7C2 sR4(C2
7)C6
Output
Parameter GMOD1) GMOD2) (eq.
Frequency (kHz) 0.091 0.009 23.9 77.4 0.482
Magnitude (dB) 6.03
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AND8119/D
Magnitude (dB) Frequency (Hz) Magnitude Phase -100 Angle (degrees)
UNDER/OVERVOLTAGE DETECTORS NCP1030 eliminates need additional supervisory circuitry incorporating individual under overvoltage detectors with hysteresis. controller enabled voltage above voltage below UV/OV detectors biased using external resistor divider shown Figure
Ibias2
Figure Error Amplifier Frequency Response
phase contributions zero pole crossover frequency given Equations respectively.
(eq.
Figure UV/OV Resistor Bias Network
(eq.
resistor network bias current, Ibias2, known, thresholds equal, calculated using Equations respectively.
Vin(max) Ibias2
(eq.
phase margin, evaluated taking into account phase contribution poles zeros shown below Equation
qM°+ (eq. 180° 89.5° 22.7 7.33° 87.24° 72.4°
(eq. Vin(min) Vin(min)Vin(max) VOV(DVin Vin(min)
calculated phase margin 72.4°. 180° term arises because inverting configuration. simulated system frequency responses GMOD1 GMOD2 shown Figure
Magnitude (dB)
Phase (Vin 76V, Rout 720W) Magnitude (Vin 36V, Rout 72W) Magnitude (Vin 76V, Rout 720W) Phase (Vin 36V, Rout 72W)
DVin Vin(min)
(eq.
-100 Angle (degrees) -110 -120 -130 -140 -150 -160 -170 -180
Using bias current turn voltage turn voltage threshold 2.55 calculated approximately 45.3 respectively. Capacitors help reduce noise provide stable voltage during turn turn transitions. They OSCILLATOR FREQUENCY oscillator frequency obtained with timing capacitor (CT) tolerance SNUBBER snubber shown Figure added help reduce noise. snubber returned positive supply rail reduce voltage stress Vin. returned negative supply rail, voltage stress 2Vin.
Frequency (Hz)
Figure System Frequency Response
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AND8119/D
MAGNITUDE (dB) Filter Output Impedance Converter Input Impedance
Figure Snubber
FREQUENCY (Hz)
power dissipation determined given equation
Vin2
(eq.
Figure Filter Output Impedance Approximated Converter Input Impedance
snubber components assembled converter. However, electrical connections provided user wants snubber components. INPUT FILTER filter converter input used reduce EMI. input filter reduces noise provides solid input voltage converter. filter shown Figure Capacitor used common mode noise reduction.
0.022
LAYOUT CONSIDERATIONS Switching regulators noisy! However, with careful layout, noise reduced. things remember are: Keep switching elements high current traces away from controller sensitive nodes. Keep trace lengths minimum, especially important high current paths timing components. wide traces high current paths. Place bypass capacitors close components. ground plane possible single point ground system. bias supply built using single layer FR4, board. board size complete circuit schematic shown Figure actual size picture board shown Figure Bill Material listed Table
MURA110T3 35-76V 0.022 1:2.78 MBRA160T3 MBRA160T3
Figure Input Filter Schematic
Oscillation occur converter input impedance, Zin, lower than filter output impedance[1]. converter input impedance approximated negative resistor using Equation
Zin(dB Ohm) Vout Iout
(eq.
converter closed loop input impedance ultimately determined converter feedback loop well open loop input impedance. However, resistor good approximation will used analysis. Figure shows theoretical input filter output impedance approximated converter input impedance.
680p
NCP1030 VDRAIN COMP
4k99 45k3 0.01 1k30
680p 0.033
0.01
Figure Complete Circuit Schematic
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AND8119/D
Figure Demonstration Board (Actual Size)
Table Bill Materials
J1-J4 Value 0.033 0.01 0.022 45.3 4.99 1.30 Vendor Vishay Vishay Vishay Vishay Semiconductor Semiconductor Mill-Max Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Vishay Coilcraft Semiconductor Part Number VJ0805A681JXA VJ0805Y333KXXA C4532X5R1E226M C4532X7R1H225M C4532X7R2A225M VJ0805A681JXA VJ0805Y103KXXAT C1608C0G2E101J C2012X7RE223K MBRA160T3 MURA110T3 Terminal IMC-1210 CRCW08051004F CRCW08054532F CRCW08053402F CRCW08054991F CRCW08051301F CRCW080510R0F CRCW08051002F CRCW0805000ZJ CRCW12104990F B0226-E NCP1030DR2
DESIGN VERIFICATION final step design includes validation test bias supply. Before powering supply, should inspected potential problems. suggestions include: Verify connections. Check shorts opens, especially input output terminals. Verify component values. Slowly increase input voltage while monitoring input current. input current exceeds repeat steps Once input voltage reaches measure voltage critical nodes. NCP1030 start-up regulator should voltages correct, remove power repeat steps Increase input voltage Measure output voltage. approximately repeat steps Increase input voltage above output should turn OFF. Please careful when probing testing converter. High voltage present. Exercise CAUTION! Once converter functionality verified, board performance evaluated compared original goals. evaluation criteria includes: Open loop frequency response. Efficiency. Line load regulation. Step load response. Start-up response. open loop response measured injecting signal across using network analyzer shown Figure
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AND8119/D
Line load regulation Equations respectively.
DVout RegLINE DVin RegLOAD
Network Analyzer
calculated
using
(eq.
Converter
Error Amplifier
Vout(No Load) Vout(Full Load) Vout(No Load)
(eq.
Rbias
Line regulation measured below 0.5% load regulation measured below Figure shows output voltage variation output current under several input voltage conditions.
12.0
measured frequency response shown Figure crossover frequency measured kHz.
Magnitude (dB) Frequency (Hz) Rout
Vout, Output Voltage
Figure Open Loop Frequency Response Measurement Set-up
11.9 11.8 11.7 11.6 11.5 11.4 11.3 11.2
11.1 11.0 Iout, OUTPUT CURRENT (mA)
Figure Output Voltage Output Current
dynamic response converter evaluated stepping load current from from Iout(max). step load transient responses shown Figures
Iout, Output Current mA/DIV)
Figure Open Loop Frequency Response
Peak efficiency measured 83%. Figure shows efficiency output current under several input voltage conditions.
Efficiency Iout, OUTPUT CURRENT (mA)
Iout Vout 11.6
Vout, Output Voltage mV/DIV)
ms/DIV
Figure Output Voltage Response Step Load from
Figure Efficiency Output Current
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AND8119/D
Iout, Output Current mA/DIV) Iout Vout, Output Voltage (2.0 V/DIV) Operation OUTPUT2 Iout
Finally, converter turn response full load evaluated. Figure shows output turn transient response full load.
Vout, Output Voltage mV/DIV)
Vout 11.45 ms/DIV
OUTPUT1 (Isolated)
Figure Output Voltage Response Step Load from
ms/DIV
Output voltage ripple measured output current significantly below target. output voltage ripple waveform shown Figure
Vout, Output Voltage mV/DIV) Iout
Figure Output Voltage During Turn Full Load
Output operates while converter disabled. Once converter enabled, Output tracks Output SUMMARY isolated bias supply telecom system implemented using NCP1030. converter achieves peak efficiency while providing good transient response. REFERENCES Ridley, Ray. "The Evolution Power Electronics'', Switching Power Magazine, Fall 2001:16-30. Pressman, Abraham Switching Power Supply Design. York, MacGraw Hill.
Vout 11.33
ms/DIV
Figure Output Voltage Ripple
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AND8119/D
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INTRODUCTION Power converters using secondary side controllers provide

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