Introduction Quasi-square wave resonant converters, also known quasi-r

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Introduction Quasi-square wave resonant converters, also known quasi-r

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AND8145/D Power Supply Operating Quasi-square Wave Resonant Mode using NCP1207 Controller
Introduction Quasi-square wave resonant converters, also known quasi-resonant (QR) converters, allow designing flyback Switch-Mode Power Supplies (SMPS) with reduced Electro-Magnetic Interference (EMI) signature improved efficiency. level generated noise, SMPS therefore very well suited applications dealing with signals, such TVs. Semiconductor NCP1207 controller that will ease your design EMI-friendly power supply with only additional components, able lower standby power down
What Quasi-Resonance?
CTOT
term quasi-resonance normally related association real hard-switching converter resonant tank. While operation terms control similar that standard controller, additional network added shape variables around MOSFET: current voltage. Depending operating mode, becomes possible either switch zero current (ZCS) zero voltage (ZVS). Compared conventional converter, operation offers less switching losses current circulating through MOSFET increases forces higher conduction losses; with careful design, efficiency improved. However, main advantages favor quasi-resonance reduced spectrum content either conducted radiated. True quasi-resonance means that voltage present switch looks like sinusoidal arch. Figure shows such signal could look like.
Figure Truly Resonating Signal Quasi-resonant Flyback Converter
main problem with this technique lies very high voltage generated switch opening. Most time, these resonant offline designs require around BVdss MOSFETs whose price clearly incompatible with high volume markets. result, designers orientate their choice toward another compromise called quasi-square wave resonant power supply.
Quasi-Square Wave Resonant Converters
saw, true resonant operation constraint MOSFET selection imposing high voltage switch opening. closely look standard hard-switching waveform (Figure that given time drain voltage goes minimum. This occurs just after core reset.
Semiconductor Components Industries, LLC, 2004
March, 2004 Rev.
Publication Order Number: AND8145/D
AND8145/D
LLEAK CTOT
CORE RESET
DRAIN VOLTAGE
MINIMUM
CTOT
DRAIN CURRENT
Figure Hard-switching Waveforms Discontinuous Conduction Mode (DCM)
From Figure possible imagine controller that turns MOSFET until current grows-up setpoint. Then turns MOSFET until core reset detected (usually auxiliary winding). result, controller does include stand alone clock only detects presence events conditioned load/line conditions: this so-called free-running operation. Converters based this technique often designated Self-Oscillating Power Supplies (SOPS), valley switching converters, etc. Oscillations origins seen from Figure arrangement where networks appear.
Depending event, different configurations seen: switch closing, primary current flows through primary inductance also leakage inductance, LLEAK. When turn-on time expires, energy stored transferred secondary side transformer coupling flux. However, leakage inductance, which models coupling between both transformer sides, reverses voltage imposes quickly rising drain voltage. slope this current
CTOT (eq.
where CTOT gathers capacitors
VOUT
surrounding drain node: MOSFET capacitors, primary transformer parasitic capacitors also those reflected from secondary side, etc. result, LLEAK together with CTOT form resonating network natural frequency
LLEAK CTOT (eq.
LLEAK
maximum drain voltage then computed using characteristic impedance this network:
(VOUT LLEAK CTOT
(eq.
CTOT
Figure Typical Flyback Arrangement Shows Different Resonating Networks
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AND8145/D When transformer core resets, primary secondary
currents drop zero. secondary diode stops conduction reflected voltage primary naturally dies out. From equation this means that terms after collapse zero tends toward VIN. However, transition would brutal lack resonating network, this time made primary inductance, nearly same CTOT before. sinusoidal ringing takes place, damped presence ohmic losses resistance primary winding, modeled RP). drain-source shape rings formula below details:
VDS(t) (VOUT *a@t FPRIM
(eq.
with:
damping factor (eq. FPRIM FPRIM CTOT (eq.
VDS(t)
natural ringing frequency input voltage, diode's forward drop
turn ratio.
tvalley -100 Multiple Valleys
from Figure that drain seat various local minimums when going along ringing wave. These drops called "valleys". manage switch MOSFET right middle these valleys, ensure minimum turn-on losses, particularly those related capacitive dissipation:
PavgCAP CTOT VDS2 (eq.
Figure Typical Flyback Ringing Waveform Occurring Switch Opening
Thus, quasi-square wave operation valley switching) will imply re-activation switch when minimum. various figures portray, this occurs some time further transformer core reset. implementing this method, build converter that naturally exhibits variable frequency operation since reset time depends upon input/output operating conditions. Figure shows typical shot quasi-square wave converter. see, total period made different events, where core first magnetized (TON), then fully reset (TOFF) finally time delay (TW) inserted reach lowest value drain. look frequency moves respect input/output conditions.
TOFF
First Valley
Figure Typical Drain-Source Shot Quasi-square Wave Converter
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Evaluating Free-Running Switching Frequency
event, which fourth natural ringing frequency given equation will compute derivative equation null find minimum:
(VIN *a@t FPRIM
(eq.
IPEAK
S+N@
IP(t)
VOUT
Which gives result
2@p@FPRIM FPRIM
(eq.
Figure Primary Inductance Current made Different Slopes
However, this result very practical because inherent complexity. observe equation that minimum reached when term FPRIM equals Otherwise stated, solve which cosine equal zero, full product equals This gives:
FPRIM
(eq.
free-running frequency evaluated looking Figure where primary current (circulating primary inductance) depicted. From definition various slopes, express first events, TOFF quite easily:
(eq.
However, this result valid only damping coefficient, that say, *a@t Experience shows that good enough vast majority cases.
TOFF
(eq.
result, final switching period computed summing these sequences introducing input power expression: TOFF (eq.
TOFF
(eq.
(eq.
with: VREFLECT [VOUT
from equation
POUT
(eq. 16).
Now, plugging equation gives:
VREFLECT POUT
(eq.
converter efficiency POUT output power VOUT respectively output voltage rectifier drop IOUT primary inductance.
Stating that: POUT
VREFLECT VREFLECT VREFLECT VREFLECT VREFLECT (eq.
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From equation then compute switching frequency using calculated peak current:
POUT
(eq.
POUT
VOUT)VF )VIN VIN@ VOUT)VF
(eq.
However, equation very practical since involves what actually looking for. certainly used discover operating peak current from known inductance capacitor values. neglecting simpler formula used first frequency iteration (e.g. feed SPICE simulator instance):
POUT REFLECT VREFLECT 7*104 6*104 5*104 (Hz) 4*104 3*104 POUT VOUT NP:NS 1:10 (eq.
Entering equation into spreadsheet plotting versus various parameters (VOUT, IOUT, etc.) gives idea about high frequency variability system. Figure Figure respectively plot function input voltage output current given application.
2*105 VOUT NP:NS 1:10
1.5*105 (Hz)
1*105
5*104 2*104 1*104
POUT
Figure Frequency Variations SMPS Operated from Universal Mains
Figure Frequency Dependency with Load Given Input Voltage (100
VOUT NP:NS 1:10 POUT
Figure Peak Current Variations Output Power with Different Line Voltages
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Quiet Signature
Manipulating sinusoidal close-to) variables always offer narrower spectrum content compared hard-switching systems. Figure Figure depict conducted signature systems operated same point implementing different switching techniques. Since MOSFET re-activated lowest drain level, classical COSS capacitor discharge switch closing does exist very narrow peak current gone (also this peak often confusing current-sense comparator when really energetic, even sometimes despite presence circuitry). result, Quasi-square wave converters recommended where Switch-Mode Power Supply (SMPS) needs operate close Radio-Frequency section, notably chassis.
Detecting Core Reset Event
Core reset detection usually done dedicated auxiliary winding whose voltage image directly linked transformer flux
VAUX
(eq.
Depending controller device, polarity observed signal must detection circuitry. Semiconductor NCP1207, this polarity should Flyback type, that say, when MOSFET closes, auxiliary voltage dips below ground stays there, safely clamped -0.7 until MOSFET turned off. Figure gives example demagnetization signal NCP1207.
Figure Soft-switching Approach Reduces Energy Content Above
Figure Hard-switching System Generates Noise Same Portion
20.0 Leakage Contribution 10.0 VAUX(t)
-10.0 -N.VIN -20.0
Figure Core Reset Detection Signal Coming from Flyback Winding
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NCP1207 Quasi-resonant Controller Quasi-square Wave Resonant Operation: dedicated pin, NCP1207 able detect transformer core demagnetization before starting switching cycle. closing MOSFET thus occurs zero current, cutting switch turn-on losses secondary diode recovery losses. delaying turn-on event, possible turn MOSFET minimum drain-source wave, further reducing losses electromagnetic interference (EMI). NCP1207 also features minimum TOFF, preventing frequency runaway light loads: when demagnetization occurs before blanking delay, device waits next valley before enabling cycle. Standby Power: When output power demand decreases, feedback (FB) voltage decreases same time. When becomes lower than selected threshold, device starts skip cycles, generating just enough switching pulses maintain output voltage. This cycle skipping only occurs peak current, ensuring noise-free standby operation. Short-circuit Protection: permanently monitors feedback line activity, ready enter safe burst mode detects short circuit. Once short-circuit disappeared, controller automatically goes back normal operation. Protection: sampling plateau voltage demagnetization winding, NCP1207 able detect over voltage output. this case goes fault, permanently disabling output. This protection fully latched, which means that power supply unplugged from mains unlatch External MOSFET Connection: leaving MOSFET external from choose device exactly suited your application. also have ability control shape gate signal, giving additional reduce amount video noise. SPICE Model: free-running model allows running transient cycle-by-cycle simulations verify theoretical design help speed design stage power supply. averaged model dedicated analysis also available ease stabilization loop. Ready-to-use templates downloaded OrCAD's PSpice Intusoft's ISPICE from Semiconductor site, NCP1207 related section. data sheet gives complete details regarding implementation NCP1207.
Power Supply Design Power Supply Specification
Input Voltage Output Power Outputs Universal input +108 Regulated (8.0 derived from through regulator +3.3 derived from +5.0 through regulator Short-circuit, over-voltage over- power Below
Protections Standby Power
Design Steps
Reflected Voltage first start design selecting amount secondary voltage want reflect primary side, which will give primary secondary turn ratio transformer. decide that want rather cheap common MOSFET, will select turn ratio
(VOUT
VINmax (VOUT about decide keep safety margin, gives 1.5. will choose turn ratio 1.2, which will give reflected voltage Peak Current Knowing turn ratio, calculate peak primary current needed supply output power. neglect delay between zero current valley drain voltage, calculate IPmax (from equation
VINmin (VOUT IPmax POUT VINmin (VOUT
VINmin 85%. Plugging other values gives maximum peak current IPmax 2.96 will choose value take into account various tolerances. NCP1207 current sense setpoint should sense resistor 0.286 will four standard resistors parallel.
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Primary Inductance calculate primary inductance need decide switching frequency range allow controller operate. There constraints; line, maximum power, switching frequency should above audible range (higher than kHz), high line, lowest nominal power, time (TOFF MOSFET should higher than prevent controller jump between valleys (because these discrete jumps between valleys generate noise transformer well). still neglect then given (equation 19):
FSWmin POUTmax
clamp. also SPICE simulator test right values components. chose clamp, using 1N4937 diode with snubber capacitor, resistor capacitor: aggressive design (the maximum drain voltage will very close maximum voltage allowable MOSFET), gives enough protection without degrading much efficiency. Once again, design SMPS work ZVS, have bigger drain capacitor, that will damp leakage inductor effect (see below).
Same Calculation Power Supply:
VINmin)N@(VOUT)VF) h@N@VINmin@(VOUT)VF)
choose output power Vdc, obtain: take tolerances into account, choose verify satisfies second condition: output power Vdc, 1.46 From equation TOFF 6.74 connect drain-to-source capacitor, calculate from equation TOFF 8.14 which higher than nominal output power range power supply wider, choose higher (650 instance) increase CDRAIN. this last solution will decrease efficiency, equal when MOSFET turned this case Zero Voltage Switching (ZVS) good choice (see below). Clamp equation calculate overvoltage leakage inductance: VOVLEAK
LLEAK CTOT
this time don't know value LLEAK, choose value primary inductance (i.e. mH), which would from final value. Considering again drain, input voltage output power, which give 1.83 obtain VOVLEAK only have available before reaching MOSFET breakdown voltage. will need clamp limit spike turn-off. Please refer application note AN1679/D (available www.onsemi.com) calculate this
start design from beginning, implement true ZVS: decide reflect assuming that have MOSFET, will have turn ratio 2.8. exact reflected voltage will available margin leakage inductance effect will IPmax will then equal 2.18 Applying same conditions will give 1.26 choose CDRAIN should higher than avoid valley jumping output consumption. want avoid clamping network protect MOSFET, CTOT should higher than 2.05 (stating that LLEAK that maximum overvoltage leakage inductance choose capacitor CDRAIN safe. through lines wrote that many parameters could changed obtain different converters end. reflected voltage obviously most sensitive parameters that influence others. Increasing reflected voltage keep wider operating range price other numbers: switching frequency increases (reset voltage stronger) primary peak current conduction losses improved goes peak demand goes low) secondary peak current conduction losses increase MOSFET undergoes bigger stress switch opening MOSFET turn-on losses really null achieved). simplify design your power supply, spreadsheet (that includes parasitic elements) available download from Semiconductor site (www.onsemi.com), under NCP1207 page. formulae described application note AND8089/D. also simulate complete power supply SPICE simulator, using NCP1207 models also available from website.
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SPICE Simulation faster easier simulate this power supply simplified free-run model have idea final results. Figure offers possible represent free-running controller: demagnetization path includes standard flip-flop that latches transition while feedback signal fixes current setpoint. simple
MR851
arrangement, system simulates very quickly allows immediate assessment what been suggested Excel spreadsheet. feedback loop purposely simplified with Zener diode arrangement, upgrade with TL431 circuitry. will simply take longer simulation time settle.
Vpos12
pos12
XFMR-AUX RATIO_POW -0.17 RATIO_AUX 0.17
Vneg12
neg12
Current 7.0/V(pos12)
MR851
Current 7.0/V(pos12)
XFMR-AUX RATIO_POW -1.2 RATIO_AUX -0.06
IOUT
RPRIM
VOUT
MR856 Idiode
VOUT Resr1
Icoil
LPRIM LPEAK
COUT1
Current 30/V(VOUT)
Free rgate toffmin 7.5m
MUR160
VOUT
Free
VDRAIN
MTP6N60E
MOC8101
Rsense 0.275
Figure Simulation Schematic Power Supply
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Figure Figure show, simulation very close what obtained board:
VDRAIN (100 V/div)
VSENSE (500 mV/div)
Figure Simulation Results
Figure Real Measurements
SPICE simulation offers another advantage, which evaluation component stresses. good models, immediately measure MOSFET conduction losses worse case, current rectifiers, resonating capacitor output capacitors, choose right components accordingly. instance used simulated currents determinate winding characteristics transformer, knowing that line imposes highest stress transformer. Based simulation results, following specification been sent transformer manufacturer: Primary: Input voltage: Switching frequency: IPpeak Aux: ratio NP/NAUX 9.0, IRMS Secondaries: (+108 ratio 1.0, IRMS POW1 (+12 ratio NPOW1 9.0, IRMS POW2 (-12 ratio NPOW2 9.0, IRMS Auxiliary Winding auxiliary winding will used supply controller detect transformer demagnetization. supply VCC, voltage should higher than (VCCOFF VF), lower than
(max voltage applied pin): choose value voltage applied demagnetization (pin should lower than over-voltage protection (OVP) threshold, which will external resistor divide auxiliary voltage plateau voltage during normal operation will will allow over-voltage auxiliary winding, corresponding 21.6 over-voltage +108 output, which acceptable. There internal resistor, just need another external more standard value. There internal clamping diode protect against lethal over-voltages, current this diode should never higher than mA/-2 must verify that chosen resistor accordance with this specification. during turn-on, auxiliary winding delivers highest line level), then maximum current flowing from V)/27 1.32 which safe. This resistor, which connects winding (called ROVP1 schematic), will also used delay turn-on MOSFET sure right valley drain voltage. total internal capacitance pin1 giving enough delay, external capacitor will added. case, will capacitor, which will delay turn-on exactly valley.
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main reason auxiliary winding will also used supply controller that maximum total gate charge MOSFET high Knowing that current consumed output stage IDRV VDRV, even frequency VDRV IDRV will higher than this current will directly flow through auxiliary supply used. Nevertheless, great interest power supply. When secondary reconfiguration used least regulation point lowered) reduce standby power, auxiliary voltage collapses. DSS, controller still fully powered during standby. This allows regulate lowest possible voltage (minimum input voltage standby regulator), transition from standby normal mode smoother (see measurements section this document). high voltage will connected mains inputs through simple 1N4007 diode lower standby power, reduced average voltage half-wave rectification (see NCP1207 data sheet details). Standby standby consumption should below achieve this target, secondary current consumption should reduced. choose secondary reconfiguration that, re-routing high voltage winding voltage output, reduces voltage unused outputs.
+108 +108 STBY
reconfiguration made thyristor, activated manual switch simplify evaluation board (see Figure 16). fact, energy stored high voltage winding used refuel voltage output capacitor, regulation made this voltage output. windings imposing currents (not voltages), connecting high voltage winding voltage output completely safe. regulation loop forces high voltage winding deliver voltage, then other windings also delivering lower voltages than normal conditions same ratio). consumptions windings drastically reduced this division output voltages. During standby, regulation made through Zener diode (Figure 17). NCP1207 still powered DSS, even there more auxiliary voltage, regulation point lower than normal mode. only constraint output voltage higher than minimum input voltage voltage regulator, there need guard band. regulate output, standard MC7805 TO220, with drop voltage regulation point added soften transitions between standby normal modes. They usually necessary loop compensation correctly designed adding networks around TL431).
STBY
Figure Secondary Reconfiguration with Thyristor
Figure Standby Regulation Secondary Reconfiguration
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NCP1207 enters peak current skip mode lower consumption low-load conditions. with some cheap transformers, peak current might high, generating audible noise. that case, propose different implementation standby regulation (Figure 18): imposing ripple regulated output, force controller burst mode, which generates less mechanical stress transformer.
STBY OUTPUT
Approach (Overpower Compensation):
classical compensate this effect amount input voltage primary current sense information (Figure 19):
Cbulk RCOMP
LPRIM
IC3x Burst Generator
RSENSE
Figure Classical Overpower Compensation
Unfortunately, possible implement this scheme with NCP1207 resistor series with current sense information (RCS) low, since used adjust skip cycle level. would require compensation resistor RCOMP, wasting power. would interesting have image input voltage, lower level. possible using forward voltage auxiliary winding: adding diode series with auxiliary winding, have access forward voltage (Figure 20).
Cbulk
Figure This Standby Regulation Circuitry Imposes Noise-free Burst Mode
LPRIM
Overpower Protection NCP1207 integrates short-circuit protection, based sensing peak primary current. Unfortunately, have seen before, this peak current dependent input voltage (Figure 19): sense resistor chosen allow maximum peak current input voltage flow MOSFET. high input voltage, peak current necessary deliver same output power much lower: sense resistor being fixed, maximum output power deliverable high input voltage much greater. conclusion that built-in short-circuit protection overpower protection (OPP). however possible implement adding additional components beside controller. propose different approaches, compensating voltage depending input voltage, other sensing output current.
CVCC
RVCC
RFWD
LAUX CRES
Rdmg
NCP1207 RCOMP RSKIP RSENSE
Cdmg
Figure Overpower Compensation using Forward Voltage
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This forward voltage proportional N.VIN being turn ratio windings). RFWD added supply reverse current during forward activity. Knowing value forward voltage series resistor RSKIP, then easy calculate value compensation resistor RCOMP create desired offset current sense signal high input voltage. Here some screen shots describing effect compensation:
COMPENSATION OFFSET
CURRENT SENSE VOLTAGE SENSE RESISTOR VOLTAGE
COMPENSATION VOLTAGE
DRAIN VOLTAGE
Figure Line Compensation
COMPENSATION OFFSET CURRENT SENSE VOLTAGE SENSE RESISTOR VOLTAGE
COMPENSATION VOLTAGE
DRAIN VOLTAGE
Figure Line Compensation
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Approach (Regulation Foldback): Final Schematic
sensing current flowing output, possible build efficient overcurrent protection, folding back regulation level when current threshold reached. purposely completely independent input voltage. simple bipolar transistor sense voltage across resistor pull down optocoupler emitting diode (Figure 23). protection temperature dependent, gives enough precision most applications. main drawback this approach that only output protected: circuitry must duplicated each output that needs protected.
+108 RSENSE
Figure following page, shows final schematic implemented demonstration board. includes options presented design steps. board equipped default with following options: clamp non-ZVS designs regulation Zener diode when secondary reconfiguration activated overcurrent protection output also accepts following options: regulation ripple generator when secondary reconfiguration activated (see bill material components mounting this option) overpower compensation through forward voltage auxiliary winding types transformers soldered board, either from OREGA from VOGT ELECTRONIC.
Figure Overcurrent Foldback Output
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+5.0 +3.3
IC3x
ROVP1
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ROVP2
MAINS
Figure Schematic Demonstration Board
AND8145/D
Board Performance
Efficiency
VAC, POUT 84.3% VAC, POUT 85.1% VAC, POUT 83.6% VAC, POUT 84.7%
length hour). VAC, output loaded with (i.e. output power): With simple Zener regulation: PSTBY (but might noisy with some transformers) With ripple generator: PSTBY
Conducted Signature
Standby Power
Measured Infratek wattmeter operating watt-hour accumulation mode better accuracy (run
test been conducted board, VAC, with full load outputs total secondary power): Figure measurement done quasi-peak (QP) mode.
Figure Signature Captured
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WAVEFORMS
Figure VDRAIN Different Output Power
Figure shows valley jumping when output power decreases P1), skip case really light load (P4).
Maximum drain voltage obtained high line, full load. Vdc, output, from Figure that MOSFET safe.
Figure VDRAIN High Line, Full Load
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Figure shows, transition from standby normal mode smooth, without steps. "+12 output still regulated standby, lowered much needed supply regulator.
Output
Output
Figure Standby Normal Mode Transition
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BILL MATERIAL
Standard Equipment Board GENERIC TABLE
Part Number D11, Reference NCP1207 TL431 SFH615 MC7805 LP2950-3.3 IRFIB6N60 BC547C KBU4K 1N4007 1N4148 1N4937 MR856 MR852 Replaced wire Zener Zener Replaced wire MCR22-6 VAC/2.0 Transformer VOGT reference UL030 121/21 OREGA reference G7209-01 Mains filter OREGA TL36P nF/275 classe nF/1 mF/400 nF/50 pF/50 nF/630 pF/1 mF/50 nF/50V pF/1 mF/35 mF/16 mF/250 nF/4 classe pF/200 C26, Rs1, Rs2, Rs3, RVOP1 R18, R13, R14, R15, R16, R20, R22, Part Number Replaced wire Meg/4 Replaced wire Reference
*For transformer, order OREGA ref. G7209-03 (C22, C26, C27, R31, implemented, Zener diode added parallel IC2)
C11, C13, C15, C25, C14, C17,
Modifications needed implement standby ripple generator:
Part Number Reference Replaced wire Zener mF/25
Overpower Compensation:
Part Number 1N4148 Reference
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LAYOUT
STANDBY
Some important points that have been taken into account make proper layout: high alternating current loops areas both primary secondary smallest possible minimize noise emission
drain track shortest possible heatsink connected ground. acts shield
between noisy signals (drain, clamp, transformer) sensitive signals around controller
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Notes
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Introduction Quasi-square wave resonant converters, also known quasi-r

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