CS1124 offers dual-channel component count interface solution ground r

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CS1124 offers dual-channel component count interface solution ground r

Datasheet Thumbnail

Top Searches for this datasheet

AND8149/D Understanding Using CS1124 Sensor Interface
CS1124 offers dual-channel component count interface solution ground referenced variable reluctance sensors. product easy when basic circuit operation understood when certain application guidelines followed. This note, along with CS1124 data sheet (CS1124/D) will provide user with information necessary successful application. Circuit Basics Each channel CS1124 independent input bias clamp circuitry, independent comparators with Hysteresis voltage generators. Both channels share common reference generator normal diagnostic modes. block diagram detailing channel shown Figure along with some external application components. We'll explore circuit using channel and, where convenient, subscripted indicate either channel. voltage developed sensor applied through resistor pin. When sensor produces voltage (VRS biased voltage developed RRS). When diagnostic (normal mode) voltage compared COMP1 voltage INADJ developed RADJ plus minus VHYS. When diagnostic (diagnostic mode) voltage compared voltage developed RADJ plus VHYS. From comparator's viewpoint, these voltages respectively shown labels block diagram comparator's inputs, When comparator output will low, transistor will OUT1 will [VCC. When comparator output will high, transistor will OUT1 will [GND.
CS1124
DIAG INP1 ACTIVE CLAMP (6.05 OUT2 OUT1
SENSOR
"VHYS ("160 INADJ
COMP1 COMP2
INADJ RADJ
Figure CS1124 Block Diagram
Semiconductor Components Industries, LLC, 2004
March, 2004 Rev.
Publication Order Number: AND8149/D
AND8149/D
polarity VHYS controlled input states COMP1. When VIN1 VINADJ, VHYS polarity shown Figure When VIN1 VINADJ, VHYS polarity shown Figure
INADJ
Figure clarity, sensor voltage shown triangular wave.
+TRP
VINX INADJ
VINADJ
VHYS
VHYS
-TRP VOUTX
VIN1 VINADJ
VIN1 VINADJ
Figure Hysteresis Voltage States
normal mode, VHYS alternately added subtracted from bias voltage developed RADJ. diagnostic mode, VHYS added bias voltage developed RADJ. resultant voltages described data sheet variously "VHYS trip point ("TRP) thresholds, nominally specified "160 around bias voltage developed INADJ RADJ. Figure shows threshold bias voltage relationships between VINADJ VHYS normal diagnostic modes, bias voltage VINX (VIN1).
Figure Input Threshold Output Responses (Normal Mode)
+VHYS +TRP +VHYS VINADJ -VHYS -TRP RADJ RADJ
NORMAL MODE VINX
DIAGNOSTIC MODE
RRS)
Figure Comparator Bias Points Thresholds
resistance should substantially equal RADJ prescribed data sheet. normal mode INPX INADJ equal resistances INADJ pins will establish equal voltage bias points. voltage produced sensor alternates around VINX bias voltage. VINX voltage (VP) compared "TRP voltage (VN) produced alternating polarity VHYS around VINADJ bias voltage. CS1124's normal mode input output responses shown
Let's review circuit basics, using Figure We'll component values RADJ we'll typical data sheet values: "VHYS "160 INP1 INADJ INP1, where 1.00 normal mode 1.55 diagnostic mode. We'll ignore moment. Assume that RADJ zero, that DIAG (normal mode), that we've connected voltage source (VRS) IN1. Assume also that zero. OUT1 will then when increased slightly greater than +160 above GND, then high when decreased slightly less than -160 below GND. With INADJ connected (RADJ "TRP "VHYS trip points "VHYS around GND. lowest signal detect "VHYS. Next we'll RADJ Using equivalent resistance (REQ) INP1 (I1) current, VIN1 (with will kW). Since normal mode 1.00, INADJ current (I2) VINADJ kW). With INADJ biased VINADJ, "TRP VINADJ VHYS trip points "VHYS around VINADJ. OUT1 will change states when VIN1 slightly greater than +424 when VIN1 slightly less than +104 (264 above GND. With nearly same RADJ since (VIN1 VINADJ), VHYS will +160 (Figure OUT1 will high state since (VIN1 VINADJ VHYS VN). With VIN1 OUT1 will when slightly greater than above VINADJ, VHYS will change polarity -160 When slightly less than below VINADJ, OUT1 will high VHYS will change back +160 normal mode, INADJ INP1 with RADJ, lowest signal detect (VINADJ VINX) VHYS.
http://onsemi.com
AND8149/D
we'll voltage zero volts. When VIN1 compared VINADJ VHYS (the trip point), OUT1 will high state since VN). increase slightly above 38.545 (424 mV/11 OUT1 will state VN). we'll DIAG VCC. Since diagnostic mode 1.55, current INADJ will increase 17.05 that INADJ bias voltage 409.2 (17.05 trip point 569.2 (VINADJ VHYS). With VIN1 (38.545 OUT1 will high state since 569.2 VN). further increase slightly above 51.745 (569.2 mV/11 OUT1 will state VN). These results show that expect diagnose minimum (RDMIN) maximum (RDMAX) resistances respectively 38.545 equivalent [(1.00 RADJ) (VHYS/INPX)] 51.745 equivalent [(1.55 RADJ) (VHYS/INPX)] resistance change 51.745 38.545 =13.2 equivalent 0.55 RADJ. Input Clamps There three clamp points associated with inputs IN2. Figure shows simplified clamp circuitry. data sheet specifies these points positive (7.0 typical) negative (-0.30 typical.) Since sensors easily produce voltages excess peak, clamp prevents damage CS1124 keeping these voltages below breakdown voltage manufacturing process product. Since substrate integrated circuit must always lowest voltage potential, -0.30 clamp prevents turn-on parasitic elements within maintain input signal within dynamic range comparators, third clamp used limit comparator input voltage [1.6 This clamp places upper limit value RADJ. Since VINADJ VHYS highest reference which VINX compared, VINADJ VHYS must remain below clamp. reference Figure derived from internal band-gap regulator substantially insensitive temperature while varies considerably with temperature. therefore recommended that VINADJ VHYS should RADJ (MAX) (1.2 VHYS)/ INPX).
Circuit Dynamics Getting predictable behavior from CS1124 requires correct power-up pre-conditioning comparators' inputs. Since there internal power-up control circuitry, this must managed application components INADJ pins. Assuming that diagnostics done power-up, since VINADJ VHYS reference which VINX compared, need establish VINADJ before VINX guarantee predictable behavior. delays imposed pre-conditioning also need considered order obtain correct diagnostic results. following sections will show circuit behavior with without presence sensor with several circuit modifications. sensor used with test circuits automotive-type sensing unit. cases DIAG input held low. sure note voltage time scales graphs presented. Powering slew rate power supply must slow enough allow internal bias currents voltages correctly established. Using test circuit Figure observe power-up behavior when step applied pin.
STEP
RADJ INADJ OUT1 OUT2 DIAG OUT1 OUT2
CS1124 Figure Test Circuit
graphs Figures show results when step applied Test Circuit with without sensor. Figure VIN1 quickly reaches clamp point despite capacitor pin. Because quick rise time step, INP1 current well controlled (>>11 mA.) Figure shows that when sensor present, VIN1 still quickly approaches clamp, then decays level defined INP1 RRS). decay rate (tIN1) established RRS). Note that both graphs VIN1 established before VINADJ (our reference node) OUT1 remains low.
Figure Simplified Input Clamp Circuit http://onsemi.com
AND8149/D
OUT1
INADJ
Figure Sensor Absent
Figure Sensor Present
Experiment shown that proper operation results with slew rate about V/ms, limiting slew rate V/ms adds sufficient margin. bulk filter capacitance application's regulator circuit isn't large enough keep slew rate V/ms, simple network added trick. bypass capacitor recommended event. Figure shows RSLEW-CSLEW arrangement.
STEP RSLEW RADJ INADJ OUT1 OUT2 DIAG OUT1 OUT2 CSLEW
CS1124 Figure Test Circuit
CS1124 data sheet specifies maximum operating current, choosing RSLEW would produce about drop pin. Recalling that exponential response linear over range 0.6t, solve [5.0 V-0.2 [1-e-0.6] 2.16 Given V/ms requirement, time needed reach 2.16 2.16 V/(0.5 V/ms) 4.32 Since this time represents 0.6, solve that t/0.6: 4.32 ms/0.6 Lastly find CSLEW t/RSLEW choose next highest standard value, Note that choice RSLEW only accounted voltage drop produced during power-up consider additional dynamic currents during output switching activation negative clamps, each which will produce additional drops (ripple voltages) pin. RSLEW decreased CSLEW increased reduce ripple voltages. Figure shows that slew rate 0.425 V/ms when step applied Test Circuit (and also reveals intrinsic start-up delay CS1124's internal circuitry, [130 sample tested.)
OUT1
INADJ 0.425 V/ms
Figure Slew V/ms
http://onsemi.com
AND8149/D
Figures show results when step applied Test Circuit Figure shows that VIN1 ramps linearly clamp point about correctly established INP1 current. Since VINADJ already established VIN1 ramps OUT1 initially goes high then when VIN1 crosses +TRP threshold. Figure shows that when sensor present, VIN1 rises exponentially level defined INP1 RRS). Again, rise rate (tIN1) established RRS). both cases VIN1 expected response when correctly established INP1 current step applied capacitor (sensor absent) combination.
OUT1
INADJ
Figure Sensor Absent
Figure Sensor Present
STEP RADJ INADJ OUT1 OUT2 DIAG OUT1 OUT2 RSLEW CSLEW
Pre-Conditioning described data sheet, provide pass filter and, when power-up properly managed, also serve pre-condition comparator correct state delaying signal. could also force VINADJ quickly established regardless external components inputs. Adding capacitor Figure between power supply INADJ does both channels. With RRS) RADJ, choosing gives nearly equal tINX tINADJ time constants settling times under nominal circuit conditions. benefit comes with both risk penalty. Power supply noise could coupled through INADJ thereby risk modulation comparators' trip points. risk could reduced using separate "clean" supply using voltage reference (the clamp voltage.) course, we'd have certain that these alternate voltages established before CS1124's voltage. penalty delay that results from RADJ time constant, tINADJ. need wait several time constants power-up when changing from normal mode diagnostic mode before sampling OUTX.
CS1124 Figure Test Circuit
Figures show results when step applied Test Circuit Both figures show effect VINADJ. Since initially appears short-circuit, VINADJ quickly brought power supply voltage, then decays bias point defined INADJ RADJ. decay rate (tINADJ) established RADJ Again, both cases VIN1 expected responses.
http://onsemi.com
AND8149/D
OUT1
INADJ
Figure Sensor Absent
Figure Sensor Present
Diagnostic Operation that we've examined circuit basics power-up pre-conditioning requirements, examine interpret CS1124's outputs power-up when changing modes. also impact component choices resulting delays (tINX tINADJ) imposed affect diagnostics. Each input circuit consists sensor, series resistor, filter capacitor. While equation data sheet shows determine quality sensor resistance RRS, quality entire input circuit assessed including series resistor with RRS: [(INPX RADJ) VHYS]/INPX. shorted sensor shorted filter capacitor diagnosed change output occurs during normal operation (DIAG GND) when expected that sensor should produce output voltage greater than (VINADJ VINX) VHYS. open sensor series resistor (Figures diagnosed power-up (DIAG GND) after delay that results from tINADJ and, since CV/I after delay (tINX) that results from VCLAMPX, INPX. VIN1 eventually reaches clamp voltage VINADJ will eventually settle RADJ INADJ. While Figures show that OUT1 does change state after both VIN1 VINADJ have settled, necessary wait until after delays before changing state DIAG input guarantee valid results. Setting DIAG then will
Table Diagnostic Behavior
OUTX After Power-Up DIAG
change output state since VINX (VINADJ VHYS) before changing state diagnostic input. normal input circuit (Figures diagnosed power-up (DIAG GND) after tINX delay after tINADJ delay. Figures also show that OUT1 does change state after both VIN1 VINADJ have settled, again necessary wait before changing state DIAG input. Setting DIAG then will change output state since VIN1 already below VINADJ before changing state diagnostic input. does setting DIAG give additional information? When input circuit resistances change enough cause VINX greater than VINADJ VHYS, OUTX will low. When DIAG GND, this will occur when RRS) just slightly greater than RDMIN =[(1.00 RADJ) (VHYS/INPX)]. When DIAG VCC, this will occur when RRS) just slightly greater than RDMAX [(1.55 RADJ) (VHYS/INPX)]. We've seen, after correct power pre-conditioning, that OUTX will high remain high input circuit good that OUTX will remain input circuit bad. OUTX after power-up, then DIAG switched VCC, OUTX will high RDMIN RRS) RDMAX. samples OUTX needed know quality input circuit: after power-up after changing DIAG from high. Table summarizes diagnostic behavior.
OUTX After DIAG
Circuit Quality GOOD RDMIN RRS) RDMAX
http://onsemi.com
AND8149/D
worst-case delays sampling OUTX occur where just RDMIN when VINADJ VHYS. Test Circuit case Figure need wait several RDMIN time constants after power-up VINX settle before sampling OUTX. wait typical VINX will near 99.4% VINADJ VHYS. only need wait mode change delay time specified data sheet max.) after changing DIAG from high before again sampling OUTX. Test Circuit case Figure need wait longer several RDMIN tINADJ time constants after power-up VINX VINADJ settle before sampling OUTX. wait typical VINX will near 99.4% VINADJ VHYS vice-versa.) Since INADJ current will have step change typical when changing from normal mode diagnostic mode, need wait additional 5tINADJ after changing DIAG from high before again sampling OUTX.
http://onsemi.com
AND8149/D
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center Semiconductor P.O. 5163, Denver, Colorado 80217 Phone: 303-675-2175 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder additional information, please contact your local Sales Representative.
http://onsemi.com
AND8149/D

CS1124 offers dual-channel component count interface solution ground r

Top Searches for this datasheet

Other recent searches