16Mbyte(4Mx36) 72-pin SIMM, with Parity Mode, 2K/4K Ref. Part HMD4M36M
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HMD4M36M9EG, HMD4M36M9EA
16Mbyte(4Mx36) 72-pin SIMM, with Parity Mode, 2K/4K Ref. Part HMD4M36M9EG HMD4M36M9EAG
HMD4M36M9EG dynamic high-density memory module. module HMD4M36M8E consists eight CMOS DRAMs 24-pin packages CMOS Quad /CAS DRAM 28-pin package mounted 72-pin, double-sided, FR-4-printed circuit board. 0.1uF 0.22uF decoupling capacitor mounted printed circuit board each DRAM. module single Inline memory module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs -compatible.
FEATURES
Part Identification HMD4M36M9E-2048 Cycles/32ms Ref. Solder HMD4M36M9EG- 2048 Cycles/32ms Ref. Gold HMD4M36M9EA-4096 Cycles/64ms Ref. Solder HMD4M36M9EAG- 4096 Cycles/64ms Ref. Gold Access times 60ns High-density 16MByte design Single ±0.5V power supply JEDEC standard pinout mode operation /CAS-before-/RAS refresh capability compatible inputs outputs FR4-PCB design Packages 72-pin SIMM 60ns
ASSIGNMENT
SYMBOL DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 SYMBOL DQ24 DQ25 /RAS2 DQ26 DQ17 DQ35 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 SYMBOL DQ27 DQ10 DQ28 DQ11 DQ29 DQ12 DQ30 DQ13 DQ31 DQ32 DQ14 DQ33 DQ15 DQ34 DQ16
OPTIONS
Timing 50ns access 60ns access
MARKING
PRESENCE DETECT PINS
50ns
PERFORMANCE RANGE
Speed tRAC 50ns 60ns tCAC 13ns 15ns 90ns 110ns tHPC 26ns 30ns
A0-A11 Address Input Ref.) A0-A10 Address Input Ref) *Note:A11 used only HMD4M36M9EA
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
HANBit Electronics Co.,Ltd.
FUNCTIONAL BLOCK DIAGRAM
HMD4M36M9EG, HMD4M36M9EA
/CAS0 /RAS0
A0-A10(A11)
DQ0-DQ3
A0-A10(A11)
DQ4-DQ7
/CAS1
A0-A10(A11)
DQ9-DQ12
A0-A10(A11)
DQ13-DQ16
CAS0 CAS0 CAS0 CAS0 A0-A11(A11)
DQ17 DQ26 DQ35
/CAS2 /RAS2
A0-A10(A11)
DQ18-DQ21
A0-A10(A11)
DQ22-DQ25
/CAS3
A0-A10(A11)
DQ27-DQ30
A0-A10(A11)
DQ31-DQ34
A0-A10(A11)
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
-20.1uF 0.22uF Capacitor each DRAM HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature
HMD4M36M9EG, HMD4M36M9EA
SYMBOL ,OUT TSTG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 SPEED UNITS
ICC4 ICC5 ICC6 Il(L) IO(L)
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V
URL:www.hbe.co.kr REV. 1.0. (August. 2002) HANBit Electronics Co.,Ltd.
HMD4M36M9EG, HMD4M36M9EA
ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
STANDARD OPERATION Random read write cycle time Access time from Access time from Access time from column address output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
HANBit Electronics Co.,Ltd.
Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced /RAS Refresh period Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge Fast page mode cycle time /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh)
HMD4M36M9EG, HMD4M36M9EA
tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH 200K 200K
/CAS precharge(C-B-R counter test) tCPT NOTES 1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles before proper device operation achieved. 2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. 3.Measured with load equivalent 2TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. 5.Assumes that tRCD tRCD(max) tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
HANBit Electronics Co.,Ltd.
HMD4M36M9EG, HMD4M36M9EA
PACKAGING INFORMATION
SIMM Design
107.95 3.38 1.57 101.19 3.18 0.51
16.00 10.16 6.35
2.03 1.02 6.35 95.25 6.35 1.27 3.34
0.25
2.54
1.29±0.08 Gold 1.04±0.10 1.27mm Solder:0.914±0.10mm
ORDERING INFORMATION
Refresh Cycle 2,048 Cycles 32ms Ref. 2,048 Cycles 32ms Ref. 4,096 Cycle 64ms Ref.
Part Number
Density
Org.
Package
SPEED
HMD4M36M9EG-5 HMD4M36M9EG-6 HMD4M36M9EAG-5
16MByte 16MByte 16MByte
32bit 32bit 32bit
Pin-SIMM Pin-SIMM Pin-SIMM
5.0V 5.0V 5.0V
50ns 60ns 50ns
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
HANBit Electronics Co.,Ltd.
HMD4M36M9EAG-6 16MByte 32bit
HMD4M36M9EG, HMD4M36M9EA
Pin-SIMM 4,096 Cycle 64ms Ref. 5.0V 60ns
URL:www.hbe.co.kr REV. 1.0. (August. 2002)
HANBit Electronics Co.,Ltd.
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