16Mbyte(4Mx32) 72-pin MODE, 2K/4K Ref. SIMM Design Part HMD4M32M8EG, H
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HMD4M32M8EG/8EAG
16Mbyte(4Mx32) 72-pin MODE, 2K/4K Ref. SIMM Design Part HMD4M32M8EG, HMD4M32M8EAG
HMD4M32M8E dynamic high-density memory module. module consists eight CMOS 4bit DRAMs 24-pin packages mounted 72-pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single In-line Memory Module with edge connections intended mounting 72-pin edge connector sockets. module components powered from single power supply inputs outputs TTL-compatible.
FEATURES
Part Identification HMD4M32M8EG- 2048 Cycles/32ms Ref. Gold HMD4M32M8EAG- 4096 Cycles/64ms Ref. Gold Access times 60ns High-density 16MByte design. Single ±0.5V power supply JEDEC standard pinout EDO(extended data out) mode operation compatible inputs outputs FR4-PCB design SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 SYMBOL DQ22 DQ23 /RAS2 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
ASSIGNMENT
OPTIONS
Timing 50ns access 60ns access Packages 72-pin SIMM
MARKING
PRESENCE DETECT PINS
50ns 60ns
PERFORMANCE RANGE
A0-A11:Address Input Ref.) Speed tRAC 50ns 60ns tCAC 13ns 15ns 90ns 110ns tHPC A0-A10:Address Input Ref.) 26ns *Note: used only HMD4M32M8EAG 30ns
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
FUNCTIONAL BLOCK DIAGRAM
HMD4M32M8EG/8EAG
/CAS0 /RAS0
A0-A10(A11)
DQ0-DQ3
A0-A10(A11)
DQ4-DQ7
/CAS1
A0-A10(A11)
DQ8-DQ11
A0-A10(A11)
DQ12-DQ15
/CAS2
/RAS2
A0-A10(A11)
DQ16-DQ19
A0-A10(A11)
DQ20-DQ23
/CAS3
A0-A10(A11)
DQ24-DQ27
A0-A10(A11)
DQ28-DQ31
A0-A10(A11)
0.1uFor0.22uFCapacitor foreachDRAM DRAMs
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD4M32M8EG/8EAG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Voltage reference VSS, TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 TYP. Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 Il(L) IO(L) SPEED UNITS
ICC1 Operating Current (/RAS /CAS Address cycling RC=min.) ICC2 Standby Current /RAS=/CAS=VIH ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling @tRC=min
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
HMD4M32M8EG/8EAG
ICC4 Fast Page Mode Current (/RAS=VIL, /CAS, Address cycling @tPC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level (IOH= -5mA Output Voltage Level (IOL 4.2mA NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained with output open. specified average current. ICC1 ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/WE) Input Capacitance (/RAS0,/RAS2) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.) UNIT
STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay from /CAS Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time Column address set-up time
SYMBOL tRAC tCAC tCLZ tCEZ tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
Column address hold time Column address hold referenced /RAS Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command hold referenced /RAS Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Data-in hold referenced /RAS Refresh period Write command set-up time /CAS delay time /RAS delay time /CAS precharge(C-B-R counter test) Column address delay time Access time from /CAS precharge /CAS precharge time (Hyper Page cycle) /RAS pulse width (Hyper Page cycle) /RAS precharge time (C-B-R refresh) tCAH tRAL tRCS tRCH tRRH tWCH tWCR tRWL tCWL tDHR tREF tWCS tCWD tRWD tCPT tAWD tCPA tRASP tWRP
HMD4M32M8EG/8EAG
200K 200K
/RAS hold time (C-B-R refresh) tWRH NOTES 1.An initial pause 200µs required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles before proper device operation achieved. 2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. 3.Measured with load equivalent 1TTL loads 100pF 4.Operation within tRCD(max) limit insures that tRAC(max) met. tRCD(max) specified reference point only. tRCD greater than specified tRCD(max) limit, then access time controlled exclusively CAC. 5.Assumes that tRCD tRCD(max) tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet electrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge readwrite cycles. Operation within tRAD(max) limit insures that tRAC(max) met. tRAD(max) specified reference point only. tRAD greater than specified tRAD(max) limit. then access time controlled tAA.
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
HMD4M32M8EG/8EAG
TIMING DIAGRAM
Please refer attached timing diagram chart (IV)
PACKAGING INFORMATION
SIMM Design
107.95 3.38
1.57 101.19
3.18 0.51
16.00 6.35
2.03 10.16
1.02
6.35
95.25
1.27
3.34
6.35
0.25
2.54
1.27±0.08 Gold 1.04±0.10
1.27
Solder:0.914±0.10mm
ORDERING INFORMATION
Refresh Cycle 2,048 Cycles 32ms Ref. 4,096 Cycle 64ms Ref. 2,048 Cycles 32ms Ref. 4,096 Cycle 64ms Ref.
Part Number
Density
Org.
Package
Speed
HMD4M32M8EG-5 HMD4M32M8EAG-5 HMD4M32M8EG-6 HMD4M32M8EAG-6
16MByte 16MByte 16MByte 16MByte
32bit 32bit 32bit 32bit
Pin-SIMM Pin-SIMM Pin-SIMM Pin-SIMM
5.0V 5.0V 5.0V 5.0V
50ns 50ns 60ns 60ns
URL:www.hbe.co.kr REV. 1.0(August. 2002)
HANBit Electronics Co.,Ltd.
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