8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4E, HMD2M3
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HMD2M32M4E/4EG
8Mbyte(2Mx32) Mode, Refresh 72Pin SIMM, Design Part HMD2M32M4E, HMD2M32M4EG
HMD2M32M4E 32bit dynamic high-density memory module. module consists four CMOS 16bit DRAMs 42-pin packages mounted -pin, double-sided, FR-4-printed circuit board. 0.22uF decoupling capacitor mounted printed circuit board each DRAM components. module single -line Memory Module with edge connections intended mounting -pin edge connector sockets. module components powered from single power supply inputs outputs -compatible.
FEATURES
Part Identification HMD2M32M4E- 1024 Cycles/16ms Solder HMD2M32M4EG- -1024 Cycles/16ms Gold Access times 60ns High-density 8MByte design Single ±0.5V power supply JEDEC standard pinout mode operation compatible inputs outputs FR4-PCB design 90ns 110ns 130ns 60ns
SYMBOL DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 70ns
ASSIGNMENT
SYMBOL DQ22 DQ23 /RAS3 /RAS2 /CAS0 /CAS2 /CAS3 /CAS1 /RAS0 /RAS1 SYMBOL DQ24 DQ25 DQ10 DQ26 DQ11 DQ27 DQ12 DQ28 DQ29 DQ13 DQ30 DQ14 DQ31 DQ15
OPTIONS
Timing 50ns access 60ns access 70ns access Packages 72-pin SIMM
MARKING
PERFORMANCE RANGE
Speed tRAC 50ns 60ns 70ns tCAC 15ns 15ns 15ns
PRESENCE DETECT PINS
50ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
Functional Block Diagram
HMD2M32M4E/4EG
/RAS0 /CAS0 /CAS1 /RAS /LCAS /UCAS DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A0-A11
DQ0-15
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS LCAS /UCAS /RAS1 /CAS0 /CAS1
A0-A11
/RAS2 /CAS2 /CAS3 /RAS /LCAS /UCAS
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ10 DQ16-31 DQ11 DQ12 DQ13 DQ14 DQ15
/RAS /RAS3 /CAS2 /CAS3
/LCAS /UCAS
A0-A11
A0-A11
A0-A11
0.1uFor 0.22uF Capacitor each DRAM DRAMs
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage Relative Voltage Supply Relative Power Dissipation Storage Temperature SYMBOL ,OUT TSTG
HMD2M32M4E/4EG
RATING 7.0V 7.0V -55oC 150oC
Short Circuit Output Current 50mA Permanent device damage occur Absolute Maximum Ratings" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference TA=0 PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 Vcc+1 UNIT
OPERATING CHARACTERISTICS
SYMBOL ICC1 ICC2 ICC3 SPEED Il(L) IO(L) ICC1 Operating Current (/RAS /CAS Address cycling ICC2 Standby Current /RAS=/CAS=V ICC3 /RAS Only Refresh Current /CAS=V /RAS, Address cycling RC=min
URL:www.hbe.co.kr REV.1.0 (August.2002)
UNITS
ICC4 ICC5 ICC6
RC=min.)
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ICC4 Fast Page Mode Current (/RAS=V /CAS, Address cycling PC=min ICC5 Standby Current (/RAS=/CAS=Vcc-0.2V ICC6 /CAS-Before-/RAS Refresh Current (/RAS /CAS cycling RC=min
HMD2M32M4E/4EG
Input Leakage Current (Any input 6.5V, other pins under test Output Leakage Current (Data disabled, VOUT 5.5V Output High Voltage Level -5mA Output Voltage Level 4.2mA NOTE: ICC1, ICC3, ICC4 ICC6 dependent output loading cycle rates. Specified values obtained output open. specified average current. ICC3, address changed maximum once while /RAS=VIL. ICC4, address changed maximum once within page mode cycle.
CAPACITANCE
TA=25 SYMBOL CIN1 CIN3 CIN4 CDQ1
DESCRIPTION Input Capacitance (A0-A10) Input Capacitance (/W) Input Capacitance (/RAS0) Input Capacitance (/CAS0-/CAS3) Input/Output Capacitance (DQ0-31)
UNITS
CHARACTERISTICS
70oC 5V±10%, notes 1,2.)
STANDARD OPERATION Random read write cycle time Access time from /RAS Access time from /CAS Access time from column address /CAS output Low-Z Output buffer turn-off delay Transition time (rise fall) /RAS precharge time /RAS pulse width /RAS hold time /CAS hold time /CAS pulse width /RAS /CAS delay time /RAS column address delay time /CAS /RAS precharge time address set-up time address hold time
URL:www.hbe.co.kr REV.1.0 (August.2002)
SYMBOL tRAC tCAC tCLZ tOFF tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH
UNIT
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Column address set-up time Column address hold time Column Address /RAS lead time Read command set-up time Read command hold referenced /CAS Read command hold referenced /RAS Write command hold time Write command pulse width Write command /RAS lead time Write command /CAS lead time Data-in set-up time Data-in hold time Refresh period Ref. Normal) tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL tREF tWCS tCSR tCHR tRPC tCPA tRASP tWRP tWRH
HMD2M32M4E/4EG
200K 200K
Write command set-up time /CAS setup time (C-B-R refresh) /CAS hold time (C-B-R refresh) /RAS precharge /CAS hold time Access time from /CAS precharge /CAS precharge time (Fast page) /RAS pulse width (Fast page /RAS precharge time (C-B-R refresh) /RAS hold time (C-B-R refresh)
NOTES 1.An initial pause 200ms required after power-up followed /RAS-only /CAS-before-/RAS refresh cycles before proper device operation achieved. 2.VIH (min) (max) reference levels measuring timing input signals. Transition times measured between VIH(min) VIL(max) assumed inputs. 3.Measured with load equivalent 2TTL loads 100pF 4.Operation within RCD(max) limit insures that RAC(max) met. RCD(max) specified reference point only. greater than specified RCD(max) limit, then access time controlled exclusively CAC. 5.Assumes that tRCD(max) tAR, tWCR, tDHR referenced tRAD(max) 7.This parameter defines time which output achieves open circuit condition referenced VOL. tWCS, tRWD, tCWD tAWD restrictive operating parameter. They included data sheet lectrical characteristic only. tWCS(min) cycle early write cycle data will remain high impedance duration cycle. Either tRCH tRRH must satisfied read cycle. These parameters referenced /CAS leading edge early write cycles leading edge read write cycles. Operation within RAD(max) limit insures that RAC(max) met. RAD(max) specified reference point only. greater than specified RAD(max) limit. then access time controlled
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
TIMING DIAGRAMS TIMING
WAVEFORM READ CYCLE
HMD2M32M4E/4EG
/RAS
VIHVILtCRP tRCD tRAD tASR tRAH tASC VIHVIL-
tRAS tCSH tRSH tCAS tCAH
COLUMN ADDRESS
tCRP
/CAS
tRAL tRCH
VIHVIL/W VIHVIL/OE VIHVILDQ OHVOL-
ADDRESS
tRCS tOEA tCAC tRAC
OPEN
tRRH
tOFF tOEZ
tCLZ
DATA-OUT
TIMING WAVEFORM WRITE CYCLE (EARLY WRITE)
/RAS VIHVILtCRP /CAS VIHVILA VIHVILtRAD tASR tRAH tASC tCAH
COLUMN ADDRESS
tRAS tRCD tCSH tRSH tCAS tRAL
tCRP
ADDRESS
tCWL tRWL tWCS tWCH
VIH/W VILVIH/OE VIL-
VOHVOLDATA-IN
NOTE Dout Open
URL:www.hbe.co.kr REV.1.0 (August.2002) HANBit Electronics Co.,Ltd.
PACKAGING INFORMATION
72pin -SIMM Design
HMD2M32M4E/4EG
(Front view)
107.95 3.38 1.57 3.18 0.51
101.19
19.05mm 10.16 6.35
2.03 6.35 1.02
6.35 95.25
1.27
3.17
0.25
2.54
Gold 1.04±0.10 1.27mm Solder:0.914±0.10mm
1.29±0.08
ORDERING INFORMATION
Part Number Density Org. Package SPEED
HMD2M32M4EG-5 HMD2M32M4EG-6 HMD2M32M4EG-7
8MByte 8MByte 8MByte
32bit 32bit 32bit
Pin-SIMM Pin-SIMM Pin-SIMM
5.0V 5.0V 5.0V
50ns 60ns 70ns
URL:www.hbe.co.kr REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd.
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