TMS320AV7110 Integrated Digital Set-top Decoder Functional Specificati
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TMS320AV7110 Integrated Digital Set-top Decoder Functional Specification
Last update: 07/06/98 Revision
TMS320AV7110
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Table Contents INTRODUCTION. FEATURES
FUNCTIONS TYPES
ARCHITECTURE FUNCTIONAL BLOCK DIAGRAM. OVERVIEW 3.2.1 Transport bit-stream processing 3.2.2 Audio Video data processing SOFTWARE SYSTEM OVERVIEW
CPU. FEATURES BLOCK DIAGRAM RESOURCE MANAGEMENT.
TRAFFIC CONTROLLER (TC) FEATURES SDRAM INTERFACE PRIORITIZED INTERRUPTS MANAGING TRANSFER VIDEO/AUDIO BUFFER MONITORING SUPPORT. TRANSFER VIDEO/AUDIO DATA FROM HIGH SPEED DATA INTERFACE (HSDI) SDRAM
MPEG TRANSPORT DECODER (TPP) MODULE 6.1.1 Features 6.1.2 Description. 6.1.3 Conditional access Descrambling processing 6.1.4 Transport Parser Input Interface HARDWARE SECTION FILTERING 6.2.1 Memory 6.2.2 Filter hardware definition. 6.2.3 Filter Match Data Register definition 6.2.4 Match Result Register Definition 6.2.5 Status Register Word Definition. 6.2.6 Filter Reset Control Register 6.2.7 Typical software process flow 6.2.8 load assessment. HARDWARE CIRCUIT
VIDEO DECODER. FEATURES DESCRIPTION TRICK MODE. HIGH-LEVEL COMMANDS VIDEO DECIMATION SCALING FREE-RUN VBV-BASED DISPLAY SYNCHRONIZATION MEMORY USAGE REDUCTION 7.7.1 Vsync Reset 7.7.2 Split Video Input Buffer. CONFIGURATION VIDEO DECODER 7.8.1 Configuration video display format
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7.8.2 7.8.3 7.8.4
True Size Display Mode Video display synchronization mode. Vsync reset split buffer.
GRAPHICS ACCELERATION. 8.1.1 Description. 8.1.2 data storage. SETTING WINDOW 8.2.1 Memory. 8.2.2 Window Attribute Memory 8.2.3 Color Look Table 8.2.4 Blending Transparency 8.2.5 Hardware Cursor 8.2.6 Output Channels BITBLT HARDWARE. 8.3.1 Sources Destinations. 8.3.2 Source Destination Window Formats 8.3.3 Transparency
VIDEO OUTPUT INTERFACES ANALOG VIDEO OUTPUT NTSC/PAL ENCODER MODULE TELETEXT WIDE SCREEN SIGNALING (WSS) INSERTION (PAL MODE ONLY). 9.2.1 Teletext insertion into CVBS 9.2.2 insertion into CVBS 9.2.3 Insertion mode CLOSED CAPTION, EXTENDED DATA SERVICES, VIDEO ASPECT RATIO IDENTIFICATION SIGNAL INSERTION (NTSC MODE ONLY) DIGITAL VIDEO OUTPUT 9.4.1 Mode Digital Video Output. 9.4.2 NTSC Mode Digital Video Output
AUDIO DECODER
10.1 FEATURES 10.2 AUDIO OUTPUT. 10.2.1 Using External Audio 10.3 BYPASS. 10.4 ELEMENTARY STREAM PLAYBACK 10.5 SPDIF AUDIO OUTPUT 11.1 11.2 11.3 11.4 11.5 11.6 12.1 12.2 12.3 12.4 12.5 12.6 SYNCHRONIZATION. SYSTEM TIME CLOCK STARTUP SYNCHRONIZATION RUNTIME SYNCHRONIZATION AUDIO SYNCHRONIZATION. VIDEO SYNCHRONIZATION AUDIO-VIDEO SYNCHRONIZATION (LIP-SYNC). EXTENSION INTERFACE (EBI). ADDRESS RANGE WAIT STATE CHIP SELECT READ WRITE CYCLES INTERRUPTS EXTWAIT SIGNAL EXTENSION DRAM. BYTE ORDERING EXTENSION HIGH SPEED DATA INTERFACE (HSDI)
13.1 IEEE 1394 INTERFACE 13.1.1 `AV7110 reads data from MPEG2Lynx
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13.1.2 `AV7110 writes data MPEG2Lynx. 13.1.3 `AV7110 Internal Data Path 1394 13.2 EXTERNAL INTERFACE. 13.3 IEEE 1284 INTERFACE 13.4 COMBINING 1394, 1284 EXTERNAL CONTROLLER INTERFACES 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 15.1 15.2 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 COMMUNICATION PROCESSOR. FEATURES SMART CARD INTERFACE TIMERS UARTS INPUT PORT OUTPUT PORT GENERAL PURPOSE I/OS INTERFACE DEVICE CONTROL INTERFACES. RESET JTAG PINS REGISTER MAPS. NTSC/PAL REGISTERS BASE ADDRESS 0X72000000. BITBLT REGISTERS BASE ADDRESS 0X70000000. REGISTERS BASE ADDRESS 0X6E000000. AUDIO DECODER REGISTERS BASE ADDRESS 0X6C000000 VIDEO DECODER REGISTERS BASE ADDRESS 0X6A000000 REGISTERS BASE ADDRESS 0X68000000. REGISTERS BASE ADDRESS 0X66000000. REGISTERS BASE ADDRESS 0X64000000. TIMING DIAGRAMS PARAMETERS
17.1 DRAM INTERFACE TIMING 17.2 INTERFACE TIMING 17.3 SDRAM INTERFACE TIMING 17.4 VIDEO OUTPUT TIMINGS 17.5 HSDI TIMING DIAGRAMS 17.6 EXTERNAL 17.7 INPUT STREAM TIMING 17.8 CHARACTERISTICS 17.9 SDRAM MEMORY FIRST SILICON FIRMWARE 17.9.1 mode Memory 17.9.2 NTSC mode Memory
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List Tables TABLE `AV7110 PINS. TABLE SDRAM SELECTION REQUIREMENTS TABLE DECODED BITSTREAM INFORMATION TABLE ERROR STATISTICS MONITOR INFORMATION TABLE FLAGS COMMANDS TABLE GPDMA SOURCES DESTINATIONS TABLE TRANSPORT PACKET INPUT INTERFACE DESCRIPTION TABLE SUPPORTED VIDEO RESOLUTIONS AUTOMATIC UP-SAMPLING TABLE VIDEO DECODER COMMANDS TABLE SCALING FACTORS MONITOR FORMAT. TABLE SCALING FACTORS 16:9 MONITOR FORMAT. TABLE SCALING FACTORS MONITOR NTSC FORMAT. TABLE SCALING FACTORS 16:9 MONITOR NTSC FORMAT. TABLE `AV7110 MEMORY USAGE TABLE STORAGE FRAMES TABLE TARGET MEMORY SPACE SDRAM BYTES). TABLE SDRAM WINDOW SIZE. TABLE BLENDING LEVELS TABLE BLENDING TRANSPARENCY TABLE MODULE OUTPUT CHANNEL CONTROL TABLE SOURCE DESTINATION MEMORIES BITBLT TABLE ALLOWABLE BITBLT WINDOW FORMATS TABLE MULTIPLEXED VIDEO OUTPUT DEFINITIONS TABLE DIGITAL OUTPUT CONTROL TABLE VARIS CODE SPECIFICATION. TABLE THREE BYTE VARIS CODE. TABLE CODING ASPECT RATIO VARIS CODE. TABLE AUDIO MODULE REGISTERS TABLE PCMCLK FREQUENCIES TABLE SYSTEM TIME CLOCK MODEL TABLE EXTENSION CHIP SELECT ASSIGNMENTS TABLE HIGH SPEED DATA INTERFACE SIGNAL ASSIGNMENT TABLE TYPES TRANSFERS ALLOWED DATA PORTS TABLE 1394 INTERFACE SIGNALS TABLE 1394 CONTROL LINES DESCRIPTION TABLE EXTERNAL INTERFACE SIGNALS TABLE EDMA REGISTER DEFINITION TABLE IEEE 1284 INTERFACE SIGNALS TABLE SMART CARD DESCRIPTION TABLE GROUP VALUES TABLE GROUP VALUES TABLE TIMER CONTROL STATUS REGISTERS TABLE CONTROL/STATUS REGISTERS, IOCSRN TABLE GPIO_IRQ DEFINITIONS
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List Figures FIGURE `AV7110 BLOCK DIAGRAM FIGURE `AV7110 MEMORY FIGURE SOFTWARE BLOCK DIAGRAM FIGURE CORE DATA PATH FIGURE TRAFFIC CONTROLLER DATA FLOW FIGURE DEFAULT MEMORY ALLOCATION SDRAM (NTSC) FIGURE DEFAULT MEMORY ALLOCATION SDRAM (PAL). FIGURE EXAMPLE CIRCUIT CLOCK GENERATION FIGURE INPUT INTERFACE TIMING FIGURE HARDWARE FILTER LAYOUT FIGURE DISPLAY FORMATS `AV7110 FIGURE MODULE BLOCK DIAGRAM FIGURE USING OSD_ACTIVE SIGNAL EXTERNAL ANALOG VIDEO FIGURE OUTPUT CHANNELS MATRIX FIGURE EXTERNAL INSERTION TELETEXT SIGNAL FIGURE DIGITAL VIDEO OUTPUT TIMING FIGURE OUTPUT TIMING (16-BIT FORMAT). FIGURE TRACKING DIAGRAM FIGURE EXAMPLES DRAM CONNECTIONS 16-BIT 32-BIT EXTENSION BUSSES FIGURE BYTE ORDERING EXTENSION FIGURE FUNCTIONAL BLOCK DIAGRAM HIGH SPEED DATA INTERFACE FIGURE 1394 INTERFACE FIGURE 1394 INTERFACE READ SEQUENCE FIGURE 1394 INTERFACE WRITE SEQUENCE. FIGURE 1394 DATA FLOW BLOCK DIAGRAM FIGURE INTERFACING `AV7110 SCSI CHIP FIGURE PROGRAMMABLE DELAY REGISTER ACCESSES EDMA PORT FIGURE PROGRAMMABLE DELAY ACCESSES EDMA PORT FIGURE INTERFACING `AV7110 IEEE-1284 FIGURE COMBINED MPEG2LYNX, 1284 SCSI CONTROLLER FIGURE `AV7110'S INTERFACE SMART CARDS FIGURE READ ACCESS FROM DRAM. FIGURE WRITE ACCESS FROM DRAM FIGURE READ-MODIFY-WRITE ACCESS DRAM FIGURE READ-MODIFY-WRITE ACCESS DRAM FIGURE BEFORE DRAM REFRESH TIMING FIGURE EXTENSION SINGLE ACCESS READ TIMING WAIT STATES). FIGURE EXTENSION WRITE TIMING WAIT STATES). FIGURE EXTENSION TIMING MULTI-ACCESS MODE WAIT STATES) FIGURE READ WITH EXTWAIT ACTIVE FIGURE WRITE WITH EXTWAIT ACTIVE FIGURE SDRAM READ CYCLE FIGURE SDRAM WRITE CYCLE FIGURE SDRAM MULTI READ CYCLE. FIGURE SDRAM MULTI WRITE CYCLE FIGURE SUCCESSIVE SDRAM OPERATIONS FIGURE VARIS CODE OUTPUT TIMING FIGURE DIGITAL VIDEO OUTPUT TIMING FIGURE 1394 READ CYCLE TIMING FIGURE 1394 WRITE CYCLE TIMING FIGURE EXTERNAL CYCLE TIMING FIGURE EXTERNAL "REGISTER ACCESS" TIMING FIGURE INPUT INTERFACE TIMINGS
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Introduction
TMS320AV7110 Integrated Set-top Decoder major component Digital Video Broadcast (DVB) Settop Box. incorporates: transport packet parser (TPP) with integrated European Common Descrambler (ECD), MPEG-2 video decoder, MPEG-1 audio decoder, NTSC/ video encoder, screen display (OSD) controller graphics video, configurable high speed data interface, three UART serial data interfaces, programmable infra (IR) input output ports, Smart Card interface, extension connect peripherals such additional RS232 ports, display control panels, extra ROM, DRAM, EPROM memory. External program data memory expansion allows support range set-top boxes from high end.
Features
fully functional decoder using single Mbit external SDRAM accepts transport bit-streams 72.8Mbps burst rate Mbps average over transport packet) on-chip European Common Descrambler hardware hardware accelerator SI/PSI information processing video decoder that decodes MPEG-1 MPEG-2 Main Profile@Main Level bit-streams audio decoder that decodes MPEG-1 Layer basic stereo channels from MPEG-2 Multi-channel bit-streams audio output both SPDIF formats processor that enables mixture video data with transparency BitBLT hardware that accelerates memory block move 32/16 ARM/Thumb processor that removes need another set-top firmware that controls device operation provides application access hardware resources on-chip NTSC/PAL encoder that incorporates MacroVision logic anti-taping protection analog RGB, Composite video outputs with 9-bit precision internally externally generated video sync signals on-chip SDRAM controller Mbit SDRAM general purpose 16-/32-bit Extension Interface (EBI) configurable high speed data interface connect either IEEE 1394 link device, IEEE 1284 interface, external device like SCSI that supports Mbps data rate 4-wire UART data ports supporting 115.2Kbps rate, 2-wire UART data port supporting 9.6Kbps rate 7816-3/NDC Smart Card interface master/slave interface programmable input port programmable output port four dedicated general purpose pins five multiplexed pins which configured general purpose pins volt device with volt
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Functions
`AV7110 packaged BGA. Table list names their descriptions. Multiplexed pins (muxed pins) those whose definitions selected user using APIs. example, there need SCVccDetect signal smart card interface box, SCVccDetect configured become general purpose IO3.
Table `AV7110 Pins
Name Transport Parser Description
DATAIN[7:0] DCLK PACCLK BYTE_START DERROR
Data Input. first transport stream Input Data Clock. (Note maximum frequency MHz. Packet Clock. Indicates valid packet data DATAIN. Byte Start. Indicates first byte transport packet DVB. Data Error, active high. Indicates error input data. used.
EXTRW
Extension
EXTOE/EXTACTIVE
EXTWAIT EXTADDR[24:0] EXTDATA[31:16] EXTDATA[15:0]
Extension Read/Write. Selects read when high, write when low. Active low, user programmable EXTOE: default mode, asserted only during read cycles EXTACTIVE: asserted read/write cycles Extension Wait Request, active Extension Address bus: byte address Extension Data (16-bit 32-bit EBI) Extension Data 32-bit mode (muxed with other signal pins 16-bit mode) External Interrupt requests (IRQ) active low. External Interrupt request acknowledge, active General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose General Purpose
EXTINT[2:0] EXTACK[2:0] CLK40 RAS1 RAS2 RAS3
(muxed with SCVccDetect)
(muxed with EXTDATA[15]) (muxed with EXTDATA[14]) (muxed with EXTDATA[13]) (muxed with EXTDATA[12])
40.5 Clock output extension HSDI interface Chip Select Selects EPROM Chip Select Chip Select Chip Select Chip Select Chip Select DRAM Address Strobe DRAM Address Strobe (for 32-bit support) DRAM Address Strobe (for DRAM module fixed address partition).
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Name UCAS LCAS
Description DRAM Column address strobe upper byte DRAM Column address strobe lower byte
High Speed Parallel Data Interface (See Table Section details) HSDI_DATA[7:0] Data HSDI_SIG1 HSDI_SIG2 HSDI_SIG3 HSDI_SIG4 I/O, HSDI_SIG5 I/O, HSDI_SIG6 HSDI_SIG7 HSDI_SIG8 HSDI_SIG9 HSDI_STATUS[1:0] Signals indicate which three device interfaces (1394, External DMA, 1284) active Smart Card Interface
SCDET1 SCDET2 SCRESET SCCLK SCVppEN SCVccEN SCDATAIO SCSEL
SCVccDetect
Smart Card Detect Card (programmable polarity) Smart Card Detect Card (programmable polarity) Smart Card Reset. Smart Card Clock. Smart Card enable (programmable polarity) Smart Card enable (programmable polarity). Smart Card data Input Output. Smart Card selection signal: Smart Card Selected, High Smart Card Selected. Smart Card detect input signal (for mode). (muxed with IO3)
IRIN IROUT
Communications Processor
Infra-Red sensor input Infra-Red sensor output. UART port Data Input UART port Data Output UART port RTS. UART port CTS. UART port UART clock output UART port2, Data Input UART port2, Data Output UART port RTS. UART port CTS. UART port3, Data Input UART port3, Data Output Interface Serial Data, open drain Interface Serial Clock, open drain
UART_DI1 UART_DO1 UART_RTS1 UART_CTS1 UART_CK16 UART_DI2 UART_DO2 UART_RTS2 UART_CTS2 UART_DI3 UART_DO3
IICS_SDA IICS_SCL
SDATA[15:0] SADDR[11:0] SRAS SCAS
SDRAM Interface
SDRAM Data bus. SDRAM Address bus. SDRAM Address Strobe SDRAM Column Address Strobe
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Name SDOMU SDOML SCLK SCKE SCS1 SCS2
Audio Interface VCXO
Description SDRAM Write Enable SDRAM Data Mask Enable, Upper byte. SDRAM Data Mask Enable, Lower byte. SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Chip Select
PCMDATA LRCLK PCMCLK ASCLK SPDIF APLL_LOCK
Data audio output. Left/Right Clock output audio data. Clock (for Input Note Audio Serial Data Clock SPDIF audio output Remains active while Internal Audio stable.
CLK27 VCXO_CTRL CLK_SEL
Clock input from external VCXO (Note Digital pulse output external VCXO Control. Clock select: input clock, High input clock.
Digital Video Interface YCOUT[7:0] YCCLK YCCTRL[1:0] TEXTEN
4:2:2 digital video output. (muxed with EXTDATA[7:0]) digital video output clock. (muxed with EXTDATA[8]) Digital video output control signals (muxed with EXTDATA[11] EXTDATA[10] respectively) Teletext window signal active during Teletext lines. (muxed with EXTDATA[9])
NTSC/PAL Encoder Interface VSYNC HSYNC OSD_ACTIVE RC_OUT BIAS_RC GY_OUT BIAS_GY B_OUT BIAS_B Y/COMP_OUT BIAS_COMP COMP[3:0] VREF Device Control
Vertical synchronization signal Horizontal synchronization signal Active when data being output video (active high) video signal Output. Bias terminal. Green video signal Output. Green Bias terminal. Blue video signal Output. Blue Bias terminal. Composite video signal Output. Composite Bias terminal. Compensation-capacitor terminals. [BGRC=3:0] Voltage reference.
RESET TRST test
Reset, active JTAG Data Input. tied high left floating. JTAG Clock. Must tied normal operation. JTAG Test Mode Select tied high left floating. JTAG Test Reset, active low. Must tied connected RESET normal operations. JTAG Data Output Reserved Test, ground when
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Name
Description
Power VDD2_5V VDD3_3V AVCC_CPLL AGND_CPLL AVCC_ APLL1 AGND_ APLL AVCC_ APLL AGND_ APLL AVCC_GY AGND_GY AVCC_RC AGND_RC AVCC_B AGND_B AVCC_COMP AGND_COMP Note supply core chip. tolerance. Digital supply chip. tolerance. Digital Ground. Analog supply. tolerance. Clock Analog Ground Clock Analog Supply Audio PLL1 Analog Ground Audio PLL1 Analog Supply Audio PLL2 Analog Ground Audio PLL2 Analog Supply GY_OUT Analog Ground GY_OUT Analog Supply RC_OUT Analog Ground RC_OUT Analog Supply B_OUT Analog Ground B_OUT Analog Supply COMP_OUT Analog Ground COMP_OUT
These signals Schottky inputs
Types
pins power input mode. outputs 3.3V output will require external level shifters interface with devices. digital inputs/outputs comply with normal standard: 2.0Vmax, 0.8V min, 0.4V min, 0.4V max, specified source/sink currents.
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Architecture
Functional Block Diagram
Figure shows functional block diagram TMS320AV7110.
Digital Video Output
Transport Bitstream from Front
External System Memory
NTSC/PAL Encoder
RGB, Composite Video
Traffic Controller Video Decoder
HSDI
1394 1284
Audio Decoder
Audio Output SPDIF Output
Comm. Processor
Extension Interface
ARM/ Thumb
Data
Smart Card UART (three) JTAG GPIO
Figure `AV7110 Block Diagram Overview
Figure shows overall memory `AV7110.
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Comments
Address FFFF FFFF CE00 0000 CDFF FFFF
Content USED
General Description
Unprotected with some Supervisor only access sub-regions CC00 0000 CBFF FFFF
SDRAM MBytes)
SDRAM Memory Section
USED
A200 0000 A1FF FFFF A000 0C00 A000 0BFF A000 0000 9FFF FFFF 9E00 0D34 9E00 0D33 9E00 0000 9DFF FFFF 7400 0000 73FF FFFF 7200 0000 71FF FFFF 7000 0000 6FFF FFFF 6E00 0000 6DFF FFFF 6C00 0000 6BFF FFFF 6A00 0000 69FF FFFF 6800 0000 67FF FFFF 6600 0000 65FF FFFF 6400 0000 63FF FFFF 6200 0000 61FF FFFF 3A00 0000 39FF FFFF 3800 0000 37FF FFFF 3600 0000 35FF FFFF 3400 0000 33FF FFFF 3200 0000 31FF FFFF 3000 0000 2FFF FFFF 2E00 0000 2DFF FFFF
Reserved
FIQ/BIT access only (protected)
SRAM (CPU) Chip SRAM Reserved
FIQ/BIT access only (protected)
SRAM
USED
Supervisor access only (protected)
NTSC/PAL Encoder
Supervisor access only (protected)
BitBlt
Supervisor access only (protected)
FIQ/BIT access only (protected)
Audio Decoder Hardware Registers Memory Region (See Register descriptions Section
FIQ/BIT access only (protected)
Video Decoder
Supervisor access only (protected)
FIQ/BIT access only (protected)
FIQ/BIT access only (protected)
FIQ/BIT access only (protected with some User accessable sub-regions)
HDSI
USED
USER Access (un-protected)
USER Access (un-protected)
USER Access (un-protected)
USER Access (un-protected)
Space (Section
USER Access (un-protected)
USER Access (un-protected)
DRAM
USER Access (un-protected some Supervisor only sub-regions 8-bit write access) 2C00 0000 2BFF FFFF 0200 0000
USED
Figure `AV7110 Memory
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3.2.1 Transport bit-stream processing
`AV7110 accepts transport bit-stream from output Forward Error Correction (FEC) device with maximum (burst) throughput 72.8 Mbits/s Mbytes/s (60Mbps average over transport packet). Transport Packet Parser (TPP) `AV7110 processes header each packet determines whether packet should discarded, further processed CPU, packet only contains relevant data needs stored without intervention from ARM. sends packets requiring further processing containing relevant data through Traffic Controller (TC) internal RAM. also activates deactivates decryption engine (ECD) based content individual packet. conditional access keys stored local table managed special firmware running CPU. data transfer from Data done DMA. Further processing packet done firmware, which activated interrupt from after completion packet data transfer. types transport packets stored Data managed FIFO. pure data which routed SDRAM without intervention from ARM, other packets that need further processing. Within interrupt service routine, checks FIFO packets that need further processing, performs necessary parsing, removes header portion, establishes transferring payload data from Data SDRAM. re-packs data gets voids created header removal. Together with ARM, also handles Program Clock Reference (PCR) recovery with external VCXO. will latch transfer internal system clock upon arrival packet which contains PCR. After further processing packet identifying system clock, calculates difference between system clock from bit-stream actual system clock time packet arrives. Then, filters difference sends through 8-bit Sigma-Delta control external VCXO. will drive VCXO center frequency during start-up enabled API, after channel change when there incoming PCR. hardware capable detecting packets lost from transport stream. With error concealment audio video decoders `AV7110 minimizes effect lost data.
3.2.2 Audio Video data processing
After removing packet headers other system related information, both audio video data stored external SDRAM. video audio decoders then read bit-streams from SDRAM process them according standards. chip decodes MPEG-1 MPEG-2 main profile main level video Layer MPEG-1 MPEG-2 stereo audio. This includes abnormal cases such discontinuity reference clock packet continuity counters well splicing. Both Video Audio decoders synchronize their presentation reconstructed data using transmitted Presentation Time Stamps (PTS) their local system clock. local system clock continuously updated ARM.
Software System Overview
Software `AV7110 divided into three sections: Firmware, API, user application software. first section, firmware, masked into internal `AV7110. This software supplied Texas Instruments used level control hardware bit-stream de-multiplexing `AV7110. user application software resident external memory contains software written application programmer. user application software communicates with firmware through Application Programming Interfaces (APIs). These APIs contained external ROM. API's written provided form Time Support Library (RTSL). `AV7110 firmware comprises collection interrupt (FIQ) service routines supervisor mode run-time support programs. This software isolates application software from direct interaction with hardware.
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Figure shows high level block diagram complete software system. lowest level, each hardware component firmware module associated with module consist Initialization code executed processor reset Interrupt Service Routines executed from interrupt associated hardware module run-time support library provides application programming interface user application software. run-time modules written invoked from supervisory mode. This prevents software running user mode from interfering with built-in firmware. Functionally, firmware consists several software processes that self contained runtime operate most part, independently asynchronously. Because nature processing complex input stream, processes interrupt driven. interrupt priorities determine processing sequence, de-multiplexed input stream packet information determines data path through system. There only minimal inter-process dependency, which eliminates need software control-flow process. inter-process dependencies handled proper structuring interrupt process terms priorities multi-level processing.
Application Software
Real Time Operating Systems
chip
Firmware control
Firmware Hardware
Graphics Traffic Controller Comm Processor
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Run-time Support Library
Figure Software block diagram
MPEG
Cond. Access
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Features
Runs 40.5 Supports byte (8-bit), half-word (16-bit), word (32-bit) data types Reads instructions from on-chip from Extension switch between (32-bit) Thumb (16-bit) instruction mode 32-bit data 32-bit address lines processing modes interrupts,
32-bit processor running 40.5 associated firmware provide following: initialization management hardware modules service selected interrupts generated hardware modules ports application program interface (API) users develop their applications on-chip SRAM (also referred Internal Data this document) provides space necessary `AV7110 properly decode transport bit-streams without losing packets. run-time support library (RTSL) user application software located outside `AV7110. Details firmware RTSL provided separate software specification document. `AV7110 32-bit RISC processor, ARM7TDMI/Thumb, which capability execute instructions 32-bit format clock frequency 40.5 MHz. regular instructions exactly word (32-bit) long, data operations only performed word quantities. LOAD STORE instructions however, transfer either byte, half-word word quantities. Thumb uses same 32-bit architecture with 16-bit instruction set. That retains 32-bit performance reduces code size with 16-bit instructions. With 16-bit instruction, Thumb still gives performance running instructions from 32-bit memory. Thumb used interchangeably, throughout this document.
Block Diagram
uses LOAD STORE architecture; i.e. operations registers. different processing modes with 32-bit registers visible user mode. Thumb state, there only registers available user mode. high registers still accessed through special instructions this case. instruction pipeline three stage, fetch decode execute, most instructions only take cycle execute. Figure shows data path processor core.
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B-Bus Register Bank
Barrel Shifter
A-Bus Booth Multiplier
ALU-Bus
Figure Core Data Path Resource management
responsible managing hardware software resources `AV7110. power verifies existence size external memory. Following that, initializes hardware modules setting control registers tables then resetting data pointers. then executes default firmware from internal transfers control application software. run-time library routines provide access firmware hardware user application programs. application programs stored external memory attached Extension Bus. During normal operation, constantly responds, based programmable priority, interrupt requests from hardware modules devices Extension Bus. types interrupt services include transport packet parsing, program clock recovery, traffic controller service requests, service data transfer requests from Extension Communication Processor, service requests from Audio/Video decoder.
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Traffic Controller (TC)
Features
Manages interrupt requests Authorizes manages transfers Provides SDRAM interface Manages Extension Provides memory access protection Manages data flow between processors memories from internal Data Data to/from Extension SDRAM from internal Data Audio Video Decoder from SDRAM SDRAM from internal Data High Speed Data Interface from internal Data Generates chip selects (CS) internal modules devices Extension Generates programmable wait states devices Extension Provides breakpoint registers 64x32-bit patch space Figure depicts data flow managed
SDRAM
Palette Mixer
MPEG Audio Video
HSDI
Extension Core
32-bit Program 32-bit Data
Vectors
Figure Traffic Controller Data Flow
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SDRAM Interface
SDRAM must 16-bits wide. `AV7110 provides control signals SDRAMs. combination Mbit SDRAMs used, provided they total least Mbits. Other supported sizes configurations are: Mbit Mbit SDRAM Mbit Mbit Mbit SDRAM Mbit Mbit SDRAM SDRAM must operate clock frequency. After power reset, `AV7110 issues Mode Register (MRS) Cycle configure SDRAM. format fixed automatic. does this holding SRAS, SCAS, SWE, while placing input mode word value A9-A0 (SADDR[11:0] 0000 0011 0111). This forces Read Latency Serial operation sets burst length maximum. choosing SDRAM, parameters Table represent some critical requirements found vary most with SDRAM manufacturers. Mbit TMS626162 SDRAM recommended with `AV7110 meets these requirements.
Table SDRAM Selection Requirements
PARAMETER (Note Access time, data REFR command ACTV, MRS, REFR, SLFR command; ACTV command ACTV, MRS, REFR, SLFR command; Self-refresh exit ACTV, MRS, REFR, SLFR command tRAS tRCD tRRD tRWL ACTV command DEAC DCAB command DEAC DCAB command ACTV, MRS, SLFR, REFR command ACTV command READ command ACTV command bank ACTV command other bank Final data DEAC DCAB command DEAC DCAB READ Bank deactivate (precharge) Deactivate banks Column-address entry/read operation Column-address entry/write operation Read latency UNIT
Note Command mnemonics REFR Auto refresh ACTV Bank activate Mode-register SLFR Self-refresh entry
Timing diagrams various cycles given Section 17.2. These represent more detailed timing parameters SDRAM interface `AV7110. access SDRAM byte, half word, single word, continuous block, video line block, macroblock. interface also supports decrement mode bitBLT block transfers. chip selects correspond following address ranges: SCS1 0xCC00 0000 0xCC1F FFFF SCS2 0xCC20 0000 0xCDFF FFFF During decoding, `AV7110 allocates SDRAM NTSC modes according default layouts shown Figure Figure respectively. Address pointers Audio Buffer, Video Buffer, B-Frame primary Space SDRAM partitioning (Shaded regions Figure Figure configurable API; hence, actual layout customized. Note that more space obtained synchronizing video decoder VSYNC signal thus reducing Video Buffer, storing decoded pictures reduced resolution reduce B-Frame storage (the figures show Frame reduction), using DRAM overflow portion video input buffer which would reduce Video Buffer size. Refer Section more details.
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Address
CDFF FFFF CC40 0000 CC3F FFFF
Content
Reserved
Size
Comments
Expansion Memory Region (OSD/User Data)
CC20 0000 CC1F FFFF CC1F E000 CC1F DFFF CC1A A200 CC1A A1FF CC15 3100 CC15 30FF CC10 7200 CC10 71FF CC08 8900 CC08 88FF CC00 A000 CC00 9FFF CC00 1000 CC00 0FFF CC00 0400 CC00 03FF CC00 0000 Bytes, Bits This default size vary based application Pointers Tables FIFOs Video Microcode 36,864 First Reference Frame 518,400 506.25 Second Reference Frame Frame 311,040 303.75 (0.6 Frame Size) 518,400 506.25 other 356,608 348.25 Video Buffer 2,748,416 335.5 Audio Buffer 65,536
Table through Table
Figure Default Memory Allocation SDRAM (NTSC)
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Address
CDFF FFFF CC40 0000 CC3F FFFF
Content
Reserved
Size
Comments
Expansion Memory Region (OSD/User Data)
CC20 0000 CC1F FFFF CC1F E000 CC1F DFFF CC1A A200 CC19 C1FF CC19 4E00 CC19 4DFF CC13 9C00 CC13 9BFF CC0A 1E00 CC0A 1DFF CC00 A000 CC00 9FFF CC00 1000 CC00 0FFF CC00 0400 CC00 03FF CC00 0000 Bytes, Bits This default size vary based application Pointers Tables FIFOs Video Microcode 36,864 First Reference Frame 622,080 607.5 Second Reference Frame Frame 373,248 364.5 (0.6 Frame Size) 622,080 607.5 other 87,040 Video Buffer 2,748,416 335.5 Audio Buffer 65,536
Table through Table
Figure Default Memory Allocation SDRAM (PAL)
addresse range from 0xCC000000 0xCC000FFF contains decoded bitstream information, error statistics monitor information, Commands Flags that provide communication channel between Video Decoder. relative addresses these locations defined Table through Table
Table Decoded Bitstream Information
Byte Address Name Sequence Header defined ISO/IEC 13818-2 0x000C00 horizontal_size_value 0x000C04 vertical_size_value 0x000C08 aspect_ratio_information 0x000C0C frame_rate_code 0x000C10 bit_rate_value 0x000C18 vbv_buffer_size_value 0x000C1C constrained_parameters_flag 0x000C20 load_intra_quantizer_matrix 0x000C24 load_non_intra_quantizer_matrix Sequence Extension defined ISO/IEC 13818-2 0x000C60 profile_and_level_indication
Usage
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Byte Address Name Usage 0x000C64 progressive_sequence 0x000C68 chroma_format 0x000C6C low_delay 0x000C70 frame_rate_extension_n 0x000C74 frame_rate_extension_d Sequence Display Extension defined ISO/IEC 13818-2 0x000C80 video_format 0x000C84 colour_description 0x000C88 colour_primaries 0x000C8C transfer_characteristics 0x000C90 matrix_coefficients 0x000C94 display_horizontal_size 0x000C98 display_vertical_size Group Pictures Header defined ISO/IEC 13818-2 0x000CA0 first bits time_code stores time_code_hours, time_code_minutes 0x000CA4 rest bits time_code stores time_code_seconds, time_code_pictures 0x000CA8 closed_gop broken_link Picture header defined ISO/IEC 13818-2 0x000CC0 temporal_reference 0x000CC4 vbv_delay
Table Error Statistics Monitor Information
Byte Address 0x000510 0x000514 0x000518 0x000544 0x000548 0x000184 0x000188 0x000194 0x000198 0x00019C
Name
SCR_Monitor RATE_BUF_RPTR RATE_BUF_WPTR TOTAL_SKIP_PICS TOTAL_REPEAT_PICS ERRORS_IN_SLICE ERRORS_NOT_IN_SLICE PIC_ERROR_COUNT SEQ_ERROR_COUNT VLD_ERROR_COUNT
Usage
value time picture decode read pointer buffer time picture decode write pointer buffer time picture decode total skipped pictures since last channel switch power total repeated pictures since last channel switch power accumulated error slice layer; reset power channel change accumulated error outside slice layer; reset power channel change accumulated error within picture; reset each picture accumulated error within sequence; reset each sequence accumulated error variable length decode; reset power channel change
Table Flags Commands
Byte Address 0x000FA8
Name
DISABLE_USER_SYNC
Usage
default mode; given application video synchronization disable synchronization using default mode; apply Pan_Scan 16:9 source video disable Pan_Scan 16:9 source video FIFO normal commands like Play, Decimate etc. Video Command FIFO command like Reset NewChannel higher priority should this location read pointer Command FIFO write pointer Command FIFO
0x000FC4 0x000400 0x0004FC 0x000500 0x000F00 0x000F04
DISABLE_PAN_SCAN CMD_FIFO_START CMD_FIFO_END HIGH_PRIORITY_CMD CMD_FIFO_RPTR CMD_FIFO_WPTR
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Byte Address 0x000FA0
Name
DECIMATION_CMD
Usage
Designated location decimation commands
Prioritized Interrupts
Interrupt requests generated from internal modules like TPP, OSD, decoder, Communication Processor, devices Extension Bus. Some requests data transfers internal RAM, whereas others true interrupts CPU. handles data transfers, provides services true interrupts. interrupts grouped into FIQs IRQs. firmware uses FIQs; application software uses IRQs. priorities FIQs managed firmware while those IRQs managed application software.
Managing transfer
`AV7110 provides capability facilitate large block transfers between memories buffers. burst length multiple bytes) DMAs independently selectable 6bit registers with API. This provides burst value from bytes. SDRAM used store system-level tables, video audio streams, reconstructed video images, data, video decoding codes, tables, FIFOs. internal Data stores temporary buffers, window attributes, keys conditional access, other tables buffers firmware. manages types transfers, only General Purpose (GPDMA) accessible application software. DMAs initiated TPP, video decoder, audio decoder, module inaccessible. GPDMA includes ARM-generated bitBLTgenerated DMAs. accept GPDMAs given time. from Data Extension (and vice versa) byte aligned. Table describes allowable GPDMA transfers.
Table GPDMA Sources Destinations
Transfers Allowed Hardware SDRAM SDRAM Data Extension HSDI Data Extension HSDI
Note that while there direct transfer between Extension memories, HSDI SDRAM. user general DMAs internal Data intermediate step this process. Alternatively, provided transfer data between these interfaces. This accomplished using this internal Data DMAs.
Video/Audio Buffer Monitoring support
continuously monitors fullness video audio input buffers. overflow underflow occurs, firmware alerted that corrective action taken timely manner. Alternatively, application software periodically inspect (read access) read/write pointers circular video audio input buffers take preemptive actions overflow/underflow deemed imminent. Moreover, also keeps number bytes video data being sent video decoder wrap-around counter. This byte-count used firmware accurate video synchronization.
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Transfer Video/Audio Data from High Speed Data Interface (HSDI) SDRAM
With APIs, possible general purpose (GPDMA) 'AV7110 feed audio/video data from HSDI audio/video circular buffers SDRAM. Although recommended, possible this from application software well. Given restricted traffic through Transport Packet Parser (TPP, Section 6.1), possible transfer low-frequency Elementary Stream Video Data using appropriate API. Likewise, similar Audio Elementary Stream data transferred. processing done this mode. Also, application software manages data types coming into HSDI. Management audio video circular buffers will however handled automatically hardware this case. When there other Audio/Video data traffic, transfer mechanism handled differently. When audio video played from HSDI, same type data cannot demultiplexed from incoming stream hardware. sets transfer data from HSDI called from application software.
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MPEG Transport Decoder (TPP)
module 6.1.1 Features
Parses transport streams Accepts stream either from transport parser input from 1394 interface Provides filtered decrypted encrypted packets directly 1394 interface
Maximum Input rate (peak) Transport parser input 72.8Mbps Maximum Input rate (average over transport packet) Transport parser input 60Mbps Maximum Input rate through 1394 interface. 64.8Mbps Video rate 15Mbps audio rate 1.13Mbps Minimum time between transport packets (providing input rate less than average rate) Maximum number PIDs that filtered Maximum number PIDs that descrambled. Maximum number pairs keys descrambler. Recording mode through 1394 interface full transport stream without descrambling full transport stream with PIDs descrambled descrambled PIDs
6.1.2 Description
Transport Packet Parser (TPP) `AV7110 filters header each packet according decides whether packet should discarded, further processed CPU, stored without intervention from CPU. start discards data until firmware enables reception. Individual encrypted channel data then ignored until first control word received until firmware indicates that data acceptable. filter different PIDs time. packets requiring further processing containing relevant data sent internal Data RAM. also activates deactivates European Common Descrambler (ECD) hardware based content individual packets under control. pairs Conditional Access (CA) keys stored TPP. data transfer from internal Data done automatically. Transport packets containing only audio video payloads automatically transferred proper external SDRAM memory buffer space DMA. Other packets that require further processing transferred buffer, issued CPU. Within interrupt service routine, firmware checks FIFO that contains packets further processing. then performs necessary parsing, removes header portion, establishes transferring payload data from internal Data appropriate destination. also detects packets lost from transport stream. Together with error concealment audio/video decoder, minimizes effect lost data. Along with CPU, handles Program Clock Reference (PCR) recovery control external VCXO. latches transfers internal system clock upon arrival packet containing PCR. Firmware, through interrupt handling routine (FIQ), performs minimal filtering PCRs control external 27MHz VCXO. Application software perform more extensive filtering. Figure shows example circuit external VCXO. output from `AV7110 pulse width modulated signal with resolution levels.
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HVU359TRF Vari-Cap
HVU359TRF Vari-Cap
VCXO_CTRL
CLK27
Figure Example Circuit Clock Generation 6.1.3 Conditional access Descrambling processing
`AV7110 contains full implementation European Common Descrambler (ECD) hardware. descrambling incoming data performed automatically with minimum intervention CPU. module detects which transport packets scrambled, either program elementary stream (PES) transport stream level, routes data through necessary. stores descrambler keys locally automatically selects correct specific PID. sets keys stored table ECD. possible more than same key. descrambler keys derived conditional access software using command packet from bit-stream.
6.1.4 Transport Parser Input Interface
`AV7110 accepts transport packet data from front such Forward Error Correction (FEC) unit. Data input byte time using DCLK. PACCLK indicates when data valid. BYTE_START signals first byte byte packet. interface compatible with common Conditional Access. diagram Figure shows input timing this interface.
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DCLK Input
Data Valid
PACCLK Input
Byte Byte Byte Byte Byte Byte Byte
DIN0-7 Input
Byte_Start Input
Derror
Derror only sampled during this period
Figure Input Interface Timing
DCLK edge programmable; PACCLK, BYTE_START, DERROR level programmable. Figure shown with default levels. maximum burst rate transport parser interface 72.8Mbps. more detailed timing diagram included Section 17.7 reference.
Table Transport packet Input interface description
DATAIN[0.7] DCLK PACCLK Parallel data input Data clock. Runs rate which bytes sent `AV7110 D0-D7. (max 9.1MHz) Programmable, edge triggered; default mode rising edge triggered. Packet clock. Level programmable, default active high. Indicates valid data bytes D0D7. bytes transport packet consecutive, which case PACCLK high whole duration transport packet. Certain clocking strategies adopted require there gaps more byte times between some consecutive bytes within and/or between transport packets. this case PACCLK more byte times indicate data bytes that should ignored. Valid during first byte each transport packet D0-D7. edge this signal synchronous with that DATAIN. Level programmable, default active high. This sampled `AV7110 during byte header. signal same meaning Transport Error transport packet header. transport enable error status register when this signal detected, `AV7110 discards packet. During recording, such packet always transferred 1394 port with Transport Error header signal error. This DERROR must detected High Byte error detected.
BYTE_START DERROR
Hardware Section Filtering
hardware section filtering module comprises following elements: byte) filters byte) mask Match Data registers Match Result Registers Reset Control Register Status register Start Filter Enable Stop Filter Enable
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comparisons, irrespective number active filters, require machine cycles with result available 33'rd cycle.
6.2.1 Memory
hardware section filtering module uses following quick reference memory mapped locations: Name HW_FILT_CONTROL HW_FILT_STATUS MATCHDATA MATCH_RESULT_REG HW_FILT_BASE HW_MASK_BASE Description Write this register causes initialization Indicates result search, contains done, found bits index first match Register write bytes data compare against filter values using masking Bitmapped index matches data filter Starting address filter members bytes) Starting address filter masks bytes)
6.2.2 Filter hardware definition
filter hardware consists tables containing filter compare against mask apply both data compared filter. addition hardware engine contains attribute word each element filter table. Filter values, filter masks attributes related tables addressed same index respective tables shown Figure Filter Data Very Word word1 word2 Filter Mask Very Word word1 word2
Filter Number
High Word word0
Attrib Data word3
High Word word0
Attrib Data word3
word0
word1
word2
word3
word0
word1
word2
word3
Figure hardware filter layout 6.2.2.1 Filter Data Memory Addressing
filter entries comprised three WORDs filter data plus WORD attribute information. Storage entries memory mapped follows. starting word address filter #define HW_FILT_BASE (ulong high word, upper bytes filter data, stored word remaining bytes filter data word Word contains attribute data, right justified. attribute data field, enable non-maskable filter. Word empty.
6.2.2.2 Filter Attribute Definition
Difference Filter Control non-maskable filter byte Enable Flag Index
[5:0] Index
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index into filter table (PID CAM) that allows application attach each filter entry given active PID. index bits, entries. Currently, AV7110 hardware only supports separate PIDs. additional indexes available potential future AV7XXX implementations using this filter. Enable Flag: indicates filter inactive. comparisons performed associated filter data. indicates filter enabled (active). Filtering will performed each valid section. [15:8] Non-Maskable Filter Byte Eight field that loaded with filter data. These eight bits cannot masked. [31:16] Difference filter control bits. When diffence filtering enabled byte, that byte match bits filter different from match register. enables diffence filtering byte enables byte etc.
6.2.2.3 Filter Mask Memory Addressing
mask entries memory mapped follows. starting word address filter defined #define HW_MASK_BASE (ulong mask entry corresponds each filter. mask applied both filter memory words input match data words before they compared. mask position indicates that corresponding bits filter input match data words should compared. mask position indicates that corresponding bits filter input match data words ignored comparison.
6.2.3 Filter Match Data Register definition
sets input match data registers available. sets registers enable search taking place same time that next search data readied. switching Filter Match Data Register from register other automatic. After Attribute word written match data register, subsequent writes Filter Match Data Register will load other register. Match Data Attribute should last word written because write this register initiates search. match data registers contain bytes data that loaded attribute match word. match data normally extracted from bytes 5-10 PSI/SI section header. Data extraction performed firmware, from Transport Packet stored into internal SRAM buffers. attribute value index Transport Packet, from which section data extracted. Bits match attribute word contains byte non-maskable search data. Match High Word Match Word Match Word Match Attribute Word
Match Attribute word Unused Bits
Non-maskable search byte
Index
[0:5] Index index. Index Match attribute compared with Index filter table indicate which filter entries perform comparison.
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[8:15] Non-maskable search data These search bits will compared against bits each filter attribute word. These bits Match Attribute Word Filter Attribute Word maskable. [6:7,16:31] used, must written 0's.
6.2.3.1 Filter Match Data Register Memory Addressing
sets registers enable search taking place same time that next search data readied. After Attribute word written match data register, subsequent writes Filter Match Data Register will load other register. #define MATCHDATA (ulong matching operation performed hardware follows: i=1,32 MATCH[i] enable_bit[i] (filter_PID_index[i] match_data_PID_index) &((filter_data[i] mask[i])==(match_data mask[i]) Although match data register mapped into address space CPU, reality there them operating "flip-flop." While used matching hardware compare match data with each entry filter memory, other available loading match data. full comparison duration cycles 40.5 MHz) "masked" actual loading data. software must ensure that second search started writing Match Data Attribute Register until current search done. filter status word contains done flag.
6.2.4 Match Result Register Definition
Depending type filtering being performed possible have either multiple filter matches given PID_Index. Multiple matches caused when application generates overlapping definitions, separate tasks request exactly same filter data. result Match Register will represented result, where matches search will indicated corresponding position. example, Filter matched, result register (0x0000 0001). match register follows:
6.2.4.1 Match Result Memory Addressing
Match Result register mapped #define MATCH_RESULT (ulong
6.2.5 Status Register Word Definition
status register polled indicate completion search. defined status register. most significant byte always contains index first filter match. This specifically used cached filters, where there will ONLY match section. this case index will read instead pattern stored Match Result Register.
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When search initiated input match register, done '0'. Upon completion search, done '1'. Filter Index used found done
done bit. Indicates completion filtering operation. found bit. `1', indicates that Filter Index valid. Also indicates that least result vector set. [2:24] used. [25:31] Contains index first filter match found
6.2.5.1 Status Register Memory Addressing
#define HW_FILT_STATUS (ulong
6.2.6 Filter Reset Control Register
filter reset achieved writing control register. This operation resets only hardware filter circuitry. hardware filter only needs reset event catastrophic system failure software crash. control register contains "escape first match" flag. When this control `1', filtering operations stops first match. hardware does through rest filter search further matches. Status Register valid after first match. When escape first match `0', locations filter searched. both cases, Match Result register valid. resets Start/Stop filter settings controls difference mode Local mode: each filter attributes difference byte control Global mode: control register difference byte control global difference control difference mode start/stop reset escape first match filter reset
6.2.6.1 Filter Reset Control Register Memory Addressing
filter reset control register mapped #define HW_FILT_CONTROL (ulong writing pulses internal reset. Following reset, write Match Data Attribute register will initiate search.
6.2.7 Typical software process flow
software algorithm accessing hardware filter needs take account time takes complete search (approx. cycles). Polling completion status register acceptable firmware level, where processing packet (EOP) interrupt extremely time critical. Completion interrupt process cannot extend over microseconds general case. Therefore important search time hardware filter pre-load second match done.
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parallel processing will continue until last data compare loaded from firmware. that time wait last completion used pre-setup some parameters. This parallelism allows zero time loss case needed done. case needed, there processing penalty. typical payload processing sequence using this mechanism could Reset Hardware Load section data Write attributes; while( payload end) move start next section; load section data; next flag; while (filter complete) read result; (next flag) write attributes; reset next flag; if(result match) process result; while (filter complete) read last result process last result Initialize hardware filter state machine load first data into hardware filter start first compare whole payload setup next data load into data compare register don't start search wait previous search complete match search pending start hardware engine free next round
process previous result here setup needed wait previous search complete finish last search process
Note: above algorithm intended functional example only.
6.2.8 load assessment 6.2.8.1 Introduction
load filtering SI/PSI data will depending following factors: Bit-rate incoming data Number sections payload Number channels perform filter
Sample current broadcast requirements are: Maximum bit-rate Mb/s (3486 packets bytes each) Maximum sections payload Maximum filters Only carrying electronic program guide information
Expected increases above requirements (near) future: Maximum sections payload (including "start/stop" filters) Possible carrying this type data
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Texas Instruments implementation hardware assisted filter, there time/CPU load difference between using filter filters PID. Therefore assessment below number filters will taken into account.
6.2.8.2 Assumptions
Maximum rate filter data does exceed Mb/s Assessments based 100% load available processing (High priority FIQ)
6.2.8.3 load assessment
Data only sections sections 3324 3324 usec usec 49.86 msec 83.1 msec Data sections sections 26596 26596 usec usec 398.94 msec 664.9 msec 39.9 66.5
Packets/second Processing time/packet Processing time
clear from above information, load with sections each, there significant impact average available application use.
Hardware circuit
CRC-32 hardware module available that allows compute verify checksums (for example, CRC-32 PSI/SI data). calculated with following polynomial: Transfer data from DRAM hardware circuit transparent application software. completion processing, interrupt issued requested call.
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Video Decoder
Features
Real-time decoding MPEG-2 Main Profile@Main level MPEG-1 video bit-streams Error detection concealment Internal KHz/27 System Time Clock Sustained input rate Mbps Supports Trick Mode with full size trick mode picture Provides 1/16 decimated size picture Extracts Closed Caption other picture user data from bit-stream pulldown NTSC mode Provides read access video input buffer's read/write pointers Pan-and-scan 16:9 20:9 source material according MPEG syntax Letterbox support High level command interface Synchronization using Presentation Time Stamps (PTS); also supports delay based free synchronization) video playback Supports automatic upsampling display format with polyphase horizontal resampling vertical chrominance filtering (see Table Others done automatically call.
Table Supported Video Resolutions Automatic Up-Sampling
NTSC Source Display Source Display
Description
Video Decoder module receives video bit-stream from SDRAM. also uses SDRAM working memory store tables, buffers, reconstructed images. decoding process controlled RISC engine which accepts high level commands from ARM. that fashion, acting external host initialize control Video Decoder module. output video sent module further blending with data. `AV7110 synchronizes presentation video with audio using transmitted Presentation Time Stamps (PTS) extracted from packets. compares with local system time clock (STC) performs synchronization recovery difference outside user programmable threshold range given follows: threshold threshold synchronization recovery needed, video decoder either redisplays skips frame, depending value. lags, that time displaying current picture already passed, video decoder discards following pictures without decoding them until catches with STC. leads, that time displaying current picture arrived yet, video decoder pauses decoding continuously displays last picture. Section more details.
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Trick Mode
When decoding picture from digital recorder, decoder handle trick modes (decode display frame only. limitation that data whole picture instead several intraslices. Random bits allowed between trick mode pictures. important note that random bits emulate start code, unpredictable decoding display errors will likely occur. trick mode activated scan command (see Table During trick mode decoding, video decoder repeats following steps: searches sequence header followed picture ignores video buffer under-flow error continuously displays decoded frame.
High-Level Commands
Video decoder accepts high-level commands detailed Table
Table Video Decoder Commands
Play Freeze Freeze1 Freeze2 Stop Scan FastForward SingleStep SlowMotion FindIndex FreezeIndex NewChannel Normal decoding Normal decoding continue display last picture (The choice field only Full Frame dependent data stream) Normal decoding continue display last picture (Top field) Normal decoding continue display last picture (Full frame) Stops decoding process. display continue with last picture Searches first picture, decodes displays then continues searching next picture repeats Decode display only pictures. Decode display next picture, then stop. Applicable only when user control input bit-stream. Decode pictures display each picture N-frame times. Applicable only when user control input bit-stream. Generate interrupt when value reached. value, time_code field layer. Freeze picture index value Index value same FindIndex. channel change, video decoder first finishes current display picture. Then, based settings provided through user software, selects what display: pre-setup window blank background. Halts execution current command. bit-stream buffer flushed video decoder performs internal reset Continue normal decoding displaying decimated picture (controlled API) Continue normal decoding displaying decimated picture (controlled API) Turn true size display mode (controlled API). Turn true size display mode (controlled API).
Reset Decimate1/2 Decimate1/4 TS_Display_On TS_Display_Off
Video Decimation Scaling
video decoder contains polyphase filter vertical interpolation filter performing horizontal resampling luma/chroma vertical interpolation support decimation scaling pictures. operation, decoder first loads picture data from video storage space SDRAM internal buffer video decoder. Vertical horizontal filters then applied video data produce 4:2:2 image. video decoder capable producing decimated pictures using decimation dimension, which results reduced areas 1/16. Decimation achieved using field data frame, skipping lines, performing vertical filter smooth decimated image. However this decimation mode does apply when picture displayed letterbox format.
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decimated picture viewed real time. Such decimated picture positioned anywhere screen inserting into window positioning window desired location. picture also scaled vertical horizontal direction allow changes display format (see Figure 11). Various compression ratios vertical direction supported handle vertical scaling required (Table Table NTSC (Table Table 13). Transmitted Format Monitor 16:9 Monitor
Aspect Ratio
adjustment
adjustment
16:9 Aspect Ratio
Scan
Vertical Compression
adjustment
`AV7110
Display Formats
Scan 2.21:1 Aspect Ratio (PAL only)
Scan
Scan
Vertical Compression
Vertical Compression
Vertical Compression
Figure Display Formats `AV7110
full size pictures, scan mode supported 1/16-pel resolution (i.e., full-pel, 1/8-pel). decimated picture scan resolution 1/8-pel decimated picture decimated picture. non-full size pictures, scan mode supported full-pel resolution only.
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Table Scaling Factors monitor format.
Monitor Source Aspect ratio 2.21:1 2.21:1 2.21 Display Type Full Screen Scan Letterbox Letterbox Scan Letterbox Scan V4/5 Source Luminance resolution Horz vert. V1/1 16/9
16/9
Table Scaling Factors 16:9 monitor format.
Monitor Source Aspect ratio 2.21:1 2.21 Display Type Stretched Full Screen Scan Letterbox Source Luminance resolution Horz vert. V1/1 16/9
Table Scaling Factors monitor NTSC format.
Monitor Source Aspect ratio 16:9 Display Type Full Screen Scan Letterbox Source Luminance resolution Horz vert. 16/9
Table Scaling Factors 16:9 monitor NTSC format.
Monitor Source Aspect ratio Display Type Stretched Full Screen Source Luminance resolution Horz vert. V1/1
Free-run VBV-based Display Synchronization
Typically, display decoded pictures synchronized using transmitted internal system time clock (see Section more details). also provided application software instruct video decoder `AV7110 display pictures soon possible (the freerun mode) wait duration specified VBV-delay field each picture header before
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decoding picture. VBV-based display mode synchronization applied display time. Note that change display synchronization mode takes effect only when channel selected.
Memory Usage Reduction
minimum memory configuration, `AV7110 designed work with memory devices: single 16Mbit SDRAM device system data storage (Audio, video data, etc.), 4Mbit DRAM local data storage (private data, information etc.). Table shows what memories used for, bytes. amount memory available applications depends upon mode operation `AV7110. example, letterbox display format used, more memory required store frames hence less space available. Table shows size frame buffer different display formats normal (full) resolution.
Table `AV7110 Memory Usage
Video Input Buffer (theoretical decoder delay display synchronization 229,376 52,000 75,000) split between SDRAM DRAM Audio Lip-sync buffer MPEG frames Video decoder micro-code Internal Tables FIFO's Scratch space frames User application, data private data etc. SDRAM (bytes) 107,000 356,376 DRAM (bytes) 249,376
8,192 1,244,160 36,864 4,096 Table 393,216 Table
Table Storage frames
Display Format Normal resolution (1.0 Frame 622,080 bytes) Portion each B-Frame Memory stored Required (bytes) 0.60 373,248 0.72 447,898 0.78 485,223
Full Screen Letterbox ratio Letterbox ratio
amount available space significantly improved reducing SDRAM space usage during video decoding. combination following options available: Vsync reset, split Video Input Buffer.
7.7.1 Vsync Reset
video input buffer, which located SDRAM, made three components: theoretical rate control buffer whose size specified MPEG-2 video standard (229,376 bytes); buffer space compensate decoder delay (52,000 bytes); additional storage space synchronize video decoder timing with that NTSC/PAL encoder Vsync timing (75,000 bytes). `AV7110, provided allow user applications synchronize video sync pulse video decoder timing channel change. Doing potentially recover 75,000 bytes (15Mbps 40msecs) storage space usage. When Vsync reset activated, display during channel change always blank.
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7.7.2 Split Video Input Buffer
also possible split video input buffer between DRAM SDRAM increase amount SDRAM space available display. When this mode selected, DRAM portion only used overflow buffer. When allocated buffer space SDRAM full, incoming data written directly DRAM. soon memory space available SDRAM, data transferred from DRAM SDRAM automatically. Once overflow buffer DRAM been emptied, incoming data written directly SDRAM again. video decoder always takes data from SDRAM. size buffers each area memory under control. least KBytes Video Input Buffer must located SDRAM video decoder operate properly. minimum total buffer size required from combined SDRAM DRAM 356,376 Bytes. split should changed only when decoder inactive avoid loss data. dedicated channel used automatic transfer data from DRAM SDRAM implement this split buffer scheme. Table shows maximum amount memory bytes) that made available applications when video input buffer split DRAM (1Mbits 1.5Mbits shown) extension bus.
Table Target Memory Space SDRAM Bytes)
internal display sync Decoder Options Video Input Buffer split SDRAM 356,376 356,376 225,304 159,768 DRAM 131,072 196,608 space with 16Mbit SDRAM Letterbox ratio Letterbox ratio Normal Display 0.78 frame 0.72 frame frame 37,241 168,313 233,849 74,566 205,638 271,174 74,216 149,216 280,288 345,824
Configuration Video Decoder 7.8.1 Configuration video display format
`AV7110 processes video with aspect ratios 4:3, 16:9, 2.21:1. also supports display aspect ratio 16:9. Figure details various display formats supported `AV7110, application select specific format using API. following flags, controlled API, used define specific display format. 16:9_DISPLAY: This flag only during power because setting this flag causes automatic hardware reset. display device, default value 16:9 display device This flag time takes effect next sequence start. [default value] Apply Pan_Scan mode when source video 2.21:1, when source video 16:9 display device specified 4:3. [Letterbox mode] Selects letterbox display when source video 16:9 display when source video 2.21 display 16:9. source video 2.21 display 4:3, specific display depends flag LB_PAN_SCAN This flag only applies case where source 2.21:1 output letterbox display only, default value apply scan followed letterbox display
DIS_PAN_SCAN:
LB_PAN_SCAN:
7.8.2 True Size Display Mode
MPEG-2 stream contains types image size information; encoded source image size active display size. Typically, these sizes equal. size information specified
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output display device usually equal largest allowable source image, pixels lines, defined MPEG-2 main profile main level. `AV7110, application software must specify whether display should follow active display size, true size display mode, full screen output display size, default mode. available setting TS_DISP flag indicate true size display mode, specified window host true size video, location true size display value indicates left, right, middle justification, whereas value indicates top, middle, bottom. true size display takes effect start next video sequence. full screen output display size, default mode, active display size information ignored. video decoder automatically adjusts encoder source image size full screen display device. During parsing active display size, video decoder always checks TS_DISP flag. set, then following sequence actions occurs: video decoder compares active display size against previous display size; which normally full screen size. they different, issue interrupt with interrupt status register indicating that active display size different from previous display size. they same continue decoding. video interrupt service routine (ISR) reads active display size from fixed SDRAM location. active display size equals full screen size, issues TS_display_off video decoder disables corresponding window. size different, then sets window with active display size adjusts window location specified pair defined above. interrupt service routine then issues command, TS_display_on, video decoder start True Size display mode. Upon receiving command, video decoder turns automatic size conversion process only sends number pixels equivalent active display size window starting from next available picture. video decoder also converts aspect ratio, needed, with active display size target size.
7.8.3 Video display synchronization mode
2-bit flag, SYNC_MODE, used specify synchronization method video decoder. This flag part channel switch initialization process. meaning this flag defined follows: SYNC_MODE during channel change default value, apply based synchronization free run, disable synchronization synchronization based delay each picture disable reserved
synchroniation
7.8.4 Vsync reset split buffer
VSYNC_RESET VBV_SPLIT flags control status vsync reset split buffer modes, respectively. These flags specified APIs during hardware reset initialization. value indicates mode value"0" indicates OFF. default these flags "0". When VSYNC_RESET screen always goes blank frames during channel change. VBV_SPLIT mode selected, same should also provide size allocated SDRAM, which should smaller than Kbytes.
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Graphics Acceleration
Supports eight hardware windows, which used cursor Displays nonoverlapped windows simultaneously Displays overlapped windows obstructively with highest priority window Provides hardware window-based cursor with programmable size, shape, color (two colors) blinking frequency Provides programmable background color, which defaults black Supports four window formats: empty window decimated video bitmap YCrCb 4:4:4 graphics component YCrCb 4:2:2 CCIR component Supports blending bitmap, YCrCb 4:4:4, YCrCb 4:2:2 with motion video with empty window Supports window mode color mode blending Provides programmable, Color Look table (CLUT) with entries. Outputs motion video mixture with programmable, 4:2:2 digital component format Provides motion video mixture with on-chip NTSC/PAL encoder Each hardware window following attributes: window position: even pixel horizontal position screen; windows with decimated video have start from even numbered video line also window size: from pixel wide (even values only) from lines window base address data format: bitmap, YCrCb 4:4:4, YCrCb 4:2:2, empty bitmap resolution: bits pixel full half resolution bitmap YCrCb 4:4:4 windows bitmap color palette base address blend enable flag levels blending transparency enable flag YCrCb 4:4:4 YCrCb 4:2:2 output channel control Provides graphics acceleration capability with bitBLT hardware
8.1.1 Description
module handles data from different windows blends with video. accepts video from Video Decoder, reads data from SDRAM, produces three sets video output: on-chip PAL/NTSC Encoder another digital output that goes chip. Contents these three sets video output individually chosen. module defaults standby mode, which simply sends video from Video Decoder outputs. After being configured activated CPU, module reads data mixes with video output. responsible turning operations. BitBlt hardware which attached module provides acceleration memory block moves graphics operations. Figure shows block diagram module. various functions described following subsections.
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Analogue CVBS Data FIFO Video Decoder
Analogue
Digital
Component Latch
CLUT Window Attributes
Output Channel Selection
Video Component Latch
Blending Window Selection Display Control
position position
Figure Module Block Diagram 8.1.2 data storage
data variable size. bitmap mode, each pixel bits wide. graphics YCrCb 4:4:4 CCIR YCrCb 4:2:2 modes, takes 8-bit components, components arranged according 4:4:4 (Cb/Y/Cr/Cb/Y/Cr 4:2:2 (Cb/Y/Cr/Y format. case where graphics data needs used OSD, application should perform software conversion Y/Cr/Cb before storing data always packed into 32-bit words left justified. Starting from upper left corner window, data packed into adjacent 32-bit words. dedicated bitBLT hardware expedites packing unpacking data. This allows access individual pixels using internal shifter within module. Table shows fraction full size window (720 576) supported available SDRAM space. This assumes that decoded picture normal display mode (non letterbox).
Table SDRAM Window Size
Decoder Options internal Video Input Buffer split display sync SDRAM DRAM 356,376 356,376 225,304 159,768 131,072 196,608 Fraction full-size window supported window resolution (bits/pel) storage Full-res 0.06 0.18 0.36 0.72 Half-res 0.21 0.63 1.26 2.51 Full-res 0.12 0.36 0.72 1.44 Half-res 0.27 0.81 1.62 3.24 Full-res 0.27 0.81 1.62 3.24 Half-res 0.38 1.13 2.25 4.50 Full-res 0.28 0.83 1.67 3.34 Half-res 0.43 1.28 2.57 5.14
Setting Window
window defined attributes. Besides storing data window into SDRAM, application program also needs update window attributes other setup module described following subsections.
8.2.1 Memory
memory contains locations upper left lower right corners each window. application program needs enable selected windows.
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priority each window determined location CAM. That lower address window always higher priority. order swap priority windows, exchange locations within CAM.
8.2.2 Window Attribute Memory
module keeps local copy window attributes. These attributes allow module calculate address data, extract pixels proper size, control blending factor, select output channel.
8.2.3 Color Look Table
Before using bitmap OSD, application program initialize entry color look table (CLUT). CLUT mainly used convert bitmap data into Y/Cr/Cb components. Since bitmap pixels have either bits, whole CLUT also programmed contain segments smaller size tables, such sixteen separate 16-entry CLUTs.
8.2.4 Blending Transparency
Bitmap graphic 4:4:4 4:2:2 displays blended with MPEG video display when they overlap video display with background color when they overlap MPEG window. window blending enabled, amount blending determined blend factor. Table indicates supported blending levels. Color blending pixel level also supported. This feature available bitmap displays only. color blending enabled, amount blending each pixel determined chrominance components pixel itself: other words, blend factor pixel corresponds values that stored CLUT entry corresponding that pixel. shown Table window blending supports different levels, whereas color blending support either levels, according selected blending mode.
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Table Blending Levels
Blending Type NoBlend ColorB4 ColorB4 ColorB4 ColorB4 ColorB16 ColorB16 ColorB16 ColorB16 ColorB16 ColorB16 ColorB16 WindowB16 WindowB16 WindowB16 Window Blend Factor don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care don't care 0N15 Cb[0] Cr[0] Cb[1] Cr[1] window contribution (Opaque) 1/16 3/16 5/16 (Opaque) 1/16 (N+1)/16 (Opaque) MPEG Video contribution 15/16 13/16 11/16 15/16 (15-N)/16
don't care don't care don't care don't care
don't care don't care don't care don't care
don't care don't care don't care don't care don't care don't care don't care don't care
don't care don't care don't care don't care don't care don't care don't care don't care
hardware also supports transparency mode with bitmap, graphic 4:4:4 4:2:2 displays. transparency enabled, then pixel graphic bitmap display that value allows video displayed. Essentially, valued pixels considered transparent color, i.e. MPEG video underneath background color will show through bitmap. Table shows connection between transparency blending same window.
Table Blending transparency
Transparency Enable Blending Type NoBlend ColorB4 ColorB16 WindowB16 NoBlend ColorB4 Window Blend Factor don't care don't care don't care don't care don't care window contribution depending depending Cb0,Cr0,Cb1,Cr1 depending blend factor pixel value pixel value pixel value else MPEG Video contribution
depending depending Cb0,Cr0,Cb1,Cr1 depending blend factor pixel value pixel value pixel value else
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Transparency Enable
Blending Type
Window Blend Factor don't care
window contribution depending pixel value else depending Cb0,Cr0,Cb1,Cr1 pixel value else depending blend factor
MPEG Video contribution
ColorB16
WindowB16
depending pixel value else depending Cb0,Cr0,Cb1,Cr1 pixel value else depending blend factor
8.2.5 Hardware Cursor
shape programmable cursor 32x24 pixels colors; 64x24 pixels single color) rectangular area provided using hardware window With window cursor always appears other Windows. size, color two), shape, blinking frequency cursor specified APIs. Furthermore, APIs also provided enable vertical (i.e., over X-axis) mirroring and/or horizontal stretching cursor, effectively creating cursor 64x48 pixels colors; 128x48 pixels single color). When hardware window designated cursor, only seven windows available application. hardware cursor used, then application window regular hardware window.
8.2.6 Output Channels
When window enabled, attribute, Disp_Ch_Cntl[2:0], that defines output channel which window displayed. signal OSD_ACTIVE asserted duration when window being output outputs. With appropriate external delay element, this signal used control external analog switch graphics generated `AV7110 with external analog video source. side effect enabling OSD_ACTIVE that CVBS will longer valid. Figure shows connections synchronization mixing with external analog video data. OSD_ACTIVE
`AV7110
HSYNC Analog Video External Analog Switch CVBS
VSYNC
horizontal blanking delay (see Section 17.1 timing) Analog Video different. that case user needs provide external delay synchronize these signals.
Figure Using OSD_ACTIVE Signal External Analog Video
following table shows control output channels:
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Table Module Output Channel Control
Disp_Ch_Cntl [2:0] Channel (4:4:4) Analog matrix MPEG Video MPEG Video MPEG Video MPEG Video Mixed Window Mixed Window Mixed Window Mixed Window Channel (4:2:2) Digital Video Output MPEG Video MPEG Video Mixed Window Mixed Window MPEG Video MPEG Video Mixed Window Mixed Window Channel (4:2:2) PAL/NTSC Encoder MPEG Video Mixed Window MPEG Video Mixed Window MPEG Video Mixed Window MPEG Video Mixed Window
When windows overlapping, possible view both complete windows separate output channels. example, Figure shows display modes which allowed between channels (Channel Channel this example).
Non-overlapped
Video Only NTSC/PAL Encoder Outputs
Full picture
Bottom Overlapped
Digital video Output
Video Only
Full picture
Nonoverlapped
Overlapped
disabled this case.
Figure Output Channels Matrix BitBLT hardware
bitBLT hardware provides faster move block memory from space other. reads data from source location, performs shift/mask/merge/expand operations data, finally writes destination location. This hardware enables following graphics functions: Set/Get Pixel Horizontal/Vertical Line Drawing Block Fill
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Font BitBLTing Bitmap/graphic BitBLTing Transparency
8.3.1 Sources Destinations
allowable source destination memories bitBLT defined Table
Table Source Destination Memories BitBLT
Source Memory Destination Memory SDRAM SDRAM Ext_Bus Memory Ext_Bus Memory
8.3.2 Source Destination Window Formats
types source destination windows supported bitBLT given following table stands half horizontal resolution).
Table Allowable BitBLT Window Formats
Source Window YCrCb 4:4:4 YCrCb 4:4:4 YCrCb 4:4:4_HR YCrCb 4:2:2 Bitmap Bitmap_HR Destination Window YCrCb 4:4:4_HR YCrCb 4:2:2 Bitmap Bitmap_HR
Since bitmap allows resolutions bits pixel, bitBLT will drop most significant bits with when swapping between windows different resolution. half horizontal resolution OSD, horizontal pixel dimension must even numbers. YCrCb 4:2:2 data, drawing operation always 32-bit words, adjacent pixels that align with word boundary.
8.3.3 Transparency
block move operation, block data also made transparent allow text graphic overlay. pixels source data combined with pixels destination data. When transparency turned value source pixel non-zero, pixel written destination. When value pixel zero, destination pixel remains unchanged. Transparency only allowed from bitmap bitmap, from bitmap YCrCb 4:4:4.
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Video Output Interfaces
Analog Video Output NTSC/PAL Encoder module
Supports NTSC G/H, display formats Outputs RGB, Composite video with 9-bit DACs Generates 100/75 format color mode testing Complies RS170A standard Composite signals comply with ITU-R 470-3 ITU-R 471-1 Supports MacroVision Anti-taping function composite video Provides sync signals with option accept external sync signals composite video output either NTSC format default output format powerup PAL. Changing between NTSC mode done which selects output mode NTSC/PAL encoder. Note that Video decoder microcode specific NTSC required proper operation. addition composite video, `AV7110 also provides either analog S-video Luminance, Chrominance) signal analog output with pixel resolution. These signals share pins `AV7110. outputs conform RS170A standard. Table shows various combinations signals available output pins. Selection output done application accessible API.
Table Multiplexed Video Output Definitions
Name CASE Y/COMP_OUT R/C_OUT G/Y_OUT B_OUT Composite Green Blue Video Signal Output onto CASE Composite Chrominance Luminance -CASE Composite -CASE Luminance Chrominance
video synchronization signal pins VSYNC HSYNC `AV7110 digital outputs that default tri-state mode power Internally generated synchronization signals used NTSC/PAL encoder. user select source video sync signals API. internal source selected then VSYNC HSYNC pins configured output pins. output mode, horizontal blanking region programmable range with respect Composite output clock cycles µsec) from default value. MacroVisionversion 7.01 enabled API; default state off. version `AV7110 where MacroVision anti-taping circuitry permanently disabled also available.
Teletext Wide Screen Signaling (WSS) Insertion (PAL mode only) 9.2.1 Teletext insertion into CVBS
`AV7110 supports insertion Teletext signal onto CVBS. Teletext data transmitted packets. responsible processing packets saving them memory until they needed module. Teletext inserted into lines 7-22 320-335 specified `line offset' field data field Teletext only inserted into analog CVBS signal.
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clock period Teletext data should 144nsec Teletext transmission covered document Teletext rate 6.9375MHz 100ppm. Teletext data starts 10.2 µSec after leading edge horizontal synchronization pulse Teletext insertion conforms Teletext spec ITU-R rec. system Each Teletext line contains bytes data bits clock generated `AV7110 bytes data from payload Teletext only inserted mode
9.2.2 insertion into CVBS
data inserted into line only transmission specified ESTI standard 294, `Television systems 625-line television wide screen signaling (WSS) only inserted mode. only inserted into analog CVBS data clock frequency 5MHz
9.2.3 Insertion mode
provided user select Teletext signal inserted internally externally. only inserted internally. Teletext data resolution composite signal internal insertion TEXTEN external insertion 27MHz. Internal insertion: Teletext data inserted on-chip NTSC/PAL encoder into analog CVBS signal. External insertion: Teletext signal externally inserted external video encoder that Teletext insertion capability. allow this mode operation, Teletext signal always output TEXTEN pin. video signal digital (YCOUT[7:0]) Teletext signal TEXTEN compliant with PhilipsSA7182/3 digital video encoder's input requirements. Note that external insertion option available 32-bit mode used multiplexing. Figure shows external insertion Teletext signal.
TEXTEN
`AV7110
YCOUT[7:0] YCCLK
External Video encoder (w/Teletext e.g., Philips' SAA7182/3
CVBS
Figure External Insertion Teletext signal
Closed Caption, Extended Data Services, Video Aspect Ratio Identification Signal Insertion (NTSC mode only)
Closed Caption (CC) Extended Data Services (EDS) transmitted picture layer user data. video decoder extracts information from video bit-stream sends NTSC/PAL encoder module. video decoder also extracts aspect ratio from bit-stream sends which prepares data according Video Aspect Ratio Identification Signal (VARIS) standard, EIAJ 1204. then sends code NTSC/PAL encoder insert data into analog digital video output.
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inserted ASCII code into 21st video line; VARIS codes into 20th video line NTSC. available enable disable insertion.
Digital Video Output
NOTE: This interface supported when 32-bit used multiplexed signals. programmable blanking region available which programmable range +32/-31 YCCLK cycles from default value (Default cycles PAL) configurable API. Figure shows this region 4:2:2 digital video output. Note that this programmability does affect Analog video output signals `AV7110. that user must Analog video output programmable features described section 9.1.
Programmable Region
YCCLK @27MHz 4:2:2 YCOUT HSYNC
4:2:2 Mode
Figure Digital Video Output Timing 9.4.1 Mode Digital Video Output
digital output 4:2:2 component format. content video could either pure video blended combination video OSD. assignments digital video output signals are: YCOUT(8) YCCLK(1) 8-bit Cb/Y/Cr/Y data output clock output
9.4.2 NTSC Mode Digital Video Output
digital output includes video either 4:4:4 4:2:2 component format, plus aspect ratio VARIS code beginning each video frame. video output format programmable user defaults 4:2:2. content video could either pure video blended combination video OSD. assignments digital video output signals follows: 8-bit Cb/Y/Cr/Y VARIS multiplexed data output clock output 2-bit control signals distinguish between Y/Cb/Cr components VARIS code interpretation YCCTRL defined following table. YCOUT(8) YCCLK(1) YCCTRL(2)
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Table Digital Output Control
SIGNALS Component Component Component VARIS code YCCTRL[1] YCCTRL[0]
aspect ratio VARIS code includes bits data plus 6-bit CRC, make total bits. NTSC 14-bit data specified shown Table
Table VARIS Code Specification
Number Word0 Word0 4-bit range 4-bit range Contents Communication aspect ratio: full mode (16:9), Picture display system: letter box, normal used Identifying information picture other signals (sound signals) that related picture transmitted simultaneously Identification code associated Word0 Identification code associated Word0 other information
Word1 Word2
6-bit calculated, with preset value based equation G(X) 20-bit code further packaged into bytes according following format.
Table Three Byte VARIS Code
Byte Byte Byte VID_ -Word2
Word0
Word0 Word1
three byte VARIS code constructed part initialization process. code transmitted during non-active video line starting from byte. application VID_EN that signals NTSC/PAL encoder enable disable VARIS code. value Aspect Ratio depends setup `AV7110 video output source stream shown Table application change video output format using software call.
Table Coding Aspect Ratio VARIS Code
Source Video Video 16:9 Source 16:9 16:9
timing VARIS output based clock shown timing diagrams Section 17.1. timing both 4:4:4 4:2:2 digital video output formats also described there.
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Audio Decoder
10.1 Features
Decodes MPEG audio layers Supports MPEG-1 MPEG-2 data rates sampling frequencies Provides automatic audio synchronization Supports 18-bit data Outputs both SPDIF formats Provides error concealment muting) synchronization errors Provides frame-by-frame status information Supports half-frequency modes Supports playback 16-bit data (PCM bypass), audio elementary stream, audio Provides read/write accesses audio input buffers' read/write pointers audio module receives MPEG compressed audio data from decodes outputs audio samples format. APIs provided initialize/control audio decoder control register read status information from decoder's status register. Audio frame data information stored SDRAM packet form. audio module decodes packets extract audio data. audio decoder uses this value perform playback synchronization (see Section more details). application software determines enables MPEG-1 compliant bit-stream MPEG-2 audio program which contains both MPEG-1 compliant bit-stream MPEG-2 extension bit-stream. control operation audio module 32-bit control register. reset mute audio decoder, select output precision over-sampling ratio, choose output format dual channel mode. read status information from audio module. (32-bit) register provides MPEG header information sync, CRC, status. audio module 32-bit registers: read/write control register read-only status register. registers defined Table
Table Audio Module Registers
Register (Control Register R/W) Location 31:22 Description Reserved (set Disable Sync Enable sync Disable sync Byte Swap swap (bypass data Little Endian) Swap bytes (bypass data Endian) Elementary Stream Playback (normal operation) incoming data goes directly audio decoder, bypassing Bypass Disable bypass (normal operation) Enable bypass audio decoder Copyright Auto-Update Enable: Allows software write updated from MPEG header above. (this output through SPDIF) category (programmed user, output through SPDIF) Clock source select (PCMSRC) defaults Internal Output format select (also called PCMSEL[3:0])
15:9 (cont.)
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Register (Control Register R/W)
Location
(Status Register only)
30:29
28:27
23:4
Description Table Dual Channel Mode Output Mode Select left, right both left right both left right Reserved Mute Normal operation Mute audio output Reset Normal operation Reset audio module Stereo Mode other Dual mode MPEG-1 Sampling Frequency [kHz] MPEG (bit MPEG (bit 44.1 22.05 48.0 24.0 32.0 16.0 Reserved Reserved De-emphasis Mode None 50/15 microseconds Reserved CCITT J.17 Synchronization Mode Normal operation Sync recovery mode Error error enabled bit-stream error found Underflow Normal operation output underflowed MPEG header without sync word bit(s) (equals SAMPFREQ[2]) 22:21 Layer Protection 19:16 Bitrate index 15:14 Sampling frequency (equal SAMPFREQ[1:0]) Padding Private 11:10 Mode Mode extension Copyright Original/home Emphasis Reserved
10.2 Audio Output
audio output from `AV7110 serial data line, with associated Clock (ASCLK) left/right clock (LRCLK). data output serially PCMOUT using serial clock ASCLK, shown Figure data output PCMOUT alternates between channels, designated LRCLK. data output most significant first. case 18-bit output, word size bits. first bits zero, followed 18-bit value.
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ASCLK
LRCLK
PCMOUT
Left
Left
Left
Right
Right
Figure Output Timing (16-bit format)
Since audio sampling frequency change from audio frame another, whenever frequency changes, audio decoder soft mutes output audio frame notifies processor change sampling frequency FIQ. Table shows SAMPFREQ PCMSEL values that reserved. defined there should output format over-sampling ratio between PCMCLK ASCLK specified four-bit register PCMSEL[3:0] which API. relationship between ASCLK LRCLK given follows: 16-bit format: 18-bit format: ASCLK LRCLK ASCLK LRCLK
PCMCLK equals ASCLK there over-sampling; otherwise PCMCLK equals ASCLK.
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Table PCMCLK frequencies
SAMPFREQ[2:0] (output external PLL) Sampling Frequency (LRCLK) PCMSEL[1] (Format select) ASCLK (bit clock) PCMCLK PCMSEL[0] PCMSEL[0] over-sampling) oversampled) 1.0240MHz 1.5360MHz 1.4112MHz 2.1168MHz 1.5360MHz 2.3040MHz 0.5120MHz 0.7680MHz 0.7056MHz 1.0548MHz 0.7680MHz 1.1520MHz 8.1920MHz 12.2880MHz 11.2896MHz 16.9344MHz 12.2880MHz 18.4320MHz 4.0960MHz 6.1440MHz 5.6448MHz 8.4672MHz 6.1440MHz 9.2160MHz
(16-bit PCM) (18-bit PCM)
1.0240MHz 1.5360MHz 1.4112MHz 2.1168MHz 1.5360MHz 2.3040MHz 0.5120MHz 0.7680MHz 0.7056MHz 1.0548MHz 0.7680Hz 1.1520MHz
44.1KHz
(16-bit PCM) (18-bit PCM)
48KHz
(16-bit PCM) (18-bit PCM)
(16-bit PCM) (18-bit PCM)
22.05KHz
(16-bit PCM) (18-bit PCM)
24KHz
(16-bit PCM) (18-bit PCM)
This Power Default settings
10.2.1 Using External Audio
Either internal external used based setting PCMSRC Control Register (bit External Audio used, PCMCLK must input device from external clock source. Depending external connected `AV7110, control signals either sent extension interface (EBI Section interface (Section 14.8). According these control signals external audio should adjust clock PCMCLK that shown Table event audio sampling frequency changes from audio frame next, generated application software opportunity update settings external according setting bits (SAMPFREQ[2:0]) audio status register.
10.3 Bypass
audio decoder PCM-bypass feature that allows 16-bit data loaded into audio buffer pass through decoder PCMDATA output. Half-Sampling supported Bypass mode. data 96KHz sampling frequency, necessary application software conjunction with API's) first down sample data 48KHz lower. output, 18-bit output data format selected (see Table 29), 16-bit bypass data padded with zeroes end, zeroes end. API's provided audio decoder bypass mode obtain start addresses audio buffer SDRAM. User software these routines load data directly into audio buffer. input data transfer carried Extension Interface (Section 1394 interface (through SRAM, then DMA; Section 13.1). data must first reordered user into: bytes left, bytes right, bytes left, etc., prior
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transfer. each bytes (left right), most significant byte loaded first (Little Endian data format). front audio decoder also capable performing byte swapping data Endian format. This feature activated together with PCM-bypass mode through API. incomplete block loaded end, entire block output. data starts output after four blocks (512 bytes) have been loaded. change back compress-data input, audio decoder must reset API.
10.4 Elementary Stream Playback
normal operation, audio decoder front (Audio Front end, AFE) expects audio packets from performs synchronization time stamp extraction. also possible turn front processing through that audio elementary stream directly decoder, bypassing front processing. However, such case, user software will completely responsible audio/video synchronization.
10.5 SPDIF Audio Output
SPDIF output conforms consumer format AES3 standard serial transmission digital audio data. When using external (PCMSRC=1), SPDIF supported only oversampled PCMCLK supplied (i.e., PCMSEL[0]=1). validation disabled prior muting output during channel change Sample Frequency change. During Sample frequency change, SPDIF output invalid. External SPDIF decoder should recognize this mute output. It's expected recover automatically when frequency achieved.
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Synchronization
`AV7110 uses System Time Clock (STC) Presentation Time Stamp (PTS) determine playback time decoded audio video data. relationship between determined time generation respective elementary streams (ES). Upon reception, de-multiplexing software `AV7110 extracts video inserts array byte-count information maintained video decoder. audio, information extracted audio decoder front from PES. Video decoder contains counter that clocked system clock MHz.) normalized reference. audio decoder does contain counter. Instead, gets updated from system time reference counter every msec.
11.1 System Time Clock
system reference counter hardware/software hybrid counter shown Table
Table System time clock model
Software extension Hardware counter KHz.) Hardware counter MHz) rollover count
copy full counter kept software long variables bits total length) When lower bits hardware counter roll over, hardware counter incremented. When hardware counter incremented, generated firmware. firmware will increment software extension write value STCsys offset audio/video decoder audio/video decoder synchronization enabled.
11.2 Startup Synchronization
startup hardware counter free running increments software extension system take place every Both audio video decoders initialized "free-run". This condition identical system startup well re-synchronization after channel change. When channel activated application software through API, on-chip software monitors incoming data designated channel reset system common reference counter STCsys first that arrives designated stream (full bits). same time, video audio initialized same value, they enabled appropriate calls.
11.3 Runtime Synchronization
After initial synchronization setup, software will monitor incoming video values compares them most recent STC. difference between should exceed user programmable MAX_PTS_STC_DELTA. does, discarded. Otherwise delta stored circular entry array. average value array calculated according PTS_DELTA_AVRG (Array[0.7]) value MAX_PTS_STC_DELTA defined user call function sysSetSyncParms(). absolute value incoming exceeds pre-determined maximum delta from PTS_DELTA_AVRG, value discarded (see Figure 18). This condition calculated according unsigned (PTS PTS_DELTA_AVRG) PTS_GUARDBAND
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Discarded Guard band Delta
Incoming
PTS_DELTA_AVRG
Discarded PTS-s
Figure tracking diagram 11.4 Audio Synchronization
audio synchronization enabled/disabled through API. audio decoder time reference loaded firmware every time System reference counter (STCsys) "rolls over". This roll over will occur every ticks portion hardware system clock counter `AV7110. This approximately every msec. firmware receives from counter write STCsys aud_offset register audio decoder. value aud_offset default after initialization after audio channel change. value aud_offset derived from either sources: Setup application software syncSetStcOffset() API. Xideo decoder signal case Audio-video sync (lip-sync).
11.5 Video Synchronization
video synchronization enabled/disabled API. video decoder clocked MHz. system clock. initial value video (STCvid) written video decoder from firmware. This happens time that first from designated channel arrives some cases consistently certain amount, causing video buffer eventually over- under-run. this occurs, firmware will detect under/over-runs FIQ-s adjust Video with offset, such that under/over-run ceases. algorithm prevent occurrence under-flow caused consistent based monitoring delta (PTS STCsys every time STCsys counter rollover interrupt occurs following manner: current (PTS STC) read from video decoder, software registers delta value. STCsys GUARDBAND_VALUE twice row, then adjust appropriate channels ADJUSTMENT. case lip-sync enabled, audio offset updated value written audio
values GUARDBAND_VALUE ADJUSTMENT_VALUE defined call function sysSetSyncParms().
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case user wants force reset video reference video re-initialized with vid_offset STCsys. video_offset variable also application software using syncSetStcOffset() API.
11.6 Audio-video Synchronization (lip-sync)
audio-video synchronization required, user application software should video decoder reference both audio video synchronization. video decoder will synchronize itself described Section 11.5. audio initialization updates, however, done differently from description given Section 11.4. firmware calculates that offset video required described Section 11.5, stores video offset into aud_offset variable too. (STCvid) should used reference STCaud. Thus, every time STCsys rolls over, audio decoder update calculated follows: STCaud STCsys aud_offset this offset causes audio decoder generate audio buffer under- over-run, then firmware signals application software that lip-sync could achieved.
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Extension Interface (EBI)
extension interface 32-bit 16-bit bi-directional data with 25-bit address. also provides external interrupts wait line. external memories devices mapped 32-bit address space ARM. There internally generated Chip Selects (CSx) devices such EPROM memory, modem, front panel, front control, parallel output port, 1394 Link device. Each defined memory space programmable wait register which default maximum allowable values defined Table number wait states depends content register, with minimum wait state. EXTWAIT signal also used lengthen access time slower device exists that memory space. These programmable application software using APIs. active output signal EXTOE/EXTACTIVE user selectable either asserted during read cycles only (EXTOE), default selection, asserted both read write cycles (EXTACTIVE). This signal equals logical chip selects well DRAM access EBI. timing relationship this signal with respect other signals found Section 17.1. When 32-bit mode selected operating Thumb mode, instruction pre-fetch supported. Each instruction fetch external memory will transfer 16-bit instructions. sent immediately other stored local register service next instruction access. During Reset `AV7110, signals held tri-state condition until Reset signal released. Note that this includes full 32-bit version because device does configure operation until comes reset. External pull-up resistors required control logic prevent falsely enabling external devices during reset. Furthermore, roughly pull-up resistors recommended address data lines well prevent problems associated with "floating" busses.
12.1 Address Range Wait State Chip Select
Extension supports connection devices using pre-defined chip selects. Additional devices used externally decoding address bus. Table shows name device, chip select, address range, programmable wait state range. Every device connected required have tri-stated data outputs within clock cycle (CLK40) following removal chipselect. accesses interleaved with based accesses. This clock cycle nanoseconds) constraint ensure correct DRAM write when interleaved with transfers. tri-state timing requirement after other transactions (including DRAM) clock cycles nssec. with exception. access EPROM (CS1 region) during transfer EBI. This transaction requires restriction between access access because priority code fetches ARM.
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Table Extension Chip Select Assignments
Chip Select Byte Address Range 2C00 0000 2DFF FFFF 2E00 0000 2EFF FFFF 2F00 0000 2FFF FFFF 3000 0000 31FF FFFF 3200 0000 33FF FFFF 3400 0000 35FF FFFF 3600 0000 37FF FFFF 3800 0000 39FF FFFF Wait State Device EPROM MBytes) DRAM Mbytes, RAS1) DRAM 16Mbytes, RAS3) Peripheral Device Peripheral Device Peripheral Device Peripheral Device Peripheral Device
CS2, CS3, CS4, have same characteristics. performs reads writes these devices through Extension Bus. intended application code, writes will prevented. user needs provide number wait states each during initial default wait state maximum allowable wait state.
12.2 Read Write Cycles
Extension supports connection external EPROM, SRAM, memory DRAM with 32-bit 16-bit data 25-bit address. also supports transfers to/from Extension Bus. transfers within extension supported directly. They accomplished from user application software using internal Data RAM, followed second transfer back EBI. Extension single read write cycle timings shown Figure Figure Section 17.1 respectively. number wait states calculated following formula: wait states round_up[ device_cycle_time) 24.68 example, device with nsec read timing requires four wait states. user application software program read pattern Extension single multiple. single access mode allows access during each cycle; multiple access allows more than access during cycle. data latched based programmed wait state respective chip select. write access always single. Both read write timing examples shown Section 17.1 show case four wait states.
12.3 Interrupts
`AV7110 Extension three external interrupt lines. Each interrupt dedicated acknowledge (EXTACK[2:0]). additional interrupt, BDIRQ (HSDI_SIG7), dedicated 1394 interface associated acknowledge signal. interrupts generate application software responsible providing their service routine. These interrupts handled centralized interrupt controller. interrupt mask priority managed firmware. BDIRQ three extension interrupts connected total four different IRQs. When interrupt service routine begins servicing extension IRQs, should first issue corresponding acknowledge signal. completion IRQ, should reset acknowledge signal.
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12.4 EXTWAIT signal
EXTWAIT signal alternative communicate with slower devices. used together with programmable wait state, become active before programmable wait cycle expires. When combined total wait states exceeds maximum, decoder guaranteed function properly. EXTWAIT signal synchronized internally with on-chip 81MHz clock. When device needs EXTWAIT signal, should programmable wait state least duration EXTWAIT signal should least 24.7 nanoseconds. Because EXTWAIT signal potential stall whole decoding process, will waiting nanoseconds. Afterwards, assumes device that generated EXTWAIT failed will ignore EXTWAIT from then Only software hardware reset activate EXTWAIT signal again. timing diagram shown Section 17.1 example read using EXTWAIT signal. This example assumes that wait state final effect using EXTWAIT equivalent wait states. device generate EXTWAIT within nanoseconds, user larger wait state. maximum response time EXTWAIT signal calculated follows: Max. response time EXTWAIT nanoseconds) (programmed wait state maximum nanoseconds wait time applies each access Extension Bus. device connected Extension Bus, automatically converts single word access consecutive byte accesses, maximum wait time applies total byte accesses. consecutive read access where remains active during reading four bytes, each byte access complete within nanoseconds. device that requires longer access delay, nanoseconds, then access from limited only half words. write access where toggles each byte write, then each write take nanoseconds. reference, Section 17.1 also shows same example write cycle.
12.5 Extension DRAM
Extension supports access 60ns 70ns DRAM, well 60ns DRAM; default 70ns DRAM. Figure Figure Section 17.1 respectively show read write timing this DRAM interface. DRAM must have column address that 8-bit, 9-bit, 10-bit. DRAM must have data width bits. Byte access allowed even when DRAM 16bit data width. system default DRAM configuration 9-bit column address 16-bit data width. user reconfigure extension 32-bit with API. firmware will automatically verify configuration during start Connection between `AV7110 DRAM glueless, that address A(i) should connected directly address input A(i) DRAM. byte access specified signal UCAS EXTDATA[31:24], LCAS EXTDATA[23:16]. Another signal (RAS3) available support additional (possibly removable) DRAM device (such PCMCIA DRAM card) 16-bit width. This DRAM device mapped fixed (pre-determined) address partition (see Table 31). Configuration existence this additional DRAM device determined application software power box. insertion removal this additional DRAM device allowed. RAS2 increasing width DRAM configuration 32-bit. Possible DRAM configurations shown Figure When `AV7110 transferring data /from DRAM DMA, makes full page mode read/write cycle will read/write byte/half-word/word every 50nsec clock cycles). When 16-bit wide DRAM accessed from ARM, DRAM controller will make page mode read cycle transfer each word. Each 32-bit write/read addressed independently DRAM.
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EXTDATA[31:16] EXTDATA[15:0] RAS2 UCAS LCAS RAS1
EXTDATA[31:16]
RAS1 UCAS
DRAM-1
UCAS LCAS
DRAM-2
DRAM-1
RAS3 UCAS LCAS
LCAS
DRAM-2
DRAMs 32-bit extension bus: signals allow word, half word accesses; U/LCAS control byte accesses.
DRAMs 16-bit extension increase depth: DRAM-1 DRAM-2 different sizes; RAS1 RAS-2 select front back bank; U/LCAS control byte accesses.
EXTDATA[31:16]
EXTDATA[31:16]
EXTDATA[15:0] RAS2 UCAS LCAS RAS1
RAS1 RAS3 UCAS
DRAM-1
UCAS LCAS
DRAM-2
RAS3 UCAS LCAS
DRAM-1
DRAM-2
LCAS
three DRAMs 32-bit extension bus: signals allow word, half word accesses; U/LCAS control byte accesses.
DRAMs 16-bit extension bus.
Figure Examples DRAM connections 16-bit 32-bit extension busses 12.6 Byte Ordering Extension
Endian byte ordering adopted inside `AV7110 Extension Bus. That most significant byte Extension from EXTDATA[24] EXTDATA[31]. Figure illustrates bytes from converted consecutive 16-bit half words Extension consecutive bytes 8-bit device were used.
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'AV7100/ARM address
Byte Byte Byte Byte
Extension
16-bit device address
8-bit device address<b
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