+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs

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+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs

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19-4774; 7/04
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs
MAX3690 serializer ideal converting 8-bitwide, 77Mbps parallel data 622Mbps serial data Aand SDH/SONET applications. Operating from single +3.3V supply, this device accepts clock data inputs, delivers 3.3V differential PECL serialdata output. fully integrated synthesizes internal 622MHz serial clock from low-speed crystal reference clock (77.76MHz, 51.84MHz, 38.88MHz). MAX3690 available extended-industrial temperature range (-40°C +85°C) 32-pin TQFP package.
_Features
Selectable Reference Clock Frequency: 77.76MHz, 51.84MHz, 38.88MHz Single +3.3V Supply 77Mbps (8-bit) Parallel 622Mbps Serial Conversion Clock Synthesis 622Mbps Serial Data 200mW Power Parallel Clock Data Inputs Differential 3.3V PECL Serial-Data Output
MAX3690
_Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
PART MAX3690ECJ MAX3690ECJ+
Ordering Information
TEMP RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE TQFP TQFP
+Denotes lead-free package. Configuration appears data sheet.
Typical Operating Circuit
38.88MHz CRYSTAL REFERENCE +3.3V
PCLKI PCLKO
RCLK
CKSET
OVERHEAD GENERATION
MAX3690
FIL+ FIL-
+3.3V
+3.3V
MAX3668
THIS SYMBOL REPRESENTS TRANSMISSION LINE CHARACTERISTIC IMPEDANCE 50).
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect GND) .-0.5V Inputs, FIL-, FIL+, PCLKO .-0.5V (VCC 0.5V) Output Current PECL Outputs (SD±).50mA Continuous Power Dissipation +85°C) TQFP (derate 10.2mW/°C above +85°C) .663mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-60°C +160°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, PECL loads (VCC 2V), -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) PARAMETER Supply Current CKSET Input Current PECL OUTPUTS (SD±) Output High Voltage Output Voltage +85°C -40°C +85°C -40°C 1.025 1.085 1.81 1.83 400µA -400µA 0.44 0.88 0.88 1.62 1.555 SYMBOL ICKSET CONDITIONS PECL outputs unterminated CKSET UNITS
INPUTS OUTPUTS (PCLKI, RCLK, PCLKO, PD_) Input High Voltage Input Voltage Input High Current Input Current Output High Voltage Output Voltage
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, PECL loads (VCC 2V), thresholds VCC/2, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) (Note PARAMETER Serial Clock Rate Parallel Data Setup Time Parallel Data Hold Time Allowable Parallel Clock Output Parallel Clock Input Delay Output Random Jitter PECL Differential Output Rise/Fall Time Output Rise Time Output Fall Time SYMBOL fSCLK tSKEW CLOAD 15pF, VOUT 0.8V 2.0V CLOAD 15pF, VOUT 0.8V 2.0V 1200 1000 CONDITIONS 622.08 UNITS psRMS
Note characteristics guaranteed design characterization. Note thresholds
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
_Typical Operating Characteristics
(VCC +3.3V, +25°C, unless otherwise noted.)
SUPPLY CURRENT TEMPERATURE
MAX3690-01
PARALLEL DATA SETUP TIME TEMPERATURE
MAX3690-02
PARALLEL DATA HOLD TIME TEMPERATURE
MAX3690-03
SUPPLY CURRENT (mA)
PARALLEL DATA SETUP TIME (ps)
PARALLEL DATA HOLD TIME (ps)
TEMPERATURE (°C)
TEMPERATURE
TEMPERATURE (°C)
SERIAL DATA RANDOM JITTER (RCLKI 77.76MHz)
MAX3690-05
ALLOWED PCLKO PCLKI SKEW TEMPERATURE
MAX3690-07
SERIAL-DATA OUTPUT DIAGRAM (622Mbps, PRBS)
MAX3690-08
3.3V
TIME (ns) 2mV/ 100mV/
4.66psRMS 5ps/div TEMPERATURE (°C) TEMPERATURE (°C) 200ps/div
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
_Pin Description
NAME PD0-PD7 FUNCTION Parallel-Data Inputs. Data clocked PCLKI signal's positive transition.
Ground
PCLKO SDSD+
Parallel-Clock Output. positive transition PCLKO clock overhead management circuit. +3.3V Supply Voltage Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Reference Clock Rate Programming Pin. CKSET open: Reference clock rate 77.76MHz CKSET GND: Reference clock rate 51.84MHz CKSET GND: Reference clock rate 38.88MHz Filter Capacitor Input. Connect capacitor between FIL- VCC. Filter Capacitor Input. Connect capacitor between FIL- VCC. Reference-Clock Input. Connect crystal reference clock (77.76MHz, 51.84MHz 38.88MHz) RCLK input. active edge positive transitioning edge. Parallel-Clock Input. Connect incoming parallel-data-clock signal PCLKI input. active edge positive transitioning edge.
CKSET
FILFIL+ RCLK PCLKI
_Detailed Description
MAX3690 serializer comprises 8-bit parallel input register, 8-bit shift register, control timing logic, PECL output buffer, input/output buffers, frequency-synthesizing (consisting phase/frequency detector, loop filter/amplifier, voltagecontrolled oscillator, programmable prescaler). This device converts 8-bit-wide, 77Mbps parallel data 622Mbps serial data (Figure synthesizes internal 622MHz reference used clock output shift register. This clock generated locking onto external crystal reference clock signal (RCLK) operating either 77.76MHz, 51.84MHz, 38.88MHz. incoming par-
allel data clocked into MAX3690 rising transition parallel-clock-input signal (PCLKI). control timing logic ensure proper operation parallel-input register latched within window time that defined with respect parallel-clock-output signal (PCLKO). PCLKO synthesized 622MHz internal serial-clock signal divided eight. Parallelclock output parallel-clock-input delay (skew) must observed. Figure shows timing diagram.
PECL Outputs
serial-data PECL outputs (SD+, SD-) require termination (VCC 2V). Alternative PECLOutput Termination section.
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
8-BIT PARALLEL INPUT REGISTER
PCLKI CKSET
PRESCALER
SHIFT 8-BIT SHIFT REGISTER PECL SDOH SDOL
RCLK
PHASE/FREQ DETECT
CONTROL
LATCH
MAX3690
FIL+ FILPCLKO
Figure Functional Diagram
PCLKO tSKEW
PCLKI VALID PARALLEL DATA
NOTE:
Figure Timing Diagram
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
_Applications Information
Alternative PECL-Output Termination
Figure shows alternative PECL-output-termination methods. Thevenin-equivalent termination when (VCC termination voltage available. coupling necessary, sure that coupling capacitor placed following Theveninequivalent termination.
+3.3V
MAX3690
PECL INPUTS
Layout Techniques
best performance, good high-frequency layout techniques. Filter voltage supplies keep ground connections short. multiple vias where possible. Also, controlled-impedance transmission lines interface with MAX3690 data outputs.
MAX3690
HIGHIMPEDENCE INPUTS
Figure Alternative PECL-Output Termination
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs
Configuration
FIL+ FILVCC CKSET
MAX3690
VIEW
RCLK PCLKI
MAX3690
SDVCC PCLKO
TQFP
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs MAX3690
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
TQFPPO.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis Inputs

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