ANUAL LUATIO SHEET FOLLO +3.3V, 2.488Gbps, SDH/SONET 1:16 Deseria

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ANUAL LUATIO SHEET FOLLO +3.3V, 2.488Gbps, SDH/SONET 1:16 Deseria

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19-4767; 1/99
ANUAL LUATIO SHEET FOLLO
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Single +3.3V Supply 2.488Gbps Serial 155Mbps Parallel Conversion 660mW Operating Power LVDS Data Outputs Synchronization Inputs Self-Biasing PECL Inputs Ease Coupling Synchronization Inputs Data Realignment Reframing
General Description
MAX3885 deserializer ideal converting 2.488Gbps serial data 16-bit wide, 155Mbps parallel data SDH/SONET applications. Operating from single +3.3V supply, this device accepts PECL serial clock data inputs, delivers low-voltage differential-signal (LVDS) clock data outputs interfacing with high-speed digital circuitry. also provides LVDS synchronization input that enables data realignment reframing. MAX3885 available extended temperature range (-40°C +85°C) 64pin TQFP package.
MAX3885
Applications
2.488Gbps SDH/SONET Transmission Systems Add/Drop Multiplexers Digital Cross Connects
PART MAX3885ECB
Ordering Information
TEMP. RANGE -40°C +85°C PIN-PACKAGE TQFP
Configuration appears data sheet.
Typical Operating Circuit
+3.3V +3.3V +3.3V PD15+ 100* PD15SD86.6 SERIAL DATA INPUTS DATA CLOCK RECOVERY 86.6
MAX3875
OVERHEAD TERMINATION
MAX3885
PD0+
+3.3V PD0133 SCLK+ SCLK86.6 86.6 PCLKSYNC+ SYNCGND PCLK+
100*
100*
*REQUIRED ONLY OVERHEAD CIRCUIT DOES INCLUDE INTERNAL INPUT TERMINATION. THIS SYMBOL REPRESENTS TRANSMISSION LINE CHARACTERISTIC IMPEDANCE
Maxim Integrated Products
free samples latest literature: http://www.maxim-ic.com, phone 1-800-998-8800. small orders, phone 1-800-835-8769.
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (VCC).-0.5V +7.0V Input Voltage Level (all inputs).-0.5V (VCC 0.5V) Output Current LVDS outputs .10mA Continuous Power Dissipation +85°C) TQFP (derate 24mW/°C above +85°C) .1000mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-60°C +160°C Lead Temperature (soldering, 10sec) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, differential loads ±1%, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) PARAMETER SYMBOL CONDITIONS UNITS Supply Current PECL INPUTS (SD+/-, SCLK+/-) Input High Voltage Input Voltage Input High Current Input Current Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Voltage Differential Output Voltage Change Magnitude Differential Output Voltage Complementary States Output Offset Voltage Change Magnitude Output Offset Voltage Complementary States Single-Ended Output Resistance Change Magnitude SingleEnded Output Resistance Complementary Outputs VIDTH VHYST ±2.5 1.125 0.925 Figure 1.275 VIH(MAX) VIL(MIN) Differential input voltage 100mV Common-mode voltage 50mV 1.16 1.81 -900 -900 -100 1.475 0.88 1.48
LVDS INPUTS OUTPUTS (SYNC+/-, PCLK+/-, PD_+/-)
ELECTRICAL CHARACTERISTICS
(VCC +3.0V +3.6V, differential loads ±1%, -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) (Note Figure PARAMETER Maximum Serial Clock Frequency Serial Data Setup Time Serial Data Hold Time Parallel Clock-to-Data Output Delay SYMBOL fSCLK tCLK-Q CONDITIONS 2.488 UNITS
Note Characteristics guaranteed design characterization.
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Typical Operating Characteristics
(VCC +3.3V, +25°C, unless otherwise noted.)
MAX3885
MAXIMUM SERIAL CLOCK FREQUENCY TEMPERATURE
MAX3885-01
SERIAL DATA-SETUP TIME TEMPERATURE
MAX3885-02
SERIAL DATA-HOLD TIME TEMPERATURE
MAX3885-03
SERIAL CLOCK FREQUENCY (GHz) 3.6V
SERIAL DATA-SETUP TIME (ps)
SERIAL DATA-HOLD TIME (ps)
TEMPERATURE (°C)
TEMPERATURE (°C)
-100 TEMPERATURE (°C)
SUPPLY CURRENT TEMPERATURE
MAX3885-04
PARALLEL CLOCK DATA OUTPUT PROPAGATION DELAY TEMPERATURE
PCLK DATA OUTPUT PROPAGATION DELAY (ps)
MAX3885-05
SUPPLY CURRENT (mA)
3.6V
TEMPERATURE (°C)
TEMPERATURE (°C)
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
Description
NAME Ground FUNCTION
+3.3V Supply Voltage Serial Data Noninverting PECL Input. Data clocked SCLK signal's positive transition. Serial Data Inverting PECL Input. Data clocked SCLK signal's positive transition. Serial Clock Noninverting PECL Input Serial Clock Inverting PECL Input Synchronizing Pulse Inverting LVDS Input. Pulse SYNC signal high least four SCLK periods shift data alignment dropping bit. Synchronizing Pulse Noninverting LVDS Input. Pulse SYNC signal high least four SCLK periods shift data alignment dropping bit. Parallel Clock Inverting LVDS Output Parallel Clock Noninverting LVDS Output Parallel Data Inverting LVDS Outputs. Data updated negative transition PCLK signal.
SDSCLK+ SCLKSYNCSYNC+ PCLKPCLK+
PD0- PD15-
PD0+ PD15+
Parallel Data Noninverting LVDS Outputs. Data updated negative transition PCLK signal.
PDVPDSINGLE-ENDED OUTPUT VPD+
|VOD|
VPD+ VPDDIFFERENTIAL OUTPUT (DIFF.)
+VOD VOD, VPD+ VPD-VOD
Figure Driver Output Levels
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Detailed Description
MAX3885 deserializer uses 16-bit shift register, 16-bit parallel output register, 4-bit counter, PECL input buffers, low-voltage differential-signal (LVDS) input/output buffers convert 2.488Gbps serial data 16-bit wide, 155Mbps parallel data (Figure input shift register continuously clocks incoming data positive transition serial clock (SCLK) input signal. 4-bit counter generates parallel-output clock (PCLK) dividing serial-clock frequency PCLK signal clocks parallel-output register. During normal operation, counter divides SCLK frequency causing output register latch every bits incoming serial data. synchronization inputs (SYNC+, SYNC-) realign reframe data. When SYNC signal pulsed high least four SCLK cycles, parallel output data delayed SCLK cycle. This realignment guaranteed occur within complete PCLK cycles SYNC signal's positive transition. result, first incoming data during that PCLK cycle dropped, shifting alignment between PCLK data bit. Figure timing diagram Figure timing parameters diagram.
MAX3885
SDSCLK+ SCLKPECL PECL 16-BIT SHIFT REGISTER 16-BIT PARALLEL OUTPUT REGISTER LVDS
PD15+ PD15-
PD1+ LVDS
MAX3885
PD1PD0+
Low-Voltage Differential-Signal (LVDS) Inputs Outputs
MAX3885 features LVDS inputs outputs interfacing with high-speed digital circuitry. LVDS standard based IEEE 1596.3 LVDS specification. This technology uses 500mVp-p 800mVp-p differential low-voltage swings achieve fast transition times, minimize power dissipation, improve noise immunity. parallel clock data LVDS outputs (PCLK+, PCLK-, PD_+, PD_-) require differential
LVDS
PD0PCLK+
SYNC+ SYNC100 LVDS
4-BIT COUNTER
LVDS
PCLK-
Figure Functional Diagram
SCLK SYNC
PCLK
(LSB)
(MSB) PD15 TRANSMITTED FIRST
SLIPPED THIS TIME SLICE
Figure Timing Diagram
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
tSCLK fSCLK SCLK
PCLK tCLK-Q PD0-PD15
NOTE: SIGNALS SHOWN DIFFERENTIAL. EXAMPLE, SCLK (SCLK+) (SCLK-).
Figure Timing Parameters
termination between inverting noninverting outputs proper operation. terminate these outputs ground. synchronization LVDS inputs (SYNC+, SYNC-) internally terminated with differential input resistance and, therefore, require external termination.
THEVENIN-EQUIVALENT TERMINATION +3.3V
MAX3885
PECL INPUTS
PECL Inputs
Because self-biasing resistor networks, serial data clock PECL inputs (SD+, SD-, SCLK+, SCLK-) require termination when interfacing with PECL source (see Alternative PECL Input Termination). This results equivalent input resistance
86.6
86.6
Applications Information
Alternative PECL Input Termination
Figure shows alternative PECL input-termination methods. Thevenin-equivalent termination when termination voltage available. When interfacing with ECL-output device, MAX3885's internal self-biasing allows easy AC-coupling termination.
AC-COUPLING TERMINATION
MAX3885
PECL INPUTS
Layout Techniques
best performance, good high-frequency layout techniques. Filter voltage supplies keep ground connections short. multiple vias where possible. Also, controlled impedance transmission lines interface with MAX3885 high-speed inputs outputs.
Figure Alternative PECL Input Termination
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs
Configuration
PD9+ PD8+ PD7+ PD6+ PD5+ PD9PD8PD7PD6PD5GND
MAX3885
VIEW
PD10- PD10+ PD11- PD11+ PD12- PD12+ PD13- PD13+ PD14- PD14+ PD15- PD15+
PD4+ PD429 PD3+ PD327 PD2+ PD225
MAX3885
PD1+ PD121 PD0+ PD019 PCLK+ PCLK17
SYNC-
SCLK-
SYNC+
SCLK+
TQFP
_Chip Information
TRANSISTOR COUNT: 2820
+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with LVDS Outputs MAX3885
Package Information
TQFPPO.EPS

ANUAL LUATIO SHEET FOLLO +3.3V, 2.488Gbps, SDH/SONET 1:16 Deseria

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