ATION EVALU ILABLE +3.3V, 622Mbps, SDH/SONET Serializer with Cloc

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ATION EVALU ILABLE +3.3V, 622Mbps, SDH/SONET Serializer with Cloc

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19-4775; 5/04
ATION EVALU ILABLE
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs
MAX3693 serializer ideal converting 4-bitwide, 155Mbps parallel data 622Mbps serial data Aand SDH/SONET applications. Operating from single +3.3V supply, this device accepts low-voltage differential-signal (LVDS) clock data inputs interfacing with high-speed digital circuitry, delivers 3.3V PECL serial-data output. fully integrated synthesizes internal 622Mbps serial clock from 155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz reference clock. MAX3693 available extended temperature range (-40°C +85°C), 32-pin TQFP package. Single +3.3V Supply 155Mbps (4-bit-wide) Parallel 622Mbps Serial Conversion Clock Synthesis 622Mbps 215mW Power Multiple Clock Reference Frequencies (155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz) LVDS Parallel Clock Data Inputs Differential 3.3V PECL Serial-Data Output
Features
MAX3693
Applications
622Mbps SDH/SONET Transmission Systems 622Mbps ATM/SONET Access Nodes Add/Drop Multiplexers Digital Cross Connects
PART MAX3693ECJ MAX3693ECJ+
Ordering Information
TEMP RANGE -40°C +85°C -40°C +85°C PIN-PACKAGE TQFP TQFP
+Denotes lead-free package. Configuration appears data sheet.
Typical Operating Circuit
(155MHz LVDS CRYSTAL REFERENCE)
+3.3V
PCLKI- PCLKI+ RCLK- RCLK+ PD0+ PD0OVERHEAD GENERATION PD1+ PD1PD2+ PD2PD3+ PD3PCLKO- PCLKO+
CKSET FIL+
MAX3693
FILVCC +3.3V +3.3V
MAX3668
THIS SYMBOL REPRESENTS TRANSMISSION LINE CHARACTERISTIC IMPEDANCE
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs MAX3693
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect GND) .-0.5V Inputs, FIL+, FIL-, PCLKO+, PCLKO- .-0.5V (VCC 0.5V) Output Current LVDS Outputs (PCLKO±).10mA PECL Outputs (SD±).50mA Continuous Power Dissipation +85°C) TQFP (derate 10.20mW/°C above +85°C) .663mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-60°C +160°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC +3.6V, differential LVDS loads ±1%, PECL loads (VCC 2V), -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) PARAMETER Supply Current PECL OUTPUTS (SD±) Output High Voltage Output Voltage +85°C -40°C +85°C -40°C Differential input voltage 100mV Common-mode voltage 50mV 1.025 1.085 1.81 -1.83 0.88 0.88 1.62 1.555 SYMBOL CONDITIONS PECL outputs unterminated UNITS
LVDS INPUTS OUTPUTS (PCLKI±, RCLK±, PCLKO±, PD_±) Input Voltage Range Differential Input Threshold Threshold Hysteresis Differential Input Resistance Output High Voltage Output Voltage Differential Output Voltage Change Magnitude Differential Output Voltage Complementary States Output Offset Voltage Change Magnitude Output Offset Voltage Complementary States Single-Ended Output Resistance Change Magnitude Single-Ended Output Resistance Complementary Outputs PROGRAMMING INPUT (CKSET) CKSET Input Current ICKSET CKSET ±500 VIDTH VHYST |VOD| |VOD| ±2.5 1.125 0.925 1.275 -100 1.475
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs
ELECTRICAL CHARACTERISTICS
(VCC +3.6V, differential LVDS load ±1%, PECL loads (VCC 2V), -40°C +85°C, unless otherwise noted. Typical values +3.3V, +25°C.) (Note PARAMETER Serial Clock Rate Parallel Data-Setup Time Parallel Data-Hold Time PCLKO PCLKI Skew Output Random Jitter PECL Differential Output Rise/Fall Time SYMBOL fSCLK tSKEW +25°C +4.0 CONDITIONS 622.08 UNITS psRMS
MAX3693
Note characteristics guaranteed design characterization.
Typical Operating Characteristics
(VCC +3.3V, differential LVDS loads ±1%, PECL loads (VCC 2V), +25°C, unless otherwise noted.)
SUPPLY CURRENT TEMPERATURE
MAX3693-01
PARALLEL DATA-SETUP TIME TEMPERATURE
MAX3693-02
PARALLEL DATA-HOLD TIME TEMPERATURE
MAX3693-03
PARALLEL DATA-SETUP TIME (ps)
PARALLEL DATA-HOLD TIME (ps)
SUPPLY CURRENT (mA)
PECL OUTPUTS UNTERMINATED TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs MAX3693
Typical Operating Characteristics (continued)
(VCC +3.3V, differential LVDS loads ±1%, PECL loads (VCC 2V), +25°C, unless otherwise noted.)
SERIAL-DATA OUTPUT DIAGRAM
MAX3693-05
SERIAL-DATA OUTPUT JITTER
MAX3693-06
1.1V
1.0042V
57mV/
10mV/ fRCLK 155.52MHz
0.536V 200ps/div
0.904V Mean 25.22ns 4.073ps PkPk 32.6ps 10ps/div 70.373% 95.357% 99.759%
Description
NAME PD0+ PD3+ PD0- PD3GND PCLKOPCLKO+ SDSD+ FUNCTION Noninverting LVDS Parallel Data Inputs. Data clocked PCLKI signal's positive transition. Inverting LVDS Parallel Data Inputs. Data clocked PCLKI signal's positive transition. Ground Inverting LVDS Parallel-Clock Output. positive transition PCLKO clock overhead management circuit. Noninverting LVDS Parallel-Clock Output. positive transition PCLKO clock overhead management circuit. +3.3V Supply Voltage Inverting PECL Serial-Data Output Noninverting PECL Serial-Data Output Reference Clock Rate Programming Pin. CKSET VCC: Reference Clock Rate 155.52MHz CKSET Open: Reference Clock Rate 77.76MHz CKSET GND: Reference Clock Rate 51.84MHz CKSET Reference Clock Rate 38.88MHz Filter Capacitor Input. Typical Operating Circuit external-component connections. Filter Capacitor Input. Typical Operating Circuit external-component connections. Noninverting LVDS Reference Clock Input. Connect LVDS-compatible crystal reference clock RCLK inputs. Inverting LVDS Reference Clock Input. Connect LVDS-compatible crystal reference clock RCLK inputs. Noninverting LVDS Parallel Clock Input. Connect incoming parallel-data-clock signal PCLKI inputs. Note that data updated positive transition PCLKI signal. Inverting LVDS Parallel Clock Input. Connect incoming parallel-data-clock signal PCLKI inputs. Note that data updated positive transition PCLKI signal.
CKSET
FILFIL+ RCLK+ RCLKPCLKI+ PCLKI-
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs
_Detailed Description
MAX3693 serializer comprises 4-bit parallel input register, 4-bit shift register, control timing logic, PECL output buffer, LVDS input/output buffers, frequency-synthesizing (consisting phase/ frequency detector, loop filter/amplifier, voltagecontrolled oscillator, prescaler). This device converts 4-bit-wide, 155Mbps data 622Mbps serial data (Figure synthesizes internal 622Mbps reference used clock output shift register. This clock generated locking onto external 155.52MHz, 77.76MHz, 51.84MHz, 38.88MHz reference-clock signal (RCLK). incoming parallel data clocked into MAX3693 rising transition parallel-clockinput signal (PCLKI). control timing logic ensure proper operation parallel-input register latched within window time that defined with respect parallel-clock-output signal (PCLKO). PCLKO synthesized 622Mbps internal serialclock signal divided four. allowable PCLKO-toPCLKI skew +4ns. This defines timing window about PCLKO rising edge, during which PCLKI rising edge occur (Figure
MAX3693
PD3+ PD3LVDS
MAX3693
4-BIT PARALLEL INPUT REGISTER
PD2+ PD2LVDS
PD1+ PD1LVDS
PD0+ PD0LVDS
PCLKI+ LVDS PCLKIPRESCALER SHIFT 4-BIT SHIFT REGISTER PECL
RCLK+ LVDS RCLK-
PHASE/FREQ DETECT
CONTROL
LATCH
LVDS
FIL+ FIL- CKSET
PCLKO+ PCLKO-
Figure Functional Diagram
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs MAX3693
PCLKO
tSKEW
PCLKI VALID PARALLEL DATA*
NOTE: SIGNALS SHOWN DIFFERENTIAL. EXAMPLE, PCLKO (PCLKO+) (PCLKO-). *PD3
Figure Timing Diagram
Low-Voltage Differential-Signal (LVDS) Inputs Outputs
MAX3693 features LVDS inputs outputs interfacing with high-speed digital circuitry. LVDS standard based IEEE 1596.3 LVDS specification. This technology uses 250mV 400mV differential low-voltage swings achieve fast transition times, minimized power dissipation, noise immunity. proper operation, parallel-clock LVDS outputs (PCLKO+, PCLKO-) require differential termi-
nation between inverting noninverting outputs. terminate these outputs ground. parallel data parallel clock LVDS inputs (PD_+, PD_-, PCLKI+, PCLKI-, RCLK+, RCLK-) internally terminated with differential input resistance, therefore require external termination.
PECL Outputs
serial-data PECL outputs (SD+, SD-) require termination (VCC (see Alternative PECLOutput Termination section).
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs
Applications Information
Alternative PECL-Output Termination
Figure shows alternative PECL output-termination methods. Thevenin-equivalent termination when (VCC termination voltage available. coupling necessary, sure that coupling capacitor placed following Thevenin-equivalent termination.
FIL+ FILVCC CKSET
Configuration
VIEW
MAX3693
Layout Techniques
best performance, good high-frequency layout techniques. Filter voltage supplies keep ground connections short. multiple vias where possible. Also, controlled-impedance transmission lines interface with MAX3693 clock data inputs outputs.
RCLK+ RCLKVCC PCLKI+ PCLKIGND
MAX3693
SDVCC PCLKO+ PCLKOGND
MAX3693
PECL INPUTS
_Chip Information
TRANSISTOR COUNT: 2925
MAX3693
HIGHIMPEDENCE INPUTS
Figure Alternative PECL-Output Termination
PD0+ PD0PD1+ PD1PD2+ PD2PD3+ PD3-
+3.3V
TQFP
+3.3V, 622Mbps, SDH/SONET Serializer with Clock Synthesis LVDS Inputs MAX3693
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
32L/48L,TQFP.EPS
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

ATION EVALU ILABLE +3.3V, 622Mbps, SDH/SONET Serializer with Cloc

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