V53C517400A Max. Access Time, (tRAC) Max. Column Address Access T
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V53C517400A FAST PAGE MODE CMOS DYNAMIC
V53C517400A
Max. Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC)
Features
4-bit organization Fast Page Mode sustained data rate access time: power dissipation Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh Self-Refresh Refresh Interval: 2048 cycles/32 Available 24/26-pin SOJ, 24/26-pin TSOP-II Single ±10% Power Supply Interface
Description
V53C517400A 4,194,304 highperformance CMOS dynamic random access memory. V53C517400A offers Page mode operation. V53C517400A symmetric address, 11-bit 11-bit column, refresh. inputs compatible. Fast Page Mode operation allows random access 2048 bits, within page, with cycle times short 35ns. These features make V53C517400A ideally suited wide variety high performance computer systems peripheral applications.
Device Usage Chart
Operating Temperature Range
70°C
Package Outline
Access Time (ns)
Power Std.
Temperature Mark
Blank
V53C517400A Rev. March 1998
24/26-Pin Plastic SOJ/TSOP-II CONFIGURATION View
I/O1 I/O2
311740002-02
V53C517400A
Names
A0-A10 Row, Column Address Inputs Address Strobe Column Address Strobe Write Enable Output Enable Data Input, Output Supply Supply Connect
I/O4 I/O3
I/O1-I/O4
Description TSOP-II
Pkg.
Count 26/24 26/24
V53C517400A Rev. March 1998
Operating temperature range Storage temperature range Input/output voltage -0.5 (VCC+0.5, 7.0) Power supply voltage -1.0 Power dissipation Data current (short circuit)
*Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
V53C517400A
Capacitance*
Symbol CIN1 CIN2 COUT
Absolute Maximum Ratings*
25°C, 10%,
Parameter Address Input RAS, CAS, Data Input/Output Typ. Max. Unit
*Note: Capacitance sampled 100% tested.
Block Diagram
4096
I/O1 I/O2 I/O3 I/O4
Data Buffer
Data Buffer
Clock Generator
Column Address Buffers (11)
Column Decoder
Refresh Controller Sense Amplifier Gating Refresh Counter (11) Address Buffers (11) Decoder 2048 Memory Array 2048 2048 2048
Clock Generator
Voltage Down Generator
511740002-04
(internal)
V53C517400A Rev. March 1998
Operating Characteristics (1-2)
70°C, ±10%, unless otherwise specified.
Access Time V53C517400A Min.
V53C517400A
Symbol
ICC1
Parameter
Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Supply Current, Operating Supply Current, Standby Supply Current, RAS-Only Refresh Supply Current, Fast Page Mode Operation Supply Current, during CAS-before-RAS Refresh Supply Current, CMOS Standby
Typ.
Max.
Unit
Test Conditions
VOUT RAS, (min.)
Notes
ICC2 ICC3
RAS, other inputs (min.)
ICC4
Minimum Cycle
ICC5
ICC6
other input
ICC7
Average Self Refresh Current (CBR cycle with tRAS tRASSmin., held low, WE=Vcc-0.2V, Address Din=Vcc-0.2V 0.2V) Power Supply Voltage Input Voltage Input High Voltage Output Voltage Output High Voltage -0.5
IOUT IOUT
V53C517400A Rev. March 1998
Characteristics(5,6)
°C,VCC ±10%,
Symbol Parameter min. max. min.
V53C517400A
max.
Unit
Note
Common Parameters
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tREF Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay hold time hold time precharge time Transition time (rise fall) Refresh period
Read Cycle
tRAC tCAC tCAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD Access time from Access time from Access time from column address access time Column address lead time Read command setup time Read command hold time Read command hold time referenced output low-Z Output buffer turn-off delay Output turn-off delay from Data delay Data delay high data delay high data delay 8,10
V53C517400A Rev. March 1998
Characteristics(5,6)
°C,VCC ±10%,
Symbol Parameter min. max. min.
V53C517400A
max.
Unit
Note
Write Cycle
tWCH tWCS tRWL tCWL Write command hold time Write command pulse width Write command setup time Write command lead time Write command lead time Data setup time Data hold time
Read-modify-Write Cycle
tRWC tRWD tCWD tAWD tOEH Read-write cycle time delay time delay time Column address delay time command hold time
Fast Page Mode Cycle
tCPA tRASP tRHPC Fast Page mode cycle time precharge time Access time from precharge pulse width Fast mode precharge Delay 200k 200k
Fast Page Mode Read-modify-Write Cycle
tPRWC tCPWD Fast Page mode read-write cycle time precharge
CAS-before-RAS Refresh Cycle
tCSR tCHR tRPC tWRP tWRH setup time hold time precharge time Write precharge time Write hold time referenced
CAS-before-RAS Counter Test Cycle
tCPT precharge time
V53C517400A Rev. March 1998
Characteristics(5,6)
°C,VCC ±10%,
Symbol Parameter min. max. min.
V53C517400A
max.
Unit
Note
Test Mode
tWTS tWTH tCHRT tRAHT Write command setup time Write command hold time hold time hold time test mode
Self Refresh Cycle
tRASS tRPS tCHS pulse width precharge time hold time 100k 100k
V53C517400A Rev. March 1998
Notes:
voltages referenced VSS. ICC1, ICC3, ICC4 ICC5 depend cycle rate. ICC1 ICC4 depend output loading. Specified values obtained with output open.
V53C517400A
Address changed once less while VIL. case ICC4 changed once less during Fast Page mode cycle initial pause required after power-up followed cycles which least cycle refresh cycle, before proper device operation achieved. case using internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. measurements assume (min.) (max.) reference levels measuring timing input signals. Transition times also measured between VIL. Measured with specified current load Access time determined latter tRAC, tCAC, tCAA,tCPA, tOEA tCAC measured from tristate. Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only. tRCD greater than specified tRCD (max.) limit, then access time controlled tCAC. Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only. tRAD greater than specified tRAD (max.) limit, then access time controlled tCAA. Either tRCH tRRH must satisfied read cycle. tOFF (max.), tOEZ (max.) define time which output achieves open-circuit conditions referenced output voltage levels. tOFF referenced from rising edge CAS, whichever occurs last. Either tDZC tDZO must satisfied. Either tCDD tODD must satisfied. tWCS, tRWD, tCWD tAWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min.), cycle early write cycle data will remain open-circuit (high impedance) through entire cycle; tRWD tRWD (min.), tCWD tCWD (min.) tAWD tAWD (min.), cycle read-write cycle will contain data read from selected cells. neither above sets conditions satisfied, condition access time) indeterminate. These parameters referenced leading edge early write cycles leading edge readwrite cycles. When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refreshed evenly distributed manner over refresh interval using refresh cycles, then only cycle must performed immediately after exit from Self Refresh. addresses being refreshed other manner (ROR Distributed/Burst; CBR-Burst) over refresh interval, then full refreshes must performed immediately before entry immediately after exit from Self Refresh.
V53C517400A Rev. March 1998
Waveforms Read Cycle
Address Column
V53C517400A
(Inputs)
Valid Data
(Outputs)
V53C517400A Rev. March 1998
Waveforms Write Cycle (Early Write)
tRAS tCSH tRCD tRAD tASR Address tCWL tRAH tWCH tRWL tWCS Column tASC tCAH tRAL tASR tRSH tCAS tCRP
V53C517400A
(Inputs)
Valid Data
(Outputs)
V53C517400A Rev. March 1998
Waveforms Write Cycle Controlled Write)
tRAS tCSH
tRCD tRSH tCAS
V53C517400A
tCRP
Address Column
tCWL
tRWL
tOEH tDZO tDZC (Inputs) Valid Data tCLZ tOEA (Outputs) Hi-Z Hi-Z tOEZ tODD
V53C517400A Rev. March 1998
Waveforms Read-Write (Read-Modify-Write) Cycle
tRWC tRAS tRCD tRAH tASR Address tRAD tAWD tCWD tRWD tCAA tRCS tDZO tDZC (Inputs) Valid Data tCLZ tCAC tOEZ (Outputs) Data tODD tOEA tOEH Column tCWL tRWL tASC tCAH tASR tCSH tRSH tCAS tCRP
V53C517400A
V53C517400A Rev. March 1998
Waveforms Fast Page Mode Read Cycle
tRASP tRCD tRAH tASR Address tRAD tRCH tRCS tCAA tOEA tCPA tCAA tOEA tRCS tRCS Column Column Column tASC tCSH tCAH tCAH tCAH tASC tCAS tCAS tRHCP tRSH tCAS
V53C517400A
tCRP
tASC
tASR tRCH
tCPA tCAA tOEA
tRRH
tDZC tDZO tODD (Inputs) tRAC tCLZ (Outputs)
Valid Data
tDZC tDZO tODD tDZO
tDZC
tCDD
tODD
tCAC
tOFF tOEZ
tCAC tCLZ
tOFF tOEZ
tCAC
tOFF tOEZ
Valid Data
tCLZ
Valid Data
FPM1
V53C517400A Rev. March 1998
Waveforms Fast Page Mode Early Write Cycle
V53C517400A
tRASP
tRCD
tCRP
tRSH tCAS tCAS
tCRP
tCAS
tRAL tRAH tASC tASR tCAH tASC tCAH tASC tCAH tASR
Address
Addr tRAD tCWL tWCS tWCH tWCS
Column
Column tRWL
Column
tCWL tWCH tWCS
tCWL tWCH
(Input)
Valid Data
Valid Data
Valid Data
(Outputs)
FPM2
V53C517400A Rev. March 1998
V53C517400A Rev. March 1998
Waveforms Fast Page Mode Late Write Read-Modify-Write Cycle
tRASP
tCSH tRCD tCAS tRAD tASR tRAH tASC Column tRWD tCWD tCAH tCAH tASC Column Address tCWL tCPWD tCWD
tPRWC tCAS tCAS tRAL tASR tRSH tCRP
tCAH tASC Column tCWL tCPWD tCWD
Address
tRWL tCWL tAWD
tRCS
tAWD tCAA tOEA
tAWD tOEA
(Inputs) (Outputs)
WL17
tOEA
tDZC
tCLZ
tCPA tDZC Data tODD Data tDZC
tCPA
tDZO
tODD
Data tCLZ
tCLZ
tCAC tRAC
tODD tOEZ
Data
tOEH tCAA tOEZ
Data
tOEH tCAA
tOEH tCAC tOEZ
Data
V53C517400A
Waveforms Only Refresh Cycle
V53C517400A
tRAS
tRPC
tCRP
tRAH tASR tASR
Address
(Outputs)
HI-Z
V53C517400A Rev. March 1998
Waveforms CAS-before-RAS Refresh Cycle
V53C517400A
tRAS
tRPC
tCSR tCHR tRPC
tCRP
tWRP tWRH
tOEZ
tCDD
(Inputs)
tODD
(Outputs)
HI-Z
tOFF
WL10
V53C517400A Rev. March 1998
Waveforms Hidden Refresh Read Cycle
tRAS tRAS
V53C517400A
tRCD
tRSH tCHR tCRP
tRAD tASC tRAH tASR tCAH tWRP tWRH tASR
Address
Column
tRCS
tRRH
tCAA tOEA
tDZC tDZO
tCDD tODD
(Inputs)
tCAC tCLZ tRAC tOEZ
tOFF
(Outputs)
Valid Data
HI-Z
WL11
V53C517400A Rev. March 1998
Waveforms Hidden Refresh Early Write Cycle
V53C517400A
tRAS
tRAS
tRCD
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH Column tWCS tWCH tWRP tWRH tASR
Address
(Input)
Valid Data
(Output)
HI-Z
WL12
V53C517400A Rev. March 1998
Waveforms CAS-before-RAS Refresh Counter Test Cycle
tRAS Read Cycle:
V53C517400A
tCSR
tCHR
tRSH tCAS
tRAL tASC Address
tCAH
tASR tRRH tRCH
Column tWRP tCAA tCAC tWRH tRCS tOEA
(Inputs) (Outputs)
tDZC tODD tDZO tCLZ tOEZ Data tOFF
tCDD
tWRP Write Cycle:
tWCS
tRWL tCWL tWCH
tWRH
(Inputs) (Outputs)
Data
HI-Z
V53C517400A Rev. March 1998
Waveforms Test Mode Entry
V53C517400A
tRAS
tRPC tCSR tCHRT tRPC tCRP
tASR
tRAHT
Address
tWTS
tWTH
tODD (Inputs)
HI-Z
tCDD
tOEZ (Outputs)
HI-Z
tOFF
WL15
V53C517400A Rev. March 1998
Waveforms CAS-before-RAS Self Refresh Cycle
tRASS tRPS
V53C517400A
tRPC tCSR tCHS tCRP
tWRP tWRH
tCDD (Inputs)
tODD tOEZ HI-Z
(Outputs)
tOFF WL13
V53C517400A Rev. March 1998
Test Mode
V53C517400A organized internally 16-bits, test mode cycle using compression used improve test time. Note that version test time reduced test pattern. test mode "write" data from each written into four blocks simultaneously (all test mode "read" each output used indicating test mode result. internal four bits equal, would indicate "1".
V53C517400A
they were equal, would indicate "0". WCBR cycle (WE, before RAS) puts device into test mode. exit from test mode, "CAS before refresh", "RAS only refresh" "Hidden refresh" used.Refresh during test mode operation performed normal read cycles WCBR refresh cycles. addresses through have kept high perform testmode entry cycle. other addresses don't care.
Block Diagram Test Mode
A0C,A1C A0C,A1C Normal
Block Block Block Block
Test A0C,A1C
Test
Normal
A0C,A1C Normal
Block Block Block
Normal
Test Test
Block
A0C,A1C A0C,A1C Normal
Block Block
Normal
Test
Block Block
Test
A0C,A1C A0C,A1C Normal
Block Block
Normal
Test
Block
Test
Block
V53C517400A Rev. March 1998
Package Diagrams
24/26-pin
0.104 0.003 [2.64 0.1] 0.020 [0.5] 0.315 [0.8] 0.148 -0.020 [3.75 -0.5] 0.305 -0.009 [7.75 -0.25]
V53C517400A
0.008 +0.003 [0.2 +0.1]
0.335 [0.85] [1.27] 0.020 -0.003 [0.51 -0.1] 0.007 [0.18] [15.24] [0.003] 0.009 [0.25]
0.268 ±0.008 [6.8 ±0.2] 0.340 -0.009 [8.63 -0.25]
0.009 [0.25] 0.007 [0.18]
Index Marking
0.680 -0.009 [17.27 -0.25]
Units inches [mm]
Does include plastic metal protrusion 0.15 max. side
24/26-pin TSOP-II
0.039 0.002 [1.0 0.05] 0.006 ±0.002 [0.15±0.05] 0.050 [1.27 max] 0.005 [7.62 0.13] 0.006
+0.003 -0.004
0.15 +0.08 -0.09
max. 0.05 [1.27] 0.016
+0.005 -0.004
0.004 [0.1] 0.008 [0.2]
0.024 -0.008 [0.6 -0.2] 0.363 0.008 [9.22 0.2]
+0.12 -0.1
0.680±0.005 [17.27±0.13]
Unit inches [mm]
Does include plastic metal protrusion 0.15 max. side
V53C517400A Rev. March 1998
Notes
V53C517400A
V53C517400A Rev. March 1998
Notes
V53C517400A
V53C517400A Rev. March 1998
Notes
V53C517400A
V53C517400A Rev. March 1998
U.S.A.
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WORLDWIDE OFFICES
TAIWAN
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V53C517400A
GERMANY (CONTINENTAL EUROPE ISRAEL
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JAPAN
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IRELAND
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U.S. SALES OFFICES
NORTHWESTERN
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Copyright 1998, MOSEL VITELIC Inc.
3/98 Printed U.S.A.
information this document subject change without notice. MOSEL VITELIC makes commitment update keep current information contained this document. part this document copied reproduced form means without prior written consent MOSEL-VITELIC.
MOSEL VITELIC subjects products normal quality control sampling techniques which intended provide assurance high quality products suitable usual commercial applications. MOSEL VITELIC does testing appropriate provide 100% product quality assurance does assume liability consequential incidental arising from products. such products used applications which personal injury might occur from failure, purchaser must quality assurance testing appropriate such applications.
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