STAGES TOTAL GAIN 72dB INHI 12dB INLO LADR ATTEN BIAS CTRL DETECTORS S
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MHz-500 Demodulating Logarithmic Amplifier with Limiter Output AD8309
STAGES TOTAL GAIN 72dB INHI 12dB INLO LADR ATTEN BIAS CTRL DETECTORS SPACED 12dB 12dB 12dB LMLO LMDR GAIN 18dB LMHI
FEATURES Complete Multistage Log-Limiting Amplifier Dynamic Range: Stable RSSI Scaling Over Temperature Supplies: mV/dB Slope, Intercept RSSI Linearity Programmable Limiter Gain Output Current Differential Outputs Overall Gain Bandwidth Constant Phase (Typical Delay Skew) Single Supply +2.7 +6.5 Typical Fully Differential Inputs, Power-Up Time, Sleep Current APPLICATIONS Receivers Frequency Phase Modulation Very Wide Range Power Measurement Receiver Signal Strength Indication (RSSI) Cost Radar Sonar Signal Processing Instrumentation: Network Spectrum Analyzers
VLOG FLTR
ENBL
GAIN BIAS
BAND-GAP REFERENCE
SLOPE BIAS
INTERCEPT TEMP COMP
PRODUCT DESCRIPTION
AD8309 complete limiting amplifier, providing both accurate logarithmic (decibel) measure input signal (the RSSI function) over dynamic range programmable limiter output, useful from MHz. easy use, requiring external components. single supply voltage +2.7 +6.5 needed, corresponding power consumption under plus limiter bias current, determined application typically providing limiter gain when using loads. CMOS-compatible control interface enable AD8309 within about disable standby current under cascaded amplifier/limiter cells main path have small signal gain 12.04 with bandwidth MHz, providing total gain programmable output stage provides further gain. input fully differential presents moderately high impedance parallel with pF). input-referred noise-spectral-density, when driven from terminated source 1.28 nV/Hz, equivalent noise figure sensitivity AD8309 raised using input matching network. Each main gain cells includes full-wave detector. additional four detectors, driven broadband attenuator, used extend dynamic range over REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
overall dynamic range this combination extends from (-78 level) maximum permissible value dBV, using balanced drive antiphase inputs each amplitude, which would correspond sine wave power differential input were terminated slope RSSI output closely controlled mV/dB, while intercept -108 (-95 These scaling parameters determined bandgap voltage reference substantially independent temperature supply. logarithmic conformance typically within over central this range frequency between MHz, degraded only slightly MHz. RSSI response time nominally (10%-90%). averaging time increased without limit addition external capacitor. full output 2.34 maximum input drive resistive load down this interface remains stable with value capacitance output. AD8309 fabricated advanced complementary bipolar process using silicon-on-insulator isolation techniques available industrial temperature range -40°C +85°C, 16-lead TSSOP package.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Site: http://www.analog.com Fax: 781/326-8703 Analog Devices, Inc., 1999
AD8309-SPECIFICATIONS unless otherwise noted)
Parameter INPUT STAGE Maximum Input2 Equivalent Power Noise Floor Equivalent Power Input Resistance Input Capacitance Bias Voltage LIMITING AMPLIFIER Usable Frequency Range Limiter Output Phase Variation Limiter Output Current Input Range3 Maximum Output Voltage Rise/Fall Time (10%-90%) LOGARITHMIC AMPLIFIER Error Dynamic Range Transfer Slope Intercept (Log Offset)
Conditions (Inputs INHI, INLO) Differential Drive, Terminated 52.3 Terminated Source Bandwidth From INHI INLO From INHI INLO Either Input (Outputs LMHI, LMLO) RLOAD RLIM Point Over Input Range Nominally mV/RLIM Versus Temperature -40°C +85°C Equivalent Either LMHI LMLO, VPS2 RLOAD RLIM (Output VLOG) From Noise Floor Maximum Input Over Temperature -40°C +85°C Equivalent Over Temperature -40°C +85°C Equivalent Temperature Sensitivity Input from (-70 dBm) (+20 dBm) Input (-78 dBm) +2.7 Input (+22 dBm) Input (+22 dBm) +2.75 Ground
Min1
1.28 1000 1.725
Max1
Units nV/Hz Degrees %/°C mV/dB mV/dB dB/°C
1200
-0.008
1.25 -108 -108 -0.009 0.34 2.34 2.10
-116 -103 -117 -104
-100
Linearity Error (Ripple) Output Voltage
2.75
Minimum Load Resistance, Maximum Sink Current Output Resistance Small-Signal Bandwidth Output Settling Time Rise/Fall Time (10%-90%) POWER INTERFACES Supply Voltage, VPOS Quiescent Current Over Temperature Disable Current Additional Bias Limiter Logic Level Enable Power Input Current when Logic Level Disable Power
0.75
1.25
Large Scale Input, (+16 dBm), Large Scale Input, (+16 dBm),
VPOS
Zero-Signal, LMDR Open -40°C +85°C -40°C +85°C RLIM (See Text) Condition, -40°C +85°C ENBL, -40°C +85°C Condition, -40°C +85°C
0.01
-0.5
NOTES Minimum maximum specified limits parameters that guaranteed tested sigma values. input level specified "dBV" since logarithmic amplifiers respond strictly voltage, power. corresponds sinusoidal single-frequency input rms. power level termination corresponds input 0.2236 rms. Hence, relationship between fixed offset special case termination. extremely high Gain Bandwidth Product AD8309, output either LMHI LMLO will unstable levels below (-65 dBm, Specifications subject change without notice.
REV.
AD8309
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Input Level, Differential Input Level, Single-Ended Internal Power Dissipation 150°C/W .27.6°C/W Maximum Junction Temperature +125°C
Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature Range (Soldering sec) +300°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods effect device reliability.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8309ARU -40°C +85°C 16-Lead TSSOP RU-16 AD8309ARU-REEL -40°C +85°C Tape Reel RU-16 AD8309ARU-REEL7 -40°C +85°C Tape Reel RU-16 AD8309-EVAL Evaluation Board
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD8309 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
FUNCTION DESCRIPTIONS
CONFIGURATION
Name
Function
COM2 VPS1 PADL INHI
COM2 Special Common RSSI Output. VPS1 Supply First Five Amplifier Stages Main Biasing System. PADL Four Tie-Downs Paddle Which Mounted; Grounded. INHI Signal Input, Plus Polarity. INLO Signal Input, Minus Polarity. COM1 Main Common Connection. ENBL Chip Enable; Active When LMDR Limiter Drive Programming Pin. FLTR RSSI Bandwidth-Reduction Pin. LMLO Limiter Output, Minus Polarity. LMHI Limiter Output, Plus Polarity. VPS2 Supply Sixth Gain Stage, Limiter RSSI Output Stage Load Current. VLOG Logarithmic (RSSI) Output.
VLOG VPS2 PADL
LMHI VIEW INLO (Not Scale) LMLO
AD8309
PADL COM1 ENBL
PADL FLTR LMDR
REV.
AD8309-Typical Performance Characteristics
VLOG
SUPPLY CURRENT
0.01 0.001 GROUND REFERENCE +10dBm INPUT LEVEL SHOWN HERE 500mV VERTICAL DIVISION 500mV VERTICAL DIVISION
0.0001 0.00001 100ns HORIZONTAL DIVISION ENABLE VOLTAGE
Figure Supply Current Enable Voltage
Figure RSSI Pulse Response Inputs Stepped from Zero dBV, dBV, dBV,
VLOG 500mV VERTICAL DIVISION
-13dBV -33dBV -53dBV -73dBV -93dBV
VLOG 500mV VERTICAL DIVISION
GROUND REFERENCE ENBL VERTICAL DIVISION 500ns HORIZONTAL DIVISION
GROUND REFERENCE
100ns HORIZONTAL DIVISION
INPUT VERTICAL DIVISION
Figure Power On/Off Response Time with Input
Figure Large Signal RSSI Pulse Response with (Curves Overlap)
27pF
VLOG
270pF
VLOG
500mV VERTICAL DIVISION GROUND REFERENCE
3300pF
200mV VERTICAL DIVISION
GROUND REFERENCE
INPUT 500mV VERTICAL DIVISION 200ns HORIZONTAL DIVISION
HORIZONTAL DIVISION
Figure Large Signal RSSI Pulse Response with (Curves Overlap)
Figure Small Signal Response RSSI Output with External Filter Capacitance 3300
REV.
AD8309
RSSI OUTPUT
ERROR
-100 INPUT LEVEL
-100 INPUT LEVEL
Figure RSSI Output Input Level, Sine Input, Single-Ended Input
Figure Linearity RSSI Output Input Level, Sine Input, -40°C, +25°C, +85°C
100MHz 50MHz 200MHz 5MHz
ERROR
5MHz
DYNAMIC RANGE 5MHz 50MHz 100MHz 200MHz
RSSI OUTPUT
50MHz
100MHz 200MHz
-100
INPUT LEVEL
INPUT LEVEL
Figure RSSI Output Input Level, Frequencies MHz, MHz,
Figure Linearity RSSI Output Input Level, Frequencies MHz, MHz,
300MHz 400MHz 500MHz
DYNAMIC RANGE 300MHz 400MHz 500MHz
RSSI OUTPUT
ERROR
300MHz 500MHz 400MHz
-100
INPUT LEVEL
INPUT LEVEL
Figure RSSI Output Input Level, +25°C, Frequencies MHz,
Figure Linearity RSSI Output Input Level, +25°C, Frequencies MHz,
REV.
AD8309
FREQUENCY 1000
RSSI INTERCEPT RSSI SLOPE mV/dB
-103 -104 -105 -106 -107 -108 -109 -110 -111 -112 -113 FREQUENCY 1000
Figure RSSI Slope Frequency Using Termination 52.3 Series with
Figure RSSI Intercept Frequency Using Termination 52.3 Series with
HORIZONTAL DIVISION
CURRENT
LIMITER OUTPUTS
100mV VERTICAL DIVISION
ADDITIONAL SUPPLY CURRENT
VERTICAL DIVISION
LIMITER OUTPUT CURRENT RLIM
Figure Limiter Output Sine Wave Input (-47 dBm), Using RLOAD RLIM
Figure Additional Supply Current Limiter Output Current RLIM
NORMALIZED LIMITER PHASE RESPONSE Degrees INPUT LEVEL
LMLO LMHI LIMITER OUTPUTS 50mV VERTICAL DIVISION INPUT
VERTICAL DIVISION 12.5ns HORIZONTAL DIVISION
Figure Limiter Response LMHI, LMLO with Pulsed Sine Input (-57 dBm) MHz; RLOAD RLIM
Figure Normalized Limiter Phase Response Input Level. Frequency MHz; -40°C, +25°C
REV.
AD8309
THEORY OPERATION
AD8309 advanced signal processing intended high performance receivers, combining functions. First, provides large voltage gain combined with progressive compression, through which signal high dynamic range converted into square-wave (that hard limited) output, from which frequency phase information modulated this input recovered subsequent signal processing. this purpose, noise level referred input must very low, since determines detection threshold receiver. Further, often important that group delay this amplifier essentially independent signal level, minimize risk amplitude-to-phase conversion. Finally, also desirable that amplitude limited output well defined temperature stable. AD8309, this amplitude controlled user, even completely shut off, providing greater flexibility. second function provide demodulated (baseband) output proportional decibel value signal input, which used measure signal strength. This output, which typically runs from value close ground level volts above ground, called Received Signal Strength Indication, RSSI. provision this function requires logarithmic amplifier (log amp). this output suitable measuring signal strength, important that scaling attributes well controlled. These logarithmic slope, specified mV/dB, intercept, often specified equivalent power level amplifier input, although inherently voltageresponding device. (See further discussion, below). Also important conformance, that well RSSI approximates ideal function. Many quality amps provide only approximate solution, resulting large errors conformance scaling. Analog Devices amps designed with close attention matters affecting accuracy overall function. AD8309, these basic signal-processing functions combined provide necessary voltage gain with progressive compression hard limiting, determination logarithmic magnitude input (RSSI). This combination called limiting amplifier. good grasp this product works will avoid many pitfalls their application.
Log-Amp Fundamentals
references. Note that mathematically incomplete representing behavior demodulating such AD8309, where alternating sign. However, basic principles unaffected. Figure shows input/output relationship ideal amp, conforming Equation (1). horizontal scale logarithmic, spans very wide dynamic range, shown here over that decades voltage twelve decades input-referred power. output passes through zero (the "log-intercept") unique value becomes negative inputs below intercept. ideal case, straight line describing VOUT values would continue indefinitely both directions. dotted line shows that effect adding offset voltage VSHIFT output lower effective intercept voltage
VOUT VSHIFT VOUT 10-2VX -40dBc 0dBc 102VX +40dBc 104VX +80dBc LOWER INTERCEPT
-2VY
Figure Ideal Function
Exactly same modification could achieved raising gain signal level) ahead factor VSHIFT/VY. example, mV/decade (that mV/dB, AD8309), offset added output will appear lower intercept tenths decade, Adding offset output thus indistinguishable from applying input level that higher. function described differs from that linear amplifier that incremental gain DVOUT/DVIN very strong function instantaneous value VIN, apparent calculating derivative. case where logarithmic base easy show that
essential purpose logarithmic amplifier reduce signal wide dynamic range decibel equivalent. thus primarily measurement device. logarithmic representation leads situations that confusing even paradoxical. example, voltage offset added RSSI output equivalent gain increase ahead input. When variables expressed voltages, then, regardless particular structure, output expressed VOUT (VIN /VX) where "slope voltage." input voltage, "intercept voltage." logarithm usually base-10, which appropriate decibel-calibrated device, which case also "volts-per-decade." will apparent from that requires references, here that determine scaling circuit. absolute accuracy cannot better than accuracy scaling REV.
VOUT
That incremental gain inversely proportional instantaneous value input voltage. This remains true logarithmic base. "perfect" would required have infinite gain under classical "small-signal" (zero-amplitude) conditions. This demonstrates that, whatever means might used implement amp, accurate response under small signal conditions (that lower full dynamic range) demands provision very high gain-bandwidth product. wideband must therefore many cascaded gain cells each gain high bandwidth. AD8309, gain-bandwidth (-10 product 52,500 GHz.
AD8309
consequence this high gain, even very small amounts thermal noise input will cause finite output zero input, resulting response line curving away from ideal (Figure small inputs, toward fixed baseline. This either above below intercept, depending design. Note that value specified this intercept invariably extrapolated one: RSSI output voltage will never attain value exactly zero single supply implementation.
Voltage (dBV) Power (dBm) Response
STAGE STAGE STAGE STAGE
Figure Cascade Nonlinear Gain Cells
Theory Logarithmic Amplifiers
While Equation fundamentally correct, simpler formula appropriate specifying RSSI calibration attributes like AD8309, which demodulates input. usual measure input power: VOUT VSLOPE (PIN VOUT demodulated filtered RSSI output, VSLOPE logarithmic slope, expressed volts/dB, input power, expressed decibels relative some reference power level logarithmic intercept, expressed decibels relative same reference level. most widely used convention systems specify power decibels above written dBm. (However, that quantity [PIN simply dB). logarithmic function disappears from this formula because conversion already been implicitly performed stating input decibels. Specification input level terms power strictly concession popular convention: they respond power (tacitly "power absorbed input"), input voltage. this connection, note that input impedance AD8309 much higher that allowing impedance transformer input raise sensitivity, dBV, defined decibels with respect sine amplitude, more precise, although this still unambiguous complete general metric, because waveform also involved response amp, which, complex input (such CDMA signal) will follow value exactly. Since most users specify signals terms power-more specifically, dBm/50 both specifying performance AD8309, showing equivalent levels special case environment.
Progressive Compression
develop theory, will first consider somewhat different scheme that employed AD8309, which simpler explain, mathematically more straightforward analyze. This approach based nonlinear amplifier unit, which call cell, having transfer characteristic shown Figure here lowercase variables define local inputs outputs these cells, reserving uppercase external signals. small signal gain VOUT/VIN maintained inputs knee voltage above which incremental gain drops unity. function symmetrical: same drop gain occurs instantaneous values less than -EK. large signal gain value inputs range +EK, falls asymptotically toward unity very large inputs. logarithmic amplifiers based this simple function, both slope voltage intercept voltage must traceable reference voltage, Therefore, this fundamental analysis, calibration accuracy dependent solely this voltage. practice, possible separate basic references used determine AD8309, traceable on-chip band-gap reference, while derived from thermal voltage kT/q later temperature-corrected precise means. input N-cell cascade VIN, final output VOUT. small signals, overall gain simply sixstage system which overall gain 15,625 dB). importance very high small-signal gain implementing logarithmic function already been noted. However, this parameter only incidental interest design amps; greater emphasis needs placed nonlinear behavior.
High speed, high dynamic range amps cascade nonlinear amplifier cells (Figure generate logarithmic function from series contiguous segments, type piecewise-linear technique. This basic topology offers enormous gainbandwidth products. example, AD8309 employs main signal path cells each having small-signal gain 12.04 bandwidth MHz, followed final limiter stage whose gain typically overall gain thus 100,000 (100 bandwidth point limiter output MHz. This very high gainbandwidth product (52,500 GHz) essential prerequisite accurate operation under small signal conditions high frequencies: Equation reminds that incremental gain decreases rapidly increases. AD8309 exhibits logarithmic response over most range from noise floor dBV, rms, dBm/50 breakdownlimited peak input (requiring balanced drive differential inputs INHI INLO).
OUTPUT
SLOPE
SLOPE
INPUT
Figure Amplifier Function
Thus, rather than considering gain, will analyze overall nonlinear behavior cascade response simple input, corresponding Equation (1). very small inputs, output from first cell AVIN; from second, VIN, VIN. certain value VIN, input cell, VN-1, exactly equal knee voltage Thus, VOUT since there cells gain ahead this node, calculate that /AN-1. This unique point corresponds lin-log transition, REV.
AD8309
labeled Figure Below this input, cascade gain cells acting simple linear amplifier, while higher values VIN, enters into series segments which logarithmic approximation. Continuing this analysis, find that next transition occurs when input (N-1)th stage just reaches that when /AN-2. output this stage then exactly AEK. easily demonstrated (from function shown Figure that output final stage (2A-1)EK (labeled Figure 22). Thus, output changed amount (A-1)EK change from /AN-1 /AN-2, that ratio change
SLOPE OUTPUT
SLOPE
INPUT
Figure Amplifier Functions (Ideal tanh)
VOUT (4A-3) (3A-2) (A-1) (2A-1) EK/AN-1 EK/AN-2 EK/AN-3 EK/AN-4
Care needed interpretation this parameter. earlier defined input voltage which output passes through zero (see Figure 19). Clearly, absence noise offsets, output amplifier chain shown Figure only zero when This anomaly finite gain cascaded amplifier, which results failure maintain logarithmic approximation below "lin-log transition" (Point Figure 22). Closer analysis shows that voltage given Equation represents extrapolated, rather than actual, intercept.
Demodulating Amps
RATIO
Figure First Three Transitions
next critical point, labeled input times larger VOUT increased (3A-2)EK, that another linear increment (A-1)EK. Further analysis shows that, right point where input first cell reaches knee voltage, VOUT changes (A-1)EK ratio change VIN. Expressed certain fraction decade, this simply log10(A). example, when transition piecewise linear output function occurs regular intervals decade (log10(A), divided dB). This insight allows immediately state "Volts Decade" scaling parameter, which also "Scaling Voltage" when using base-10 logarithms:
amps based cascade cells useful baseband (pulse) applications, because they demodulate their input signal. Demodulating (detecting) log-limiting amplifiers such AD8309 different type amplifier stage, which will call cell. function differs from that cell that gain above knee voltage falls zero, shown solid line Figure This also known limiter function, chain such cells often used alone generate hard limited output, recovering signal modes. AD640, AD606, AD608, AD8307, AD8309, AD8313 other Analog Devices communications products incorporating logarithmic amplifier this technique. will apparent that output last stage cannot provide logarithmic output, since this remains unchanged inputs above limiting threshold, which occurs /AN-1. Instead, logarithmic output generated summing outputs stages. full analysis this type only slightly more complicated than that previous case. shown that, practical purpose, intercept voltage identical that given Equation (5), while slope voltage
Linear Change inVOUT Decades Change inVIN log10(
Note that only design parameters involved determining namely, cell gain knee voltage while number stages, unimportant setting slope overall function. slope would rather awkward 572.3 decade (28.6 mV/dB). well designed practical will provide more rational scaling parameters. intercept voltage determined solving Equation pairs transition points output function (see Figure 22). result
+1/[ A-1])
log10(
example under consideration, using evaluates 4.28 which thus this analysis still simple voltage.
cell very simple. AD8309 based bipolar-transistor differential pair, having resistive loads emitter current source This amplifier limiter cell exhibits equivalent knee-voltage 2kT/q small-signal gain IERL /EK. large signal transfer function hyperbolic tangent (see dotted line Figure 23). This function very precise, deviation from ideal form detrimental. fact, "rounded shoulders" tanh function beneficially result lower ripple logarithmic conformance than that which would obtained using ideal function. practical amplifier chain built these cells differential structure from input final output,
REV.
AD8309
sensitivity disturbances supply lines. With careful design, sensitivities many other parametric variations, effects temperature supply voltage, reduced negligible proportions.
STAGE STAGE STAGE VLIM
Intercept Calibration
VLOG
Monolithic amps from Analog Devices incorporate accurate means position intercept voltage equivalent sinewave power demodulating amp, when driven specific impedance level). Using scheme shown Figure value intercept level departs considerably from that predicted simple theory. Nevertheless, intrinsic intercept voltage still proportional which PTAT (proportional absolute temperature). Recalling that addition offset output produces effect which indistinguishable from change position intercept, will apparent that cancel "left-right" motion resulting from temperature variation simply adding offset demodulated output having required temperature behavior. precise temperature-shaping intercept-positioning offset result having stable scaling parameters, making true measurement device, example, calibrated Received Signal Strength Indicator (RSSI). this application, more interested value output input waveform which often sinusoidal (CW). input level stated equivalent power, dBm, essential know impedance level which this "power" presumed measured. impedance corresponds sinusoidal amplitude 316.2 (223.6 rms). AD8309, intercept specified when input impedance lowered addition shunt resistor 52.3 which case occurs dBm. However, response actually voltage input, power termination resistor, should specified dBV. sine input across resistance corresponds amplitude -108 dBV, where specified sine waveform rms, that p-p. Note that amp's intercept function waveform. example, square-wave input will read higher than sinewave same amplitude, Gaussian noise input higher than sine wave same value. Further, driven sinusoidal voltages equal amplitude will show output that only higher than response single sine wave drive, rather than that might expected device truly responded input power. These characteristics exhibited demodulating amps.
Dynamic Range
+TOP-END DETECTORS
CURRENT-SUMMING LINE RSLOPE
Figure Basic Structure Using Stages Transconductance (gm) Cells Summing
output each gain cell associated transconductance (gm) cell, which converts differential output voltage cell pair differential currents; these summed simply connecting outputs (detector) stages parallel. total current then converted back voltage transresistance stage, which determines slope logarithmic output. This general scheme depicted, simplified single-sided form, Figure Additional detectors, driven passive attenuator, added extend dynamic range. slope voltage decoupled from knee-voltage 2kT/q, which inherently PTAT. detector stages biased with currents (not shown Figure) which derived from band-gap reference thus stable with temperature. This architecture used AD8309. affords complete control over magnitude temperature behavior logarithmic slope. further step needed achieve demodulation response, required log-limiter convert alternating input into quasi- baseband output. This achieved modifying cells used summation purposes implement rectification function. Early amps based progressive compression technique used half-wave rectifiers, which made post-detection filtering difficult. AD640 first commercial monolithic full-wave rectifier; this proprietary practice been used subsequent Analog Devices types. model these detectors being essentially linear cells, producing output current that independent sign voltage applied input. That they implement absolute-value function. Since output from later stages closely approximates amplitude symmetric square wave even moderate input levels, current output from each detector almost constant over each period input. Somewhat earlier detectors stages chain produce waveform having only very brief "dropouts" twice input frequency. Only those detectors nearest amp's input produce level waveform that approximately sinusoidal. When these (current mode) outputs summed, resulting signal waveform which readily filtered, provide residual ripple output.
lower dynamic range determined largely thermal noise floor, measured input amplifier chain. AD8309, short-circuit input-referred noise-spectral density nV/Hz, 1.275 nV/Hz when driven from source impedance terminated This corresponds noise power bandwidth. upper dynamic range extended upward addition top-end detectors driven tapped attenuator. These smaller signals applied additional full-wave detectors whose outputs summed with those main detectors. With care design, this extension dynamic range `seamless' over full frequency range. AD8309 amounts further When using supply greater, input amplitude accommodated, corresponding power level larger input voltage cause damage.) REV.
-10-
AD8309
total dynamic range AD8309, defined ratio maximum permissible input noise floor, thus Good accuracy provided over substantial part this range.
Input Matching
sine wave input having amplitude greater, RLOAD change time-delay ("phase skew") over input range (100 amplitude, dBm) (±3° MHz).
STAGES TOTAL GAIN 72dB INHI 12dB INLO LADR ATTEN BIAS CTRL DETECTORS SPACED 12dB 12dB 12dB LMLO LMDR GAIN 18dB LMHI
Monolithic amps present nominal input impedance much higher than AD8309, this modeled shunted frequencies MHz. Thus, simple input matching network considerably improve basic sensitivity when driving from low-impedance source, increasing voltage applied input. 50:1000 transformation, voltage gain whole dynamic range moves downward this amount; that intercept shifted -121 (-108 primary input). Note that while useful voltage gain achieved this way, does follow that noise-figure minimal optimum power match.
Offset Control
VLOG FLTR
ENBL
GAIN BIAS
BAND-GAP REFERENCE
SLOPE BIAS
INTERCEPT TEMP COMP
Figure Main Features AD8309
monolithic amp, direct-coupling between stages invariably utilized practical reasons. Now, offset voltage early stages chain indistinguishable from "real" signal. high would larger than smallest resolvable signal µV), reducing dynamic range this amount. This problem solved using global feedback path from last stage first. high-frequency components signal must removed; this achieved AD8309 on-chip low-pass filter, providing sufficient suppression feedback allow accurate operation down least MHz. Useful operation lower frequencies remains possible, although particular device having large offset will exhibit reduction region dynamic range.
PRODUCT OVERVIEW
main cells their associated full-wave detectors, having transconductance (gm) form, handle lower part dynamic range. Biasing these cells provided references, which determines their gain, other being band-gap cell which determines logarithmic slope, stabilizes against supply temperature variations. special dcoffset-sensing cell (not shown Figure placed this main section, used null residual offset input, ensuring accurate response down noise floor. first amplifier stage provides short-circuited voltage-noise spectral-density 1.07 nV/Hz. last detector stage includes modification temperaturestabilize log-intercept, which accurately positioned make optimal full output voltage range. Four further "top end" detectors placed 12.04 taps along passive attenuator, handle upper part range. differential current-mode outputs detectors stages summed with equal weightings converted single-sided voltage output stage, generating logarithmic RSSI) output VLOG (Pin 16), nominally scaled mV/dB (that decade). junction between lower upper regions seamless, logarithmic law-conformance typically well within from (-70 dBm). full-scale rise time RSSI output stage, which operates two-pole low-pass filter with corner frequency MHz, about capacitor connected between FLTR (Pin VLOG used lower corner frequency (see below). output minimum level about 0.34 (corresponding noise power dBm, above nominal intercept dBm). This rather high baseline level ensures that pulse response remains unimpaired very inputs. maximum RSSI output depends supply voltage load. output 2.34 that mV/dB 105) guaranteed when using supply voltage greater load resistance higher, differential input sine amplitude, using balanced drives). When using supply, maximum differential input still high sine amplitude), corresponding RSSI output that mV/dB 105) also guaranteed.
AD8309 built advanced dielectrically-isolated complementary bipolar process using thin-film resistor technology accurate scaling. follows well-developed foundations proven over period some fifteen years, with constant refinement. backbone AD8309 (Figure comprises chain main amplifier/limiter stages, each having gain 12.04 small-signal bandwidth MHz. input interface INHI INLO (Pins fully differential. Thus driven from either single-sided balanced inputs, latter being required very dynamic range, where total differential drive large amplitude. first stages, also used developing logarithmic RSSI output, followed versatile programmable output, thus programmable gain, final limiter section. opencollector outputs also fully differential, LMHI LMLO (Pins 13). This output stage provides gain when using equal valued load bias setting resistors pin-to-pin output used. overall voltage gain thus When using RLIM RLOAD additional current consumption limiter approximately which goes load. ratio depends RLIM (for example, when efficiency 90%), voltage LMDR rather more than total load current accurately (400 mV)/RLIM. rise fall times hard-limited (essentially squarewave) voltage outputs typically when driven REV.
-11-
AD8309
fully-programmable output interface provided hardlimited signal, permitting user establish optimal output current from differential current-mode output. magnitude determined resistor RLIM placed between LMDR (Pin ground, across which nominal bias voltage ~400 appears. Using RLIM this bias current, which commutated alternately output pins, LMHI LMLO, signal, (The total supply current somewhat higher). These currents readily converted voltage form inclusion load resistors, which will typically range from tens ohms high lower frequency applications. Alternatively, resonant load used extract fundamental signal modulation sidebands, minimizing out-of-band noise. transformer impedance matching network also used this output. peak voltage swing down from supply voltage before output transistors into saturation. (The Applications section provides further information this interface). supply current sections except limiter output stage, with load attached RSSI output, nominally 27°C, substantially independent supply voltage. varies direct proportion absolute temperature (PTAT). RSSI load current simply voltage VLOG divided load resistance (e.g., load). limiter supply current times that flowing RLIM. AD8309 enabled/disabled CMOScompatible level ENBL (Pin following simplified interface diagrams, components denoted with uppercase thin-film resistors having very temperature-coefficient resistance high linearity under large-signal conditions. Their absolute value typically within 20%. Capacitors denoted using uppercase have typical tolerance essentially zero temperature voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, active devices protection; these neither accurate stable. Component numbering each these interface diagrams local.
Enable Interface Input Interface
Figure shows essentials signal input interface. parasitic capacitances ground labeled differential input capacitance, mainly diffusion capacitance most applications both input pins accoupled. switch closes when Enable asserted. When disabled, inputs float, bias current shut off, coupling capacitors remain charged. disabled long periods, small leakage currents will discharge these capacitors. they poorly matched, charging currents power-up generate transient input voltage which block lower reaches dynamic range until become much less than signal. most applications, input signal will single-sided, applied either with remaining accoupled ground. Under these conditions, largest input signal that handled (sine amplitude when operating from supply input handled using supply greater. When using fullybalanced drive, level achieved supplies down using >4.5 frequencies range these high drive levels easily achieved using matching network (see later). Using such network, having inductor input, input transient eliminated.
VPS1 1.78V 3.65k SIGNAL INPUT INLO INHI 1.725V 1.725V 2.6k (TOP-END DETECTORS) COMM GAIN BIAS 1.26V 3.4mA PTAT 3.65k 15mA 2.5pF STAGES THRU STAGE
Figure Signal Input Interface
Limiter Output Interface
chip-enable interface shown Figure current controls turn-on turn-off states band-gap reference bias generator, maximum when taken Left unconnected, voltage below AD8309 will disabled, when consumes sleep current much less than (leakage currents only); when tied supply, voltage above will fully enabled. internal bias circuitry requires approximately either while delay some required supply current fall below
ENBL 1.3k BIAS ENABLE
simplified limiter output stage shown Figure bias this stage provided temperature-stable reference voltage nominally which forced across external resistor RLIM connected from (LMDR, limiter drive) special buffer stage. biasing scheme also introduces slight "lift" this voltage compensate finite current gain current source output transistors maximum current permissible (RLIM special applications, desirable modulate bias current; example this provided Applications section. Note that while bias currents temperature stable, gain this stage will vary with temperature, over 120°C range. pair supply temperature stable complementary currents generated differential output LMHI LMLO (Pins 13), having square wave form with rise fall times typically when load resistors used. voltage these output pins swing below supply voltage applied VPS2 (Pin 15). -12- REV.
COMM
Figure Enable Interface
AD8309
Because very high gain bandwidth product this amplifier considerable care must exercised using limiter outputs. minimum necessary bias current voltage swings should used. These outputs best utilized fullydifferential mode. flux-coupled transformer, balun, output matching network selected transform these voltages single-sided form. Equal load resistors recommended, even when only output used, these should always returned same well decoupled node board. When AD8309 used only generate RSSI output, limiter should completely disabled omitting RLIM strapping LMHI LMLO VPS2.
VPS2 LMHI LMLO
RSSI output bandwidth, fLP, nominally MHz. This controlled compensation capacitor which increased adding external capacitor, between FLTR (Pin VLOG (Pin 16). external will reduce kHz, while will kHz, each case with essentially one-pole response. general, relationships are: 12.7 10-10 12.7 10-6
1.3k
1.3k
Using load resistance greater, temperature, peak output voltage least when using supply least supply, which consistent with maximum permissible input levels. incremental output resistance approximately frequencies, rising very high frequencies. output unconditionally stable with load capacitance, should noted while peak sourcing current over able rapidly charge even large capacitances, internally provided sinking current only Thus, fall time from level will long load. This reduced adding grounded load resistance.
USING AD8309
FROM FINAL LIMITER STAGE
400mV 2.6k 1.3k 1.3k COM1 LMDR RLIM ZERO-TC
Figure Limiter Output Interface
RSSI Output Interface
outputs from detectors differential currents, having average value that dependent signal input level, plus fluctuation twice input frequency. currents summed internal nodes shown Figure further current added LGP, position intercept -108 dBV, raising RSSI output voltage zero input, provide temperature compensation resulting stable intercept. zero signal conditions, detector output currents equal. finite input, either polarity, their difference converted output interface single-sided voltage nominally scaled mV/dB (400 decade), output VLOG (Pin 16). This scaling controlled separate feedback stage, having tightly controlled transconductance. small uncertainty slope intercept remains (see Specifications); intercept adjusted (see Applications).
AD8309 exhibits very high gain from over GHz, which frequency gain main path still over Consequently, susceptible signals within this very broad frequency range which find their input terminals. important remember that these quite indistinguishable from "wanted" signal, will have effect raising apparent noise floor (that lowering useful dynamic range). Therefore, while signal interest say, MHz, following could easily larger than this signal lower extremities dynamic range: hum, picked poor grounding techniques; spurious coupling from digital logic same board; strong source; etc. Very careful shielding essential guard against such unwanted signals, also minimize likelihood instability feedback from limiter outputs input. With this mind, minimum possible limiter gain should used. Where only logarithmic amplifier (RSSI) function required, limiter should disabled omitting RLIM tying outputs LMHI LMLO directly VPS2. good ground plane should used provide impedance connection common pins, decoupling capacitor(s) used VPS1 VPS2, output ground. inadvisable assume that ground plane equipotential, however, neither signal inputs should accoupled directly kept separate, being returned instead "low" associated with source. This requires isolating "low"' side input connector with small resistance ground plane. Note that COM2 special ground serving just RSSI output. voltages supply pins should allowed differ greatly; permissible desirable allow VPS1 slightly more negative than VPS2. When primary supply greater than decoupling resistors increased improve isolation lower dissipation However, since VPS2 supports RSSI
VPS2 CURRENT MIRROR ISOURCE >50mA DEMAND FLTR 3.5pF VLOG 20mV/dB
SUMMED 1.3k DETECTOR OUTPUTS VLOG
1.3k
3.3k
3.3k
ISINK FIXED
TRANSCONDUCTANCE DETERMINES SLOPE
COMM
Figure Simplified RSSI Output Interface
REV.
-13-
AD8309
load current, which large, value should take this into account. four pins labeled PADL down directly metallic lead frame, thus connected back chip. process which AD8309 fabricated uses bonded-wafer technique provide silicon-on-insulator isolation, there junction other path from back side circuitry surface. These paddle pins must connected directly ground plane using shortest possible lead lengths minimize inductance.
Basic Connections
100MHz 50MHz 200MHz 5MHz
RSSI OUTPUT
Figure shows connections required most applications. inputs ac-coupled which normally should have same value, say, coupling time constant ROCO where RIN, thus forming high pass corner with attenuation highfrequency applications, should chosen large possible, minimize coupling unwanted signals. other hand, frequency applications, simple network forming low-pass filter should added input same reason.
TEXT MORE ABOUT DECOUPLING VPS1 PADL SIGNAL INPUTS INHI INLO PADL 52.3 COM1 4.7nH ENABLE BROADBAND TERMINATION 1GHz ENBL FLTR RLIM LMDR LMLO PADL RLOAD LMLO VPS2 PADL LMHI RLOAD LMHI
-100
INPUT LEVEL
Figure RSSI Output Input Level Frequencies MHz, MHz,
5MHz DYNAMIC RANGE 5MHz 50MHz 100MHz 200MHz
ERROR
COM2
VLOG
RSSI
50MHz
100MHz 200MHz
AD8309
INPUT LEVEL
CONNECT
Figure Linearity Input Level Frequencies MHz, MHz,
Input Matching
Figure Basic Connections
Where necessary terminate source impedance, resistor should added, with allowance shunting effect input resistance (RIN) AD8309. example, terminate source, 52.3 resistor should used signal frequencies about MHz. termination means placed either input side coupling capacitors. former case smaller capacitors used given frequency range; latter case, resistance lowered directly inputs, which helps keep offsets minimum. higher frequencies, reactance input capacitance must accounted for. inductor series with 52.3 termination resistor provides essentially flat input impedance GHz. impedance-transforming network preferably used provide interface, since this also introduces balanced voltage gain typically AD8309 very high capacity large input voltages. Figure shows output versus input level, with axis marked (correct only when terminated sine inputs MHz, MHz, MHz. Figure shows typical logarithmic linearity (law conformance) under same conditions.
Where either higher sensitivity better high frequency match required, input matching network valuable. Using flux-coupled transformer achieve impedance transformation also eliminates need coupling capacitors, lowers offset voltages generated directly input, usefully balances drives INHI INLO, permitting full utilization unusually large input voltage capacity AD8309. choice turns ratio will depend somewhat frequency. frequencies below MHz, reactance input capacitance much higher than real part input impedance. this frequency range, turns ratio will lower effective input impedance while raising input voltage However, this does lower effect short circuit noise voltage same factor, since there will contribution from input noise current. Thus, total noise will reduced smaller factor. intercept primary input will lowered -120 (-107 dBm).
Impedance matching drive balancing using flux-coupled transformer useful whenever broadband coupling required. However, this always convenient. high frequencies, will often preferable narrow-band matching network, shown Figure which several advantages. First, same voltage gain achieved, providing increased -14- REV.
AD8309
sensitivity, measure selectively simultaneously introduced. Second, component count low: capacitors inexpensive chip inductor needed. Third, network also serves balun. Analysis this network shows that amplitude voltages INHI INLO quite similar when impedance ratio fairly high (say, 1000
COM2 VPS1 INLO PADL COM1 ENBL LMLO PADL FLTR RLIM LMDR PADL INHI VPS2 PADL LMHI LIMITER OUTPUT VLOG RSSI
DECIBELS
GAIN
INPUT TERMINATION
AD8309
FREQUENCY
Figure Response Matching Network
General Matching Procedure
other center frequencies source impedances, following method used calculate basic matching parameters.
Step Tune
CONNECT
Figure High Frequency Input Matching Network
Figure shows response center frequency MHz. response down one-tenth center frequency, falling decade below this. very high frequency attenuation relatively small, however, since limiting case determined simply ratio AD8309's input capacitance coupling capacitors. Table provides solutions variety center frequencies matching from impedances nominally Exact values shown, some judgment needed utilizing nearest standard values.
Table
center frequency shunt impedance input capacitance made disappear resonating with temporary inductor LIN, whose value given 1/{(2 fC)2CIN} 1010/fC2
Step Calculate
when example, MHz, having purely resistive input impedance, calculate nominal coupling elements using
10.7 21.4 REV.
Match (Gain 95.0 71.0 66.5 57.0 47.5 40.7 35.6 31.6 28.5 23.7 17.8 14.2 11.9 4.75 4.07 3.57 3.16 2.85 3500 3200 2250 1660 1550 1310 1070 75.3 57.4 45.3 36.7 30.4 25.6
Match (Gain 100.7 94.1 67.1 50.3 47.0 40.3 33.5 28.8 25.2 22.4 20.1 16.8 12.6 10.1 5.03 4.03 3.36 2.87 2.52 2.24 2.01 4790 4460 3120 2290 2120 1790 1460 1220 1047 89.1 66.8 52.1 41.8 34.3 28.6
AD8309, Thus, match needed, MHz, must 7.12 must
Step Split Into Parts
Since wish provide fully-balanced form network shown Figure capacitors each nominally twice shown figure, used. This requires value 14.24 this example. Under these conditions, voltage amplitudes INHI INLO will similar. somewhat better balance drives achieved when made slightly larger than which also allows wider range choices selecting from standard values. example, capacitors used (making 6.96 pF).
Step Calculate
matching inductor required provide both just parallel combination these: LINLO/(LIN (10) With value complete this example match 262.5 nearest standard value used with only slight loss matching accuracy. voltage gain resonance depends only ratio impedances, given
GAIN
(11)
-15-
AD8309
Slope Intercept Adjustment
COM2 VPS1 PADL INHI INLO PADL COM1 ENBL VPS2 PADL LMHI LMLO PADL FLTR LMDR RLIM 9.6k INTERCEPT VLOG IN914 SIMILAR RSSI
AD8309 provides limited opportunities adjustment basic scaling parameters, which controlled within tight limits through robust design. applications involving observation measured signal levels slope decade convenient: reading then directly decibels, needing only positioning decimal point. This simply achieved same time trimmed this exact value using scheme shown Figure large filter capacitor CFILT added shown when voltage measured DVM; this lowers fluctuation lowerorder display digits. precision attenuator signal generator required provide several test levels intervals. adjustment also made using modulated signal, about center dynamic range. modulation depth expressed fraction, decibel range between peaks troughs over cycle modulation period given log10 (1+M)/(1-M) (12) example, using signal level with modulation depth 0.7), decibel range signal varies from -47.5 -32.5 dBm. output would thus adjusted have peak-to-peak amplitude
COM2 VPS1 PADL INPUT COUPLING INHI INLO PADL COM1 ENBL VLOG VPS2 8.87k PADL LMHI LMLO PADL FLTR LMDR LIMITER DISABLED RSSI ONLY MODE CFILT
AD8309
Figure Trimming Intercept -113
APPLICATIONS
AD8309 versatile easily applied log-limiting amp. Being complete, used with very external components, most applications accommodated using simple connections shown preceding section. examples more specialized applications provided here.
with High Slope Voltage
AD8309
SLOPE
RSSI OUTPUT 10mV/dB
Where higher RSSI slope voltage required, and/or complete calibration with good temperature stability minimal interaction between trims, interface shown Figure used. Note that mV/dB, full dynamic range AD8309 requires swing. This provided single supply operational amplifier having rail-to-rail output stage operating from supply. Where lower range sufficient, when using mV/dB option, supply will adequate. this application, supply current into VPS2 only slightly dependent current delivered load resistance, voltage dropping resistor, added lower supply AD8309, which meet specifications with supply. lower chip dissipation resulting reduction operating temperature will minimize degradation noise figure high ambient temperatures. calculated follows:
8.87k
Figure Trimming Slope mV/dB
intercept adjusted auxiliary circuit shown Figure without changing slope, which remains mV/dB. This circuit provides range about nominal intercept -113 (-100 dBm), with fairly residual temperature sensitivity (+0.008 dB/°C). This sufficient absorb worst-case intercept error AD8309 plus system-level gain errors. adjusted while applying accurately known signal near lower dynamic range, order minimize effect residual uncertainty slope. example, position intercept exactly -100 dBm, test level applied adjusted produce output above intercept, which +0.8 This trim optionally combined with slope trim described above.
(13)
RLIM
which allows operation ambient temperatures +85°C. Table used select component values various different operating conditions. slope adjustment range intercept adjustment range Since intercept offset bias derived from supply, there sensitivity this voltage. Where supply stability poor, regulator needed bias
-16-
REV.
AD8309
AD8309 SUPPLY DROPPED COM2 VPS1 PADL INHI INPUT INLO PADL COM1 ENBL LMLO PADL FLTR LMDR VLOG VPS2 PADL LMHI SLOPE 33.2k -3V)/25mA
AD8309
AD8031 1.96k RSSI
Figure Buffered RSSI Output with Slope Intercept Adjustments
Table
High Output Limiter Loading
Slope Intercept mV/dB -102 -103 3.92 1.05 3.92 1.05
8.87 9.53 8.87 9.53
20.5 15.4
1.05 1.07
VOUT 0.56 0.75 0.08 4.56 5.75 4.08 5.10
Setting Limiter Output Level
limiter output pair differential currents magnitude, IOUT, from high impedance (open-collector) sources. These converted equal-amplitude voltages supplyreferenced load resistors, RLOAD. limiter output current RLIM, resistor connected between (LMDR) ground depending application, resulting voltage used fully balanced unbalanced manner. good practice retain both resistors, whichever output mode used. unbalanced, single sided mode, more inclined result instabilities caused very high gain signal path. limiter output needed, LMDR should left open with LMHI LMLO being tied VPS2. limiter output current equation: IOUT -400 mV/RLIM absolute accuracy voltage each limiter pins will given VLIM RLOAD /RLIM limiter current high which requires RLIM ohms, optionally increased somewhat beyond this level. inadvisable, however, high bias currents, since gain this wide bandwidth signal path proportional risk instability elevated RLIM reduced (recommended value limiter output specified input levels between dBV. output limiter will unstable levels below (-65 dBm).
AD8309 generate fairly large output power differential limiter output interface. This coupled into grounded load using narrow-band coupling network following similar lines those provided input matching. Alternatively, flux-linked transformer, having center-tapped primary, used. Even higher output powers obtained using emitter-followers. Figure supply voltage AD8309 dropped from about diode. This increases available swing each output about Taking both outputs differentially, square wave output generated.
IN914 APPROX. 4.2V COM2 VPS1 PADL INHI INLO PADL COM1 ENBL VPS2 PADL LMHI LMLO PADL FLTR LMDR RLIM DIFFERENTIAL OUTPUT pk-pk VLOG RLOAD RSSI 5*RLIM RLOAD
AD8309
Figure Increasing Limiter Output Voltage
When operating high output power levels high frequencies, very careful attention must paid issue stability. Oscillation likely observed when input signal level low, extremely high gain-bandwidth product AD8309 under such conditions. These oscillations will less evident when signal-balancing networks used, operating frequencies below MHz, they will generally fully quenched signal input levels above noise floor.
REV.
-17-
AD8309
Modulated Limiter Output
limiter output stage AD8309 also provides analog multiplication capability: amplitude output square wave controlled current withdrawn from LMDR (Pin analog control input used generate exactly-proportional current transistor, whose collector held fixed voltage internal bias AD8309. When input signal above limiting threshold, output will then squarewave whose amplitude proportional control bias.
COM2 VPS1 PADL INHI INLO PADL COM1 ENBL VPS2 PADL LMHI LMLO PADL FLTR LMDR 10mA VARIABLE OUTPUT 2N3904 8.2k VLOG RSSI
case AD8309 being alternately unmodulated sine wave single CDMA channel same power. AD8309's output voltage will differ equivalent 3.55 over complete dynamic range device (the output CDMA input being lower). Table shows correction factors that should applied measure signal strength various signal types. sine wave input used reference. measure power square wave, example, equivalent value given table mV/dB times 3.01 should subtracted from output voltage AD8309.
Table III. Shift AD8309 Output Signals with Differing Crest Factors
AD8309
Signal Type Sine Wave Square Wave Triangular Wave Channel (All Time Slots CDMA Channel Channel (All Time Slots Gaussian Noise
Evaluation Board
Correction Factor (Add Output Reading) -3.01 +0.9 +0.55 +3.55 +0.58 +2.51
AD8031 1.8k
Figure Variable Limiter Output Programming
Effect Waveform Type Intercept
AD8309 fundamentally responds voltage power. direct consequence this characteristic that input signals equal power, differing crest factors, will produce different results amp's output. effect differing signal waveforms shift effective value amp's intercept. Graphically, this looks like vertical shift amp's transfer function. device's logarithmic slope however affected. example, consider
evaluation board, carefully laid tested demonstrate specified high speed performance AD8309 available. Figure shows schematic evaluation board which fairly closely follows basic connections schematic shown Figure ordering information, please refer Ordering Guide. Links, switches component settings different setups described Table
COM2 VPS1 PADL INHI INLO PADL COM1 ENABLE ENBL VLOG VPS2 PADL LMHI (OPEN) LMLO PADL FLTR LMDR (OPEN) (OPEN)
VRSSI
INHI
0.01 LMHI
0.01
AD8309
52.3
INLO
0.01
LMLO 0.01
Figure Evaluation Board Schematic
-18-
REV.
AD8309
Table Evaluation Board Setup Options
Component
Function Device Enable. When position ENBL connected AD8309 normal operating mode. position ENBL connected connector labeled Enable. applied signal applied this connector enable/disable AD8309. left open, ENBL will float ground putting device power-down mode. This used ac-couple ground single-ended input drive. drive AD8309 differentially, should removed. Input Interface. 52.3 resistor position along with create high pass input filter whose corner frequency (640 kHz) equal 1/(RC), where parallel combination 52.3 AD8309's input impedance 1000 Alternatively, 52.3 resistor replaced inductor form input matching network. Input Matching Network section more details. Slope Adjust. simple slope adjustment implemented adding resistive divider VLOG output. whose should about never less than (see specs), slope according equation: Slope mV/dB R4/(R3+R4). Limiter Output Coupling. ac-couple limiter's differential outputs. adjusting these values installing inductor output matching network implemented. Limiter Output Current. With installed, enables sets limiter output current. limiter's output current according equation (IOUT mV/R8). limiter current high disable limiter (recommended limiter being used), should removed. RSSI Bandwidth Adjust. addition will lower RSSI bandwidth VLOG output according equation: fCORNER 12.7 10-6/(CFILT pF).
Default Condition
R/L,
R/L= 52.3 0.01
R3/R4
Open 0.01 0.01 Installed.
Open
Figure Layout Signal Layer
Figure Layout Power Layer
REV.
-19-
AD8309
Figure Signal Layer Silkscreen
Figure Power Layer Silkscreen
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Lead TSSOP (RU-16)
0.201 (5.10) 0.193 (4.90)
0.177 (4.50) 0.169 (4.30)
0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) 0.0118 (0.30) 0.0075 (0.19)
0.256 (6.50) 0.246 (6.25)
0.0256 SEATING (0.65) PLANE
0.0079 (0.20) 0.0035 (0.090)
0.028 (0.70) 0.020 (0.50)
-20-
REV.
PRINTED U.S.A.
C3440b-0-8/99
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