74HC/HCT4520 Dual 4-bit synchronous binary counter Product specif

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74HC/HCT4520 Dual 4-bit synchronous binary counter Product specif

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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4520 Dual 4-bit synchronous binary counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4520 high-speed Si-gate CMOS devices compatible with "4520" "4000B" series. They specified compliance with JEDEC standard 74HC/HCT4520 dual 4-bit internally synchronous binary counters with active HIGH clock input (nCP0) active clock input (nCP1), buffered outputs
74HC/HCT4520
from four positions (nQ0 nQ3) active HIGH overriding asynchronous master reset input (nMR). counter advances either LOW-to-HIGH transition nCP0 nCP1 HIGH HIGH-to-LOW transition nCP1 nCP0 LOW. Either nCP0 nCP1 used clock input counter other clock input used clock enable input. HIGH resets counter (nQ0 LOW) independent nCP0 nCP1. APPLICATIONS Multistage synchronous counting Multistage asynchronous counting Frequency dividers
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/ tPLH tPHL fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nCP0, nCP1 propagation delay maximum clock frequency input capacitance power dissipation capacitance counter notes CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
DESCRIPTION SYMBOL 1CP0, 2CP0 1CP1, 2CP1 1MR, NAME FUNCTION clock inputs (LOW-to-HIGH, edge-triggered) clock inputs (HIGH-to-LOW, edge-triggered) data outputs asynchronous master reset inputs (active HIGH) ground data outputs positive supply voltage
74HC/HCT4520
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
FUNCTION TABLE nCP0 Notes nCP1
74HC/HCT4520
MODE counter advances counter advances change change change change
Fig.4 Functional diagram.
HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition
Fig.5 Logic diagram (one counter).
Fig.6 Timing diagram.
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nCP0 propagation delay nCP1 propagation delay output transition time typ. max. min. max. +125 min. max.
74HC/HCT4520
TEST CONDITIONS UNIT
WAVEFORMS
Fig.8
tPHL/ tPLH
Fig.8
tPHL
Fig.9
tTHL/ tTLH
Fig.8
clock pulse width HIGH
Fig.7
master reset pulse width HIGH removal time nCP0; nCP1 set-up time nCP1 nCP0; nCP0 nCP1 maximum clock pulse frequency
Fig.7
trem
Fig.7
Fig.8
fmax
Fig.7
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT4520
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below.
INPUT nCP0, nCP1
UNIT LOAD COEFFICIENT 0.80 1.50
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER min. typ. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH trem propagation delay nCP0 propagation delay nCP1 propagation delay output transition time clock pulse width HIGH master reset pulse width HIGH removal time nCP0; nCP1 set-up time nCP1 nCP0; nCP0 nCP1 maximum clock pulse frequency max. min. max. +125 min. max. Fig.8 Fig.8 Fig.9 Fig.8 Fig.7 Fig.7 Fig.7 Fig.8 UNIT WAVEFORMS TEST CONDITIONS
fmax
Fig.7
December 1990
Philips Semiconductors
Product specification
Dual 4-bit synchronous binary counter
WAVEFORMS
74HC/HCT4520
Conditions: nCP1 HIGH while nCP0 triggered LOW-to-HIGH transition; trem also apply when nCP0 nCP1 triggered HIGH-to-LOW transition. 50%; VCC. HCT:
Fig.7
Waveforms showing removal time nMR; minimum nCP0, nCP1, pulse widths maximum clock pulse frequency.
50%; VCC. HCT:
Fig.8
Waveforms showing set-up times nCP0 nCP1 nCP1 nCP0, propagation delays output transition times.
50%; VCC. HCT:
Fig.9 Waveforms showing propagation delay from output.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990

74HC/HCT4520 Dual 4-bit synchronous binary counter Product specif

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