3164800AJ/AT(L) -40/-50/-60 3165800AJ/AT(L) -40/-50/-60 words 8-b
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8-Bit Dynamic Refresh)
3164800AJ/AT(L) -40/-50/-60 3165800AJ/AT(L) -40/-50/-60
words 8-bit organization operating temperature Fast Page Mode operation Performance: tRAC tCAC access time access time Access time from address Read/write cycle time Fast page mode cycle time
Single 0.3V) power supply power dissipation: max. active 3164800AJ/AT(L) -40) max. active 3164800AJ/AT(L) -50) max. active 3164800AJ/AT(L) -60) max. active 3165800AJ/AT(L) -40) max. active 3165800AJ/AT(L) -50) max. active 3165800AJ/AT(L) -60) standby (LVTTL) 3.24 standby (LVCMOS) standby L-versions Read, write, read-modify-write, CAS-before-RAS refresh (CBR), RAS-only refresh, hidden refresh self refresh (L-version only)
8192 refresh cycles/128 addresses (HYB 3164800AJ/AT) 4096 refresh cycles/ addresses (HYB 3165800AJ/AT) msec refresh period L-versions
Plastic Package:
P-SOJ-32-1 P-TSOPII-32-1
3164(5)800AJ 3164(5)800AT(L)
Semiconductor Group
6.97
8-DRAM
This device MBit dynamic organized bits. device fabricated advanced second generation 64Mbit 0,35 CMOS silicon gate process technology. circuit process design allow this device achieve high performance power dissipation. This DRAM operates with single +/-0.3V power supply interfaces with either LVTTL LVCMOS levels. Multiplexed address inputs permit 3164(5)800AJ/AT packaged 400mil wide SOJ-32 TSOP-32 plastic package. These packages provide high system densities compatible with commonly used automatic testing insertion equipment. HYB3164(5)800ATL parts (L-versions) have very power ,,sleep mode" supported Self Refresh Ordering Information Type
3164800AJ-40 3164800AJ-50 3164800AJ-60 3164800AT-40 3164800AT-50 3164800AT-60 3165800AJ-40 3165800AJ-50 3165800AJ-60 3165800AT-40 3165800AT-50 3165800AT-60 3164(5)800ATL
Ordering Code
Package
P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-SOJ-32-1 P-SOJ-32-1 P-SOJ-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1 P-TSOPII-32-1
Descriptions
DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time DRAM (access time Power DRAMs
Names A0-A12 A0-A11 I/O1-I/O8 Address Inputs 8k-refresh versions 3164800AJ/AT(L) Address Inputs 4k-refresh versions 3165800AJ/AT(L) Address Strobe Output Enable Data Input/Output Column Address Strobe Read/Write Input Power Supply 3.3V) Ground
Semiconductor Group
8-DRAM
P-SOJ-32-1 (400 mil) P-TSOPII-32-1 (400 mil)
I/O1 I/O2 I/O3 I/O4 N.C. WRITE
I/O8 I/O7 I/O6 I/O5 N.C.
3164800AJ/AT(L) N.C. 3165800AJ/AT(L) Configuration
Semiconductor Group
8-DRAM
TRUTH TABLE
FUNCTION Standby Read Early-Write Delayed-Write Read-Modify-Write Fast Page Mode Read Cycle Cycle Fast Page Mode Early Write Cycle Cycle Fast Page Mode Cycle Cycle only refresh CAS-before-RAS refresh Test Mode Entry Hidden Refresh READ WRITE
L-H-L L-H-L
ADDR
ADDR
I/O1I/O8 High Impedance Data Data Data Data Out, Data Data Data Data Data Data Out, Data Data Out, Data High Impedance High Impedance High Impedance Data Data
Semiconductor Group
8-DRAM
I/O1 I/O2
I/O8
Data Buffer
Clock Generator
Data Buffer
Column Address Buffer(11)
Column Decoder
Refresh Controller
Sense Amplifier Gating
Refresh Counter (12)
2048
Address Buffers(12)
Decoder 4096
Memory Array 4096 2048
Clock
Generator
Block Diagram 3165800AJ/AT(L)
Semiconductor Group
8-DRAM
I/O1 I/O2
I/O8
Data Buffer
Clock Generator
Data Buffer
Column Address Buffer(10)
Column Decoder
Refresh Controller
Sense Amplifier Gating
Refresh Counter (13)
1024
Address Buffers(13)
Decoder 8192
Memory Array 8192 1024
Clock
Generator
Block Diagram 3164800AJ/AT(L)
Semiconductor Group
8-DRAM
Absolute Maximum Ratings Operating temperature range.0 Storage temperature range.- Input/output voltage.-0.5 (Vcc+0.5,4.6) Power supply voltage.-0.5V Power dissipation.1.0 Data current (short circuit).50 Note
Stresses above those listed under ,,Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rating conditions extended periods effect device reliability.
Characteristics Parameter Input high voltage Input voltage Output high voltage (LVTTL) Output ,,H" level voltage (Iout -2mA) Output voltage (LVTTL) Output ,,L"level voltage (Iout +2mA) Output high voltage (LVCMOS) Output ,,H" level voltage (Iout -100uA) Ouput voltage (LVCMOS) Output ,,L" level voltage (Iout +100uA) Input leakage current,any input
other pins
Symbol
Limit Values min. max. Vcc+0.3
Unit Note
II(L) IO(L)
Vcc-0.2
Output leakage current
disabled, Vout
Semiconductor Group
8-DRAM
DC-Characteristics (cont'd)
Parameter Operating Current Symbol refresh version Unit Note
ICC1
version version version
(RAS, CAS, address cycling: min.)
Standby Current
(RAS=CAS= Vih)
ICC2 ICC3
version -50ns version version
Only Refresh Current:
(RAS cycling: VIH: min.)
Fast Page Mode Current: version version version
(RAS VIL, CAS, address cycling: tPC=tPC min.)
ICC4
Standby Current
(RAS=CAS= Vcc-0.2V)
ICC5 ICC5 ICC6
version version version
Standby Current (L-Version)
(RAS=CAS= Vcc-0.2V)
Before Refresh Current
(RAS, cycling: min.)
Self Refresh Current (L-version only)
(CBR cycle with tRAS>TRASSmin, held low, Vcc-0.2V, Address Din=Vcc-0.2V 0.2V)
ICC7
Semiconductor Group
8-DRAM
Characteristics (note: 6,7,8) °C,VCC 0.3V Parameter
Symbol
AC64-2F
min.
max.
Unit Note
max. min.
max. min.
Common Parameters
Random read write cycle time pulse width pulse width precharge time precharge time address setup time address hold time Column address setup time Column address hold time delay time column address delay hold time hold time precharge time Transition time (rise fall) Refresh period 8k-refresh Refresh period 4k-refresh Refresh period L-versions tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH 100k 100k 100k 100k 100k 100k
tCRP
tREF tREF tREF
Read Cycle
Access time from Access time from Access time from column address access time Read command setup time Read command hold time Read command hold time referenced output low-Z tRAC tCAC tOEA tRCS tRCH tRRH tCLZ
Column address lead time tRAL
Semiconductor Group
8-DRAM
Characteristics (cont'd)(note: 6,7,8) °C,VCC 0.3V Parameter Output buffer turn-off delay Output buffer turn-off delay from Data delay high data delay high data delay
Symbol
AC64-2F
min.
max.
Unit Note
max. min.
max. min.
tOFF tOEZ tDZO tCDD tODD
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWCS
Write command lead time Write command lead time Data setup time Data hold time delay time from tDZC
Read-Modify-Write Cycle
Read-write cycle time delay time delay time command hold time tOEH
Column address delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time Access time from precharge pulse width precharge Delay tCPA tRAS tRHPC
200k
200k
200k
Semiconductor Group
8-DRAM
Characteristics (cont'd)(note: 6,7,8) °C,VCC 0.3V Parameter
Symbol
AC64-2F
min.
max.
Unit Note
max. min.
max. min.
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time precharge tCPWD
CAS-before-RAS Refresh Cycle
setup time hold time precharge time Write precharge time tCSR tCHR tRPC tWRP
Write hold time referenced tWRH
Self Refresh Cycle (L-version only)
pulse width precharge time hold time
tRASS
100k
100k
100k
tRPS tCHS
Test Mode Cycle
Write command setup time Write command hold time
tWTS tWTH
Capacitance °C,VCC Parameter Input capacitance A11,A12) Input capacitance (RAS, CAS, capacitance (I/O1-I/O8) Symbol Limit Values min. max. Unit
Semiconductor Group
8-DRAM
Notes:
voltages referenced VSS. overshoot pulse widths with 3.3V. undershoot -2.0V pulse width with 3.3V. Pulse width measured points with amplitude measured peak reference. ICC1, ICC3, ICC4 ICC6 ICC7 depend cycle rate. ICC1 ICC4 depend output loading. Specified values measured with output open. Address changed once less while Vil.In case ICC4 changed once less during fast page mode cycle tpc). initial pause required after power-up followed RAS-only-refresh cycles, before proper device operation achieved. case using internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. measurements assume (min.) (max.) reference levels measuring timing input signals. Also, transition times measured between VIL. Measured with specified current load Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only: tRCD greater than specified tRCD (max.) limit, then access time controlled tCAC. Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only: tRAD greater than specified tRAD (max.) limit, then access time controlled tAA. Either tRCH tRRH must satisfied read cycle. tOFF (max.) tOEZ (max.) define time which outputs achieve open-circuit condition referenced output voltage levels. Either tDZC tDZO must satisfied. Either tCDD tODD must satisfied. tWCS, tRWD, tCWD, tAWD tCPWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min.), cycle early write cycle will remain open-circuit (high impedance) through entire cycle; tRWD tRWD (min.), tCWD tCWD (min.), tAWD tAWD (min.) tCPWD tCPWD (min.) cycle read-write cycle pins will contain data read from selected cells. neither above sets conditions satisfied, condition pins access time) indeterminate. These parameters referenced leading edge early write cycles WRITE leading edge Read-Modify-Write cycles. When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refresh evenly distributed manner over refresh iterval using refresh cycles, then only cycle must performed immediatly after exit from Self Refresh. addresses being refresh other manner (ROR Distributed/Burst CBR-Burst) over refresh interval, then full refreshed must performed immediately before entry immediatey after exit from Self Refresh. Test Mode Read Cycle, value trac, taa, tcac tcpa delayed from specified value. These parameters must adjusted Test Mode cycles adding specified value. Associated timings must adjusted
Semiconductor Group
8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tRCH tRAH tRCS tRRH tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC tDZO tODD tCAC tCLZ
tCDD
(Inputs)
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA
tOFF tOEZ
AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAA
(Outputs)
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Valid Data
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Read Cycle
Semiconductor Group
8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL tCAH
Column
tCRP
tRAD tASR tASC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
Address
tRAH
tWCS
tCWL
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
tWCH tRWL
(Inputs)
Valid Data
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
Write Cycle (Early Write)
Semiconductor Group
8-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
tRAD tASR tASC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tCAH
Column
tASR
AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAA tCWL
Address AAAAAAAAA AAAAAAAAA AAAAAAAAA
AAAAAAAAA IHAAAAAAAAA AAAAAAAAA AAAAAAAAA
tRAH
tRWL
tOEH
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
tODD tOEZ tCLZ tOEA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
(Inputs)
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAA
Valid Data
(Outputs)
Hi-Z
Hi-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Write Cycle Controlled Write)
Semiconductor Group
8-DRAM
tRWC tRAS
tCSH tRCD tRSH tCAS tCRP
tRAH tASR
tCAH tASC
tASR
Address
AAAA AAAA AAAA AAAA AAAA AAAA AAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column
tRAD
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tAWD tCWD tRWD
tCWL tRWL
AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAA
tRCS
tOEA
tOEH
AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAA
tDZO tDZC
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
(Inputs)
AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAA
Valid Data
tCLZ tCAC
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tODD tOEZ
AAAAAA AAAAAA Data AAAAAA AAAAAA AAAAAA AAAAAA
(Outputs)
tRAC
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
8-DRAM
tRASP
tRCD
tCAS
tCAS
tRHPC tRSH tCAS
tCRP
tCSH tRAH tASR tASC tCAH
Column
tASC
tCAH
tCAH tASC AAAAAAAAA AAAAAAAAA AAAAAAAAA Column AAAAAAAAA AAAAAAAAA AAAAAAAAA tRCS
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAA tRRH AAAAAAA
tASR
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA tRCH
Address
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tRAD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tRCH tRCS
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRCS
tCPA tOEA
tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tDZC tDZO tODD
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA tOFF
tDZC
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tCPA tOEA tDZC
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCDD tODD
AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAAA
tDZO tODD
tDZO
(Inputs)
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAA
tCAC tCLZ
tCAC tCLZ
tRAC
(Outputs)
tOFF tOEZ
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tCAC tCLZ
tOFF tOEZ
tOEZ
AAAAA AAAAA AAAAA Valid AAAAA AAAAA Data AAAAA AAAAA
AAAAAA AAAAAA AAAAAA Valid AAAAAA AAAAAA Data AAAAAA AAAAAA
AAAAAA AAAAAA Valid AAAAAA AAAAAA Data AAAAAA AAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
FPM1
Fast Page Mode Read Cycle
Semiconductor Group
8-DRAM
tRAS
tRCD
tRSH tCAS tCAS tCRP
tCAS
tRAH tASR
AAAAA AAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
tRAL tCAH tASC tASC tCAH tASC tCAH tASR
Address
AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAAA Column AAAAAAAAA Column AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA AAAAAAAAAA AAAAAAAAAA AAAAAAAAA
tRAD tWCS
tCWL tWCH
tWCS
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
tCWL
tWCS
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tCWL tRWL
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tWCH tWCH AAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
(Inputs)
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA AAAAAAAAAAA
Valid Data
Valid Data
Valid Data
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
HI-Z
FPM2
Fast Page Mode Early Write Cycle
Semiconductor Group
8-DRAM
tCPWD tCWD
tAWD
tOEA
tCPWD tCWD
tOEA
tCAH
tRWD tCWD
tAWD
tOEA
tCAH
tDZC tCLZ tDZO
tCSH
Column
tASC
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Data
tOEH
tOEZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
Column Address
tCLZ
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
Data
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCAH
tCPA
Column
tCLZ
tCAC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEH
Data
tOEZ
AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRAL
tRWL tCWL
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCRP
tASR
tODD
tCAS
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tASC
tCWL
tDZC
tPRWC
tRAS
tODD
tCAS
tOEZ
tAWD
tASC
tCPA tDZC
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tCWL
AAAAAA AAAAAA AAAAAA AAAAAA
tODD
tCAS
(Inputs)
Fast Page Mode Read-Modify-Write Cycle
Semiconductor Group
(Outputs)
Address
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
tASR
tRAD
tRAH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tRCD
tRCS
tRAC
Data
AAAAA AAAAA AAAAA
Data
AAAAA AAAAA AAAAA
Data
AAAAA AAAAA AAAAA
tRSH
8-DRAM
tRAS
tCRP tRPC
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tRAH tASR
tASR
Address
AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA AAAAAAAAAAAA
(Outputs)
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
HI-Z
RAS-Only Refresh Cycle
Semiconductor Group
8-DRAM
tRAS
tRPC
tCSR tCHR tRPC
tCRP
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tWRP tWRH
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tOEZ
tCDD
(Inputs)
tODD
(Outputs)VOL
HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL10
CAS-Before-RAS Refresh Cycle
Semiconductor Group
8-DRAM
tRAS
tRAS
tRCD
tRSH tCHR tCRP
tRAD tASC tASR tRAH
AAAAA AAAAA AAAAA
tWRP tCAH tWRH tASR
Address
AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAA Column AAAAA AAAAA
tRCS
AAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAA
tRRH
AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA AAAAAA
tOEA
AAAAAAAAAAAAAAAAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAA
tDZC
tCDD
tDZO
tODD tCAC tCLZ
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
(Inputs)
AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAA
tOFF tOEZ
Valid Data
tRAC
(Outputs)
AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAA AAAAA AAAAA AAAAA AAAAA
HI-Z
WL11
Hidden Refresh Cycle (Read)
Semiconductor Group
8-DRAM
tRAS
tRAS
tRCD
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH tASR
Address
AAAAAAA IHAAAAAAA AAAAAAA
AAAAAAA AAAAAAA AAAAAAA
AAAAA AAAAA AAAAA Column AAAAA AAAAA AAAAA tWCS tWRP tWRH tWCH
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
(Input)
AAAAAAAAAAAAAAA IHAAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA AAAAAAAAAAAAAAA
Valid Data
(Output)
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL12
Hidden Refresh Cycle (Early Write)
Semiconductor Group
8-DRAM
tRAS
tRPC tCSR tCHR tRPC tCRP
AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA AAAAAAAAAAAAA
tASR tRAH
AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAA Address IHAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAA AAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAA
tWTS
tWTH
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAA
(Inputs)
tODD
HI-Z
tCDD tOEZ
(Outputs)
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA OHAAAAAAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
HI-Z
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
tOFF
WL15
Test Mode Entry Cycle
Semiconductor Group
8-DRAM
tRASS
tRPS
tRPC tCSR
tCHS
tCRP
AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA AAAAAAAAA
tWRP tWRH
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAA
tCDD
(Inputs)
tODD
tOEZ
(Outputs) HI-Z
tOFF
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
WL13
Self Refresh (,,Sleep Mode") L-version only
Semiconductor Group
8-DRAM
Package Outlines
Plastic Package P-SOJ-32-1 (400 mil) (Small Outline J-lead, SMD)
Plastic Package P-TSOPII-32-1 (400 mil) (Small Outline J-lead, SMD)
Semiconductor Group
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