74HC/HCT4040 12-stage binary ripple counter Product specification
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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4040 12-stage binary ripple counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4040 high-speed Si-gate CMOS devices compatible with "4040" "4000B" series. They specified compliance with JEDEC standard 74HC/HCT4040 12-stage binary ripple counters with clock input (CP), overriding asynchronous master reset input (MR) twelve parallel outputs QUICK REFERENCE DATA Tamb
74HC/HCT4040
Q11). counter advances HIGH-to-LOW transition HIGH clears counter stages forces outputs LOW, independent state Each counter stage static toggle flip-flop. APPLICATIONS Frequency dividing circuits Time delay circuits Control counters
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Qn+1 fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency input capacitance power dissipation capacitance package notes CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
DESCRIPTION SYMBOL NAME FUNCTION ground parallel outputs
74HC/HCT4040
clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) positive supply voltage
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
74HC/HCT4040
FUNCTION TABLE INPUTS Notes OUTPUTS change count
Fig.4 Functional diagram.
HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay Qn+1 propagation delay output transition time typ. max. min. max. +125 min. max.
74HC/HCT4040
TEST CONDITIONS UNIT WAVEFORMS Fig.7
tPHL/ tPLH
Fig.7
tPHL
Fig.7
tTHL/ tTLH
Fig.7
clock pulse width HIGH master reset pulse width; HIGH removal time maximum clock pulse frequency
Fig.7
Fig.7
trem
Fig.7
fmax
Fig.7
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT4040
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below. INPUT UNIT LOAD COEFFICIENT 0.85 1.10
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH trem fmax propagation delay propagation delay Qn+1 propagation delay output transition time clock pulse width HIGH master reset pulse width; HIGH removal time maximum clock pulse frequency typ. max. min. max. +125 min. max. Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 Fig.7 UNIT WAVEFORMS TEST CONDITIONS
December 1990
Philips Semiconductors
Product specification
12-stage binary ripple counter
WAVEFORMS
74HC/HCT4040
50%; VCC. HCT:
Fig.7
Waveforms showing clock (CP) output (Qn) propagation delays, clock pulse width, output transition times maximum clock pulse frequency. Also showing master reset (MR) pulse width, master reset output (Qn) propagation delays master reset clock (CP) removal time.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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