Tools Information FAQs Application Note HA0077E HT49CVX Remote Control
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HT49RV5/HT49CV5 With Type 8-Bit
Tools Information FAQs Application Note HA0077E HT49CVX Remote Control Receiver SWIP Design Note HA0078E HT49CVX Display SWIP Design Note
Operating voltage: 8-bit prescaler Watchdog Timer Buzzer output On-chip crystal, 32768Hz crystal oscillator HALT function wake-up feature reduce power
fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V
bidirectional lines (PA, external interrupt inputs 16-bit programmable timer/event counters with
consumption
8-level subroutine nesting 4-channel 8-bit resolution converter 2-channel 8-bit output shared with lines voltage reset function manipulation instruction 16-bit table read instruction 0.5ms instruction cycle with 8MHz system clock powerful instructions instructions machine cycles 56-pin SSOP package
(programmable frequency divider) function
8-bit Remote Control Timer (RMT), pin-shared
with
Single channel serial interface driver with segments
(16-segment 4-grid 11-segment 11-grid)
program memory data memory Supports sound generation Real Time Clock (RTC)
General Description
HT49RV5/HT49CV5 8-bit high performance single chip MCUs. Their single cycle instruction 2-stage pipeline architecture make them suitable high speed applications. devices include driver they suitable products which require front panel their operation such DVDs, VCDs, Mini-component audio systems, cassette decks, tuners, players, other home appliances, etc.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Block Diagram
ifte
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Assignment
Note:
Each (VSS) pins must connected power (ground) system.
Description
Name PA0/BZ PA1/BZ PA3/PFD PA4~PA7 Options Wake-up Pull-high Buzzer Description Bidirectional 8-bit input/output port. Each configured wake-up input configuration option. Software instructions determine CMOS output Schmitt trigger input with without pull-high resistor (determined pull-high options: option). Pins PA0, pin-shared with PFD, respectively. Bidirectional 4-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with without pull-high resistor (determined pull-high option: option) input. Once line selected input using software control), function pull-high resistor disabled automatically. Bidirectional 2-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with without pull-high resistor (determined pull-high option: option). with wake-up function (both rising falling edge) Schmitt trigger input with without pull-high resistor (determined pull-high option). Note:The pin-shared with PC7. When PC7/RMT uses input mode function suggesting user input mode safety. that function will influence input function.
PB0/AN0~ PB3/AN3
Pull-high
PC7/RMT
Pull-high
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Name PD0/PWM0 PD1/PWM1 Options Pull-high Description Bidirectional 2-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with without pull-high resistor (determined pull-high option: option). PD0~PD1 pin-shared with PWM0~PWM1 (dependent Mask options). Bidirectional 4-bit input/output port. Software instructions determine CMOS output Schmitt trigger input with without pull-high resistor (determined pull-high option: option). Pins PD4~PD7 pin-shared with INT0, INT1, TMR0 TMR1, respectively (determined software control). Negative power supply, ground Negative power supply High voltage segment output panel. High voltage output panel. These pins selectable segment grid output. High voltage grid output panel. Serial interface serial data input Serial interface serial data output Serial interface serial clock input/output (initial Serial interface chip select pin, output master mode, input slave mode.
PD4/INT0 PD5/INT1 PD6/TMR0 PD7/TMR1 SEG0~SEG10 SEG11/Grid10~ SEG15/Grid6 Grid0~Grid5 OSC4 OSC3 OSC2 OSC1
Pull-high
Real time clock oscillators. OSC3 OSC4 connected 32768Hz crystal oscillator timing purposes system clock source (depending System Clock options). built-in capacitor. Crystal Positive power supply OSC1 OSC2 connected network crystal options) internal system clock. operation, OSC2 output system clock. system clock come from oscillator. system clock comes from RTCOSC, these pins left floating. Schmitt trigger reset input, active
Absolute Maximum Ratings
Supply Voltage .VSS-0.3V VSS+6.0V Input Voltage.VSS-0.3V VDD+0.3V Storage Temperature .-50°C 125°C Operating Temperature.-40°C 85°C
Note: These stress ratings only. Stresses exceeding range specified under Maximum cause substantial damage device. Functional operation this device other conditions beyond those listed specification implied prolonged exposure extreme conditions affect device reliability.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
D.C. Characteristics
Symbol Parameter Test Conditions load VOL=0.1VDD Conditions fSYS=4MHz fSYS=8MHz load, off, off, fSYS=4MHz load, off, off, fSYS=4MHz load, off, load, off, fSYS=4MHz load, system HALT HALT load, system HALT HALT Min. 0.8VDD 0.9VDD Typ. ±0.5 Max. VDD-30 0.2VDD 0.4VDD Ta=25°C Unit
IDD1
Operating Voltage Supply Voltage Operating Current (Crystal OSC)
IDD2
Operating Current OSC) Operating Current (fSYS=32768Hz) Operating Current (Crystal OSC)
IDD3
IDD4
ISTB1
Standby Current (*fS=T1) Standby Current (*fS=32768Hz OSC) Input Voltage Ports, Input High Voltage Ports, Input Voltage (RES)
ISTB2 VIL1 VIH1 VIL2 VIH2
Input High Voltage (RES)
Port Sink Current
IOH1 IOH2 IOH3 VLVR IADC Note:
Port Source Current Grid Source Current Segment Source Current Pull-high Resistance Ports INT0, INT1 Driver Output Pull-low Resistor Voltage Reset Voltage Input Voltage Conversion Error Additional Power Consumption Converter Used Refer clock option
VOH=0.9VDD VOH=VDD-2V VOH=VDD-2V enabled
Rev. 1.20
April 2006
HT49RV5/HT49CV5
A.C. Characteristics
Test Conditions Symbol Parameter fSYS1 System Clock System Clock (32768Hz Crystal OSC) Frequency Timer Frequency (TMR0/TMR1) tRES tSST tINT tADC tADCS Note: External Reset Pulse Width System Start-up Timer Period Interrupt Pulse Width Clock Period Conversion Time Sampling Time tSYS= 1/fSYS 2.2V~5.5V 3.3V~5.5V Power-up wake-up from HALT Conditions 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 32768 32768 1024 4000 8000 4000 8000 tSYS Min. Typ. Max. Unit Ta=25°C
fSYS2 fRTCOSC fTIMER
tWDTOSC Watchdog Oscillator Period
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Functional Description
Execution Flow system clock derived from either crystal oscillator 32768Hz crystal oscillator. internally divided into four non-overlapping clocks. instruction cycle consists four system clock cycles. Instruction fetching execution pipelined such that fetch takes instruction cycle while decoding execution takes next instruction cycle. pipelining scheme ensures that instructions effectively executed cycle. Exceptions this instructions that change contents program counter, such subroutine calls jumps, which case, cycles required complete instruction. Program Counter 12-bit program counter (PC) controls sequence which instructions stored program
executed contents specify maximum 4096 addresses. After accessing program memory word fetch instruction code, contents program counter incremented one. program counter then points memory word containing next instruction code. When executing jump instruction, conditional skip execution, loading register, subroutine call, initial reset, internal interrupt, external interrupt return from subroutine, etc., microcontroller manages program control loading address corresponding each instruction. conditional skip instructions, once condition been met, next instruction, which already been fetched during current instruction execution, discarded dummy cycle replaces while proper instruction obtained. Otherwise proceed with next instruction.
Execution Flow Program Counter Mode Initial Reset External Interrupt External Interrupt Timer/Event Counter Overflow Timer/Event Counter Overflow Serial Interface Interrupt Multi-function Interrupt Skip Loading Jump, Call Branch Return from Subroutine
Program Counter+2
Program Counter Note: *11~*0: Program counter bits #11~#0: Instruction code bits S11~S0: Stack register bits @7~@0: bits
Rev. 1.20
April 2006
HT49RV5/HT49CV5
lower byte program counter (PCL) available program control readable writeable register (06H). Moving data into performs short jump. destination will within locations. When control transfer takes place, additional dummy cycle required. Program Memory EPROM program memory (EPROM) used store program instructions which executed. also contains data, table, interrupt entries, organized into bits format. program counter composed bits, directly access whole program memory without changing banks. Certain locations reserved special usage:
Location 000H Location 008H
This area reserved external interrupt service program. INT1 input activated, interrupt enabled, stack full, program will jump this location begin execution.
Location 00CH
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program will jump this location begin execution.
Location 010H
This area reserved Timer/Event Counter interrupt service program. timer interrupt results from Timer/Event Counter overflow, interrupt enabled stack full, program will jump this location begin execution.
Location 014H
This area reserved chip reset program initialization. After chip reset initiated, program will jump this location begin execution.
Location 004H
This area reserved external interrupt service program. INT0 input activated, interrupt enabled, stack full, program will jump this location begin execution.
itia lti-
This area reserved Serial Interface interrupt service program. bits data have been received transmitted successfully from serial interface, interrupt enabled, stack full, program will jump this location begin execution.
Location 018H
This area reserved multi-function interrupt. real time clock interrupt occurs, rising edge detected from input pin, falling edge detected from input pin, overflow related interrupts enabled, stack full, program will jump this location begin execution.
Table location
Program Memory
location within program memory used look-up table where programmers store fixed data. instructions (the current page, page=256 words) (the last page) transfer contents lower-order byte specified data memory, contents higher-order byte TBLH (Table Higher-order byte register) (08H). Only destination lower-order byte table well-defined, other bits table word transferred lower portion TBLH. TBLH read only register table pointer (TBLP) read/write register (07H), which indicates table location. Before accessing table, location must placed TBLP. table
Table Location Instruction(s) TABRDC TABRDL
Table Location Note: *11~*0: Table location bits @7~@0: Table pointer bits P11~P8: Current program counter bits
Rev. 1.20
April 2006
HT49RV5/HT49CV5
lated instructions require cycles complete operation. These areas function normal program memory depending upon requirements. Stack Register STACK stack register special part memory used save contents Program Counter. stack organized into levels neither part data part program, neither readable writeable. activated level indexed stack pointer (SP) neither readable writeable. start subroutine call interrupt acknowledgment, contents Program Counter pushed onto stack. subroutine interrupt routine, signaled return instruction (RET RETI), contents Program Counter restored previous value from stack. After chip reset, will point stack. stack full non-masked interrupt takes place, interrupt request flag recorded acknowledgment still inhibited. Once decremented RETI), interrupt serviced. This feature prevents stack overflow, allowing programmer structure easily. Likewise, stack full, subsequently executed, stack overflow occurs first entry lost (only most recent return addresses stored). Data Memory data memory (RAM) capacity bits, divided into functional groups, namely; special function registers bit) general purpose data memory (RAM bank contains bits) most which readable/writeable, some read only. special function registers overlapped banks. special function registers consist Indirect addressing register (00H), Memory pointer register (MP0;01H), Indirect addressing register (02H), Memory pointer register (MP1;03H), Bank pointer (BP;04H), Accumulator (ACC;05H), Program counter lower-order byte register (PCL;06H), Table pointer (TBLP;07H), Table higher-order byte register (TBLH;08H), Real time clock control register (RTCC;09H), Status register (STATUS;0AH), Interrupt control register (INTC0;0BH), Timer/Event Counter (TMR0H:0CH; TMR0L:0DH), Timer/Event Counter control register (TMR0C;0EH), Timer/Event Counter (TMR1H:0FH;TMR1L:10H), Timer/Event Counter control register (TMR1C; 11H), Interrupt control register (INTC1;1EH), Serial control register (SBCR;1FH), Serial data register (SBDR; 20H), Remote timer control register (RMTC;21H), Remote control capture register (RMT0;22H), Remote control
Mapping capture register (RMT1;23H), Multi-function interrupt status register (MFIS;29H), data register (PWM0;1AH, PWM1;1BH), result register (ADR;25H), control register (ADCR;26H), clock setting register (ACSR;27H), control register (VFDC; 28H), registers (PA;12H, PB;14H, PC;16H, PD;18H) control registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H).
Rev. 1.20
April 2006
HT49RV5/HT49CV5
remaining space before reserved future expanded usage reading these locations will return result space before overlaps each bank. general-purpose data memory, addressed from (Bank0; BP=0), used data control information under instruction commands. data memory areas handle arithmetic, logic, increment, decrement rotate operations directly. Except some dedicated bits, each data memory reset They also indirectly accessible through memory pointer registers (MP0;01H/MP1;03H). Indirect Addressing Register Location indirect addressing registers that physically implemented. read/write operation [00H] [02H] accesses pointed (01H) MP1(03H), respectively. Reading location indirectly returns result 00H. Writing indirectly leads operation. function data movement between indirect addressing registers supported. memory pointer registers, MP1, both 8-bit registers used access combining corresponding indirect addressing registers. only applied data memory, while applied data memory display memory. Accumulator accumulator (ACC) closely related with operations carried ALU. mapped location capable operating with immediate data. data movement between data memory locations must pass through ACC. Label Arithmetic Logic Unit This circuit performs 8-bit arithmetic logic operations provides following functions:
Arithmetic operations (ADD, ADC, SUB, SBC, DAA) Logic operations (AND, XOR, CPL) Rotation (RL, RLC, RRC) Increment Decrement (INC, DEC) Branch decision (SZ, SNZ, SIZ, etc.)
only saves results data operation also changes status register. Status Register STATUS status register (0AH) bits wide contains carry flag (C), auxiliary carry flag (AC), zero flag (Z), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). also records status information controls operation sequence. Except flags, bits status register altered instructions similar other registers. Data written into status register does alter flags. Operations related status register, however, yield different results from those intended. flags only changed Watchdog Timer overflow, chip power-up, clearing Watchdog Timer executing instruction. flags reflect status latest operations. entering interrupt sequence executing subroutine call, status register will automatically pushed onto stack. contents status important, subroutine likely corrupt status register, programmer should take precautions save properly.
Function operation results carry during addition operation borrow does take place during subtraction operation, otherwise cleared. also affected rotate through carry instruction. operation results carry nibbles addition borrow from high nibble into nibble subtraction, otherwise cleared. result arithmetic logic operation zero, otherwise cleared. operation results carry into highest-order carry highest-order bit, vice versa, otherwise cleared. cleared either system power-up executing instruction. executing instruction. cleared system power-up executing instruction. time-out. Unused bit, read Status (0AH) Register
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Interrupts HT49RV5/HT49CV5 provides external interrupts, internal timer/event counter interrupts, three remote control timer interrupts, internal real time clock interrupt serial interface interrupt. interrupt control register (INTC0;0BH) interrupt control register (INTC1;1EH) both contain interrupt control bits that used enable/disable status interrupt request flags. Once interrupt subroutine serviced, other interrupts blocked clearing bit). This scheme prevent further interrupt nesting. Other interrupt requests take place during this interval, only interrupt request flag will recorded. another interrupt requires servicing while program interrupt service routine, programmer should corresponding INTC0 INTC1 allow interrupt nesting. Once stack full, interrupt request will acknowledged, even related interrupt enabled, until decremented. immediate service desired, stack should prevented from becoming full. these interrupts support wake-up function. interrupt serviced, control transfer occurs pushing contents Program Counter onto stack followed branch subroutine specified location ROM. Only contents Program Counter pushed onto stack. contents register status register (STATUS) altered interrupt service program which corrupts desired control sequence, contents should saved advance. External interrupts triggered edge transition INT0 INT1 (configuration option: high low, high, high high low), related interrupt request flag (EIF0; INTC0, EIF1; INTC0) well. After interrupt enabled, stack full, external interrupt active, subroutine call location occurs. interrupt request flag (EIF0 EIF1) bits cleared disable other maskable interrupts. internal Timer/Event Counter interrupt initialized setting Timer/Event Counter interrupt request flag (T0F; INTC0), which normally caused timer overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (T0F) reset, cleared disable other maskable interrupts. Timer/Event Counter operated same manner related interrupt request flag (bit INTC1) subroutine call location 10H. Serial Interface interrupt initialized setting interrupt request flag (TRF; INTC1), which caused completely receiving transferring bits data from serial interface. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (TRF) reset cleared disable further maskable interrupts. multi-function interrupt initialized setting interrupt request flag (MFF; INTC1), which caused regular real time clock signal, caused rising edge RMT, caused falling edge RMT, caused overflow. After interrupt enabled, stack full, set, subroutine call location occurs. related interrupt request flag (MFF) reset cleared disable further maskable interrupts. During execution interrupt subroutine, other maskable interrupt acknowledgments held until instruction executed related interrupt control both stack full). return from interrupt subroutine, invoked. RETI sets enables interrupt service, does not. Interrupts occurring interval between rising edges consecutive pulses serviced latter pulses corresponding interrupts enabled. case simultaneous requests, following table shows priority that applied. These masked resetting bit. Interrupt Source External interrupt External interrupt Timer/Event Counter overflow Timer/Event Counter overflow Serial Interface interrupt Multi-function interrupt Priority Vector
overflow interrupt flag (RMTVF; MFIS), real time clock interrupt flag (RTF; MFIS), rising edge interrupt flag (RMT0F; MFIS) falling edge interrupt flag (RMT1F; MFIS) indicate that related interrupt occurred. After reading these flags, these flags will cleared automatically, they should cleared user. serial interface interrupt indicated interrupt flag (TRF; INTC1), that caused receiving transferring complete 8-bit data transfer between HT49RV5/ HT49CV5 external device. After interrupt enabled setting ESBI; INTC1), stack full, subroutine call location occurs. should cleared users. Timer/Event Counter interrupt request flag (T0F), external interrupt request flag (EIF1), external interrupt request flag (EIF0), enable Timer/Event Counter0 April 2006
Rev. 1.20
HT49RV5/HT49CV5
Label EEI0 EEI1 ET0I EIF0 EIF1 Function Control master (global) interrupt (1=enabled; 0=disabled) Control external interrupt (1=enabled; 0=disabled) Control external interrupt (1=enabled; 0=disabled) Control Timer/Event Counter interrupt (1=enabled; 0=disabled) External interrupt request flag (1=active; 0=inactive) External interrupt request flag (1=active; 0=inactive) Internal Timer/Event Counter request flag (1=active; 0=inactive) test mode used only. Must written otherwise result unpredictable operation. INTC0 (0BH) Register Label ET1I ESBI EMFI Function Control Timer/Event Counter interrupt (1=enabled; 0=disabled) Control serial interface interrupt (1=enabled; 0=disabled) Control real multi-function interrupt (1=enabled; 0=disabled) Unused bit, read Internal Timer/Event Counter request flag (1=active; 0=inactive) Serial data transferred data received interrupt request flag (1=active; 0=inactive) Multi-function interrupt request flag (1=active; 0=inactive) INTC1 (1EH) Register Label ERMT0 ERMT1 ERMTV RMCS Unused bit, read Controls remote control timer rising edge interrupt (1=enable; 0=disable) Controls remote control timer falling edge interrupt (1=enable; 0=disable) Controls remote control timer overflow interrupt (1=enable; 0=disable) Controls remote control timer (1=enable; 0=disable) 1=enable start counting; disable clear counter Selects remote control timer clock source (1=fSYS; 0=fSYS/4) Selects remote control timer clock 00=fX/25 fX/26 fX/27 fX/28 RMTC (21H) Register Label RMTVF RMT0F RMT1F ERTI Function Remote control timer overflow interrupt flag (1=indicates that overflow occurred; 0=indicates that overflow occurred) Real time clock interrupt flag (1=indicates that interrupt occurred; 0=indicates that interrupt occurred) Remote control timer rising edge interrupt flag (1=indicates that rising edge interrupt occurred; 0=indicates that rising edge interrupt occurred) Remote control timer falling edge interrupt flag (1=indicates that falling edge interrupt occurred; 0=indicates that falling edge interrupt occurred) Controls real time clock interrupt (1=enable; 0=disable) Unused bit, read MFIS (29H) Register Rev. 1.20 April 2006 Function
RMS0 RMS1
HT49RV5/HT49CV5
interrupt (ET0I), enable external interrupt (EEI1), enable external interrupt (EEI0), enable master interrupt (EMI) constitute Interrupt Control register (INTC0) which located RAM. multi-function interrupt request flag (MFF), serial interface interrupt request flag (TRF), Timer/Event Counter interrupt request flag (T1F), enable multi-function interrupt (EMFI), enable serial interface interrupt (ESBI), enable Timer/Event Counter interrupt (ET1I), constitute Interrupt Control register (INTC1) which located RAM. enable Remote control timer rising edge interrupt (ERMT0), enable Remote control timer falling edge interrupt (ERMT1), enable Remote control timer overflow interrupt (ERMTV), enable Remote control timer start counting (RME), select Remote control timer clock source (RMCS), select Remote control timer clock (RMS0, RMS1) constitute Remote Timer control Register (RMTC) which located RAM. EMFI,ERMT0 ERMT1 used control enable/disable status interrupts. These bits prevent requested interrupt from being serviced. Once interrupt request flags (MFF, TRF, T0F, T1F, EIF1, EIF0) set, they remain INTC0~INTC1 respectively until interrupts serviced cleared software instruction. recommended that program should within interrupt subroutine. This because interrupts often occur unpredictable manner require serviced immediately some applications. During that period, only stack left, enabling interrupt well controlled, operation interrupt subroutine damage original control sequence. Oscillator Configuration HT49RV5/HT49CV5 provides three oscillator circuits system clocks, i.e., oscillator, crystal oscillator 32768Hz crystal oscillator, determined options. matter what type oscillator selected, signal used system clock. HALT mode stops system oscillator crystal oscillator only) ignores external signals conserve power. 32768Hz crystal oscillator still runs HALT mode. 32768Hz crystal oscillator selected system oscillator, system oscillator stopped instruction execution stopped. Since 32768Hz oscillator also designed timing purposes, internal timing (RTC, WDT) operation still runs even system enters HALT mode. three oscillators, oscillator used, external resistor between OSC1 required, range resistance should from 56kW 1.5MW. system clock, divided available OSC2 with pull-high resistor, which used synchronize external logic. oscillator provides most cost effective solution. However, frequency oscillation vary with VDD, temperature, chip itself process variations. therefore suitable timing sensitive operations where accurate oscillator frequency desired. other hand, crystal oscillator selected, crystal across OSC1 OSC2 needed provide feedback phase shift oscillator, other external components required. resonator connected between OSC1 OSC2 replace crystal frequency reference, external capacitors OSC1 OSC2 required. There another oscillator circuit designed real time clock. this case, only 32768Hz crystal oscillator applied. crystal should connected between OSC3 OSC4. oscillator circuit controlled start-up quickly setting (bit RTCC). recommended turn quick start-up function during power-on, then turn after seconds. oscillator free running on-chip oscillator external components required. Although system enters power down mode, system clock stops oscillator still works with period approximately 65ms oscillator disabled options conserve power.
illa
illa
System Oscillator
illa
Note:
32768Hz crystal enable condition: clock source system clock source. external resistor capacitor components connected 32768Hz crystal necessary provide oscillation. applications where precise frequencies essential, these components required provide frequency compensation different crystal manufacturing tolerances.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Watchdog Timer clock source implemented dedicated oscillator (WDT oscillator) instruction clock (system clock/4) real time clock oscillator (RTC oscillator). timer designed prevent software malfunction sequence from jumping unknown location with unpredictable results. disabled options. disabled, executions related lead operation. Once internal oscillator oscillator with period 65ms selected, divided 212~215 configuration option time-out period). minimum time-out period 300ms~600ms. This time-out period vary with temperature, process variations. selecting configuration option, longer time-out periods realized. time-out selected, 215, maximum time-out period divided 215~216 which 2.3s~4.7s. oscillator disabled, clock still come from instruction clock operates same manner except that halt state stop counting lose protecting purposes. this situation logic only restarted external logic. device operates noisy environment, using on-chip oscillator (WDT OSC) strongly recommended since HALT will stop system clock. overflow under normal operation initializes sets status HALT mode, overflow initializes only Program Counter reset zero. clear contents WDT, there three methods adopted, i.e., external reset level RES), software instruction, instruction. There types software instructions; other these types instruction, only type instruction active time depending options times selection option. selected (i.e., times equal one), execution instruction clears WDT. case where instructions chosen (i.e., times equal two), these instructions have executed clear WDT, otherwise, reset chip time-out.
Multi-function Timer HT49RV5/HT49CV5 provides multi-function timer with different time-out periods. multi-function timer consists 8-stage divider 7-bit prescaler, with clock source coming from instruction clock (i.e., system clock divided multi-function timer also provides selectable frequency signal (ranging from fS/20 fS/27) driver circuits, selectable frequency signal (ranging from fS/21 fS/28) buzzer output options. recommended select frequency close possible 32kHz driver circuits obtain good display clarity.
Real Time Clock real time clock (RTC) used supply regular internal interrupt. time-out period ranges from fS/28 fS/215 software programming. Writing data RT2, (bits RTCC; 09H) yields various time-out periods. time-out occurs interrupt enabled, related interrupt request flag (RTF; MFIS) multi-function interrupt request flag (MFF; INTC1) set. interrupt (EMFI) enabled, stack full, subroutine call location occurs. Clock Divided Factor 210* 211*
Note: recommended used
Watchdog Timer
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Real Time Clock RTCC register descriptions listed below. Label RT0~RT2 QOSC Read/ Write Reset Function multiplexer control inputs select real clock prescaler output Unused bit, read 32768Hz quick start-up oscillator 0/1: quick/slow start RTCC (09H) Register Power Down Operation HALT HALT mode initialized instruction results following.
system oscillator turns oscillator
interrupt enabled stack full, regular interrupt response takes place. interrupt request flag before entering mode, wake-up function related interrupt will disabled. wake-up event occurs, takes 1024 tSYS (system clock period) resume normal operation. other words, dummy period will inserted after wake-up. wake-up results from interrupt acknowledge signal, actual interrupt subroutine execution will delayed more cycles. However, wake-up results next instruction execution, this will executed immediately after dummy period finished. minimize power consumption, pins should carefully managed before entering HALT mode. Reset There three ways which microcontroller reset occur, through events occurring both internally externally:
reset during normal operation reset during HALT time-out reset during normal operation
keeps running oscillator real time clock selected).
contents on-chip registers
remain unchanged.
cleared starts recounting
clock source from oscillator real time clock oscillator).
ports maintain their original status. flag flag cleared. driver keeps running
lected). system leave HALT mode means external reset, interrupt, external falling edge signal port external rising/falling edge pin, overflow. external reset will initialize chip reset overflow will initialize After examining flags, source reset determined. flag cleared system power-up executing instruction, executing instruction. flag time-out occurs, causes wake-up that only resets Program Counter other flags remain their original status. port wake-up interrupt methods considered continuation normal execution. Each port independently selected wake device options. Awakening from port stimulus, program will resume execution next instruction. system woken interrupt, possibilities occur. related interrupt disabled interrupt enabled stack full, program will resume execution next instruction.
time-out reset during HALT little different from other kinds reset. Most conditions remain unchanged except that program counter stack pointer will cleared flag will Most registers reset once reset conditions met. different types resets described affect reset flags different ways. These flags, flags, located status register controlled various microcontroller operations such HALT function Watchdog Timer.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
reset flags shown table: RESET Conditions reset during power-up reset during normal operation Wake-up HALT time-out during normal operation Wake-up HALT Note:
Reset Circuit Make length wiring, which connected short possible, avoid noise interference.
Note: stands unchanged ensure that system oscillator started stabilized, (System Start-up Timer) provides extra delay 1024 system clock pulses when system awakes from HALT state during power-on. extra delay added during power-on period, wake-up from HALT enable only delay. functional unit chip reset status shown below. Program Counter Interrupt Prescaler, Divider 000H Disabled Cleared Clear. After master reset, begins counting
Reset Timing Chart
Timer/Event Counter Input/Output Ports Stack Pointer Input mode Points stack
Reset Configuration
register states summarized below: Register TMR0H TMR0L TMR0C TMR1H TMR1L TMR1C Program Counter TBLP TBLH STATUS Reset (Power-on) xxxx xxxx xxxx xxxx 00-0 1000 xxxx xxxx xxxx xxxx 0000 1-0000H xxxx xxxx xxxx xxxx -000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx Time-out Reset (Normal Operation) (Normal Operation) uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1-0000H uuuu uuuu uuuu uuuu -000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1-0000H uuuu uuuu uuuu uuuu -000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu Reset (HALT) uuuu uuuu uuuu uuuu 00-0 1000 uuuu uuuu uuuu uuuu 0000 1-0000H uuuu uuuu uuuu uuuu -000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu Time-out (HALT)* uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu u-0000H uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Register INTC0 INTC1 RMTC MFIS RTCC PWM0 PWM1 SBCR SBDR RMT0 RMT1 ADCR ACSR VFDC Note: Reset (Power-on) -000 0000 -000 -000 0000 000-0 0000 -111 1111 1111 1111 1111 1111 1111 -11- -1111 1111 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 0000 -111 stands stands stands Time-out Reset (Normal Operation) (Normal Operation) -000 0000 -000 -000 0000 000-0 0000 -111 1111 1111 1111 1111 1111 1111 -11- -1111 1111 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 0000 -111 -000 0000 -000 -000 0000 000-0 0000 -111 1111 1111 1111 1111 1111 1111 -11- -1111 1111 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 0000 -111 Reset (HALT) -000 0000 -000 -000 0000 000-0 0000 -111 1111 1111 1111 1111 1111 1111 -11- -1111 1111 xxxx xxxx xxxx xxxx 0110 0000 xxxx xxxx 0000 0000 0000 0000 xxxx xxxx 01-0 0-00 0000 -111 Time-out (HALT)* -uuu uuuu -uuu -uuu uuuu uuu-u uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu -uu- -uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u u-uu 0000 -111
Timer/Event Counter timer/event counters (TMR0,TMR1) implemented microcontroller. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source internal clock source. internal clock source comes from fSYS. Timer/Event Counter contains 16-bit programmable count-up counter clock come from external source internal clock source. internal clock source comes from fSYS/4 32768Hz selected option. external clock input allows user count external events, measure time intervals pulse widths, generate accurate time base. There registers related Timer/Event Counter Timer/Event Counter TMR0H (0CH), TMR0L (0DH), TMR0C (0EH) Timer/Event Counter TMR1H (0FH), TMR1L (10H), TMR1C (11H). Writing TMR0L (TMR1L) will only place written data internal lower-order byte buffer (8-bit) writing TMR0H (TMR1H) will transfer specified data
contents lower-order byte buffer TMR0H (TMR1H) TMR0L (TMR1L) registers, respectively. Timer/Event Counter preload register changed each writing TMR0H (TMR1H) operations. Reading TMR0H (TMR1H) will latch contents TMR0H (TMR1H) TMR0L (TMR1L) counters destination lower-order byte buffer, respectively. Reading TMR0L (TMR1L) will read contents lower-order byte buffer. TMR0C (TMR1C) Timer/Event Counter control register, which defines operating mode, counting enable disable active edge. bits define operation mode. event count mode used count external events, which means that clock source from external (TMR0, TMR1) pin. timer mode functions normal timer with clock source coming from internal selected clock source. Finally, pulse width measurement mode used count high level duration external signal (TMR0, TMR1), counting based internal selected clock source. April 2006
Rev. 1.20
HT49RV5/HT49CV5
event count timer mode, timer/event counter starts counting current contents timer/event counter ends FFFFH. Once overflow occurs, counter reloaded from timer/event counter preload register, generates interrupt request flag (T0F; INTC0, T1F; INTC1). pulse width measurement mode with values bits equal after TMR0 (TMR1) received transient from high high will start counting until TMR0 (TMR1) returns original level resets TON. Label Defines prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 T0PSC0~ 010: fINT=fSYS/4 T0PSC2 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 Defines TMR0 active edge timer/event counter: Event Counter Mode (T0M1,T0M0)=(0,1): 1:count falling edge; 0:count rising edge Pulse Width measurement mode (T0M1,T0M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge Enable/disable timer counting (0=disable; 1=enable) Unused bit, read Defines operating mode (T0M1, T0M0) Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR0C (0EH) Register Label Unused bit, read Defines TMR1 active edge timer/event counter: Event Counter Mode (T1M1,T1M0)=(0,1): 1:count falling edge; 0:count rising edge Pulse Width measurement mode (T1M1,T1M0)=(1,1): start counting rising edge, stop falling edge; start counting falling edge, stop rising edge Enable/disable timer counting disable; enable) Defines TMR1 internal clock source (0=fSYS/4; 1=32768Hz) Defines operating mode (T1M1, T1M0) Event count mode (External clock) Timer mode (Internal clock) Pulse Width measurement mode (External clock) Unused TMR1C (11H) Register Function measured result remains timer/event counter even activated transient occurs again. other words, only 1-cycle measurement made until set. cycle measurement will continue long receives further transient pulse. this operation mode, timer/event counter begins counting according logic level transient edges. case counter overflows, counter reloaded from timer/event counter register issues interrupt request, other modes, i.e., event timer modes. Function
T0ON T0M0 T0M1
T1ON
T1M0 T1M1
Rev. 1.20
April 2006
HT49RV5/HT49CV5
enable counting operation, Timer (TON; TMR0C TMR1C) should pulse width measurement mode, automatically cleared after measurement cycle completed. other modes, only reset instructions. overflow Timer/Event Counter wake-up sources also applied (Programmable Frequency Divider) output options. Only (PFD0 PFD1) applied options. matter what operation mode writing ET0I ET1I disables related interrupt service. When function selected, executing instruction will enable output executing instruction will disable output. case timer/event counter condition, writing data timer/event counter preload register also reloads that data timer/event counter. timer/event counter turned data written timer/event counter kept only timer/event counter preload register. timer/event counter still continues operation until overflow occurs.
When timer/event counter (reading TMR0/TMR1) read, clock blocked avoid errors, this results counting error. Blocking clock should taken into account programmer. strongly recommended load desired value into TMR0/TMR1 register first, before turning related timer/event counter, proper operation since initial value TMR0/TMR1 unknown. timer/event counter scheme, programmer should special attention instruction enable then disable timer first time, whenever there need timer/event counter function, avoid unpredictable result. After this procedure, timer/event function operated normally. Bits TMR0C used define pre-scaling stages internal clock sources timer/event counter. definitions shown. overflow signal timer/event counter used generate signal. timer prescaler also used counter.
Timer/Event Counter
Timer/Event Counter
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Remote Control Timer HT49RV5/HT49CV5 provides 8-bit remote control timer that pulse width measurement function. Pulse width measured from difference count value when valid edge (RMT pin) been detected while timer operates running mode. with rising/falling edge wake-up function, 8-bit timer counter will cleared during chip reset. clock starts count after rising/falling edge trigger.
llin
Remote Control Timer
Label ERMT0 ERMT1 ERMTV RMCS Unused bit, read
Function
Controls remote control timer rising edge interrupt (1=enable; 0=disable) Controls remote control timer falling edge interrupt (1=enable; 0=disable) Controls remote control timer overflow interrupt (1=enable; 0=disable) Controls remote control timer (1=enable start count; 0=disable clear counter) Selects remote control timer clock source (1=fSYS; 0=fSYS/4) Selects remote control timer clock 00=fX/25 fX/26 fX/27 fX/28 RMTC (21H) Register
RMS0 RMS1
Label RMTVF RMT0F RMT1F ERTI
Function Remote control timer overflow interrupt flag (1=indicates that overflow occurred; 0=indicates that overflow occurred) Real time clock interrupt flag (1=indicates that interrupt occurred; 0=indicates that interrupt occurred) Remote control timer rising edge interrupt flag (1=indicates that rising edge interrupt occurred; 0=indicates that rising edge interrupt occurred) Remote control timer falling edge interrupt flag (1=indicates that falling edge interrupt occurred; 0=indicates that falling edge interrupt occurred) Controls real time clock interrupt (1=enable; 0=disable) Unused bit, read MFIS (29H) Register
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Serial Interface Serial Interface function four basic signals included. They (serial data input), (serial data output), (serial clock) (slave select pin). registers (SBCR SBDR) unique serial interface provide control, status data storage.
Timing (SIOCLK Configuration Falling Edge)
Timing (SIOCLK Configuration Rising Edge) Label WCOL CSEN SBEN Unused bit, read This shows situation buffer SBDR enable (set SIO) writing SBDR disable (cleared user) reading from SBDR Serial selection signal Shift first control MSB; LSB) Serial selection enable; disable) Master/slave mode selection: master mode, baud rate=fSIO master mode, baud rate=fSIO/4 master mode, baud rate=fSIO/16 slave mode Clock source selection fSYS/4; fRTCOSC) SBCR (1FH) Register
SBCR: Serial control register
Function
(SBEN): serial enable/disable (1/0)
(CKS): clock source selection: fSIO=fSYS/4 fRTCOSC (M1), (M0): master/slave mode baud rate selection
Enable: (SCS dependent CSEN bit) Disable enable: SCK, SDI, SDO, SCS=0 waiting writing data SBDR (TXRX buffer) Master mode: write data SBDR (TXRX buffer) start transmission/reception automatically Master mode: when data been transferred Slave mode: when (and dependent CSEN) received, data TXRX buffer shifted-out data shifted-in
master mode, baud rate=fSIO master mode, baud rate=fSIO/4 master mode, baud rate=fSIO/16 slave mode
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Disable: SCK, SDI, floating, output high
Clock Polarity=Rising Edge Falling Edge (Configuration Option)
Serial interface operation
(MLS): (1/0) shift first control (CSEN): serial selection signal enable/disable (SCS), when CSEN=0, floating (WCOL): this data written SBDR (TXRX buffer) when data transferred writing will ignored data written SBDR (TXRX buffer) when data transferred (TRF): data transferred data received used generate interrupt Note: data receiving still working when enters HALT mode Data written SBDR write data TXRX buffer only Data read from SBDR read from SBDR only Operating Mode description
Master mode operation Step1: Select select Step2: Select CSEN, (the same slave) Step3: SBEN Step4: Writing data SBDR
data stored TXRX buffer output signals step Note: internal operation: data stored TXRX buffer, data shifted into TXRX buffer data transferred, data TXRX buffer latched into SBDR
SBDR: Serial data register
Step5: Check WCOL
WCOL= clear WCOL step WCOL= step
Master transmitter: clock sending data started writing SBDR Master clock sending started writing SBDR Slave transmitter: data started clock received Slave receiver: data started clock received
Step6: Check TRFor waiting serial interrupt Step7: Read data from SBDR Step8: Clear Step9: step
Block Diagram
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Slave mode operation Step1: care select Step2: Select CSEN, (the same master) Step3: SBEN Step4: Writing data SBDR
data stored TXRX buffer waiting master clock signal (and SCS): step Note: internal operation: (SCS) received output data TXRX buffer data shifted into TXRX buffer data transferred, data TXRX buffer latched into SBDR
Some instructions first input data then follow output operations. example, read entire port states into CPU, execute defined operations (bit-operation), then write results back latches accumulator. Each line port capability waking-up device. Each port pull-high option. Once pull-high option selected, port pull-high resistor, otherwise, none. Take note that non-pull-high port operating input mode will cause floating state. pin-shared with signal. option selected, output signal output mode will signal generated timer/event counter overflow signal. input mode always retains original functions. Once option selected, output signal controlled data register only. Writing data register will enable output function writing will force remain functions shown below. Mode (Normal) Note: Logical Input (Normal) Logical Output (PFD) Logical Input (PFD) (Timer
Step5: Check WCOL
WCOL=1, clear WCOL, step WCOL=0, step
Step6: Check TRFor waiting serial interrupt Step7: Read data from SBDR Step8: Clear Step9: step Input/Output Ports There bidirectional input/output lines microcontroller, labeled which mapped data memory [12H], [14H], [16H] [18H], respectively. these ports used input output operations. input operation, these ports non-latching, that inputs must ready rising edge instruction (m=12H, 14H, 18H). output operation, data latched remains unchanged until output latch rewritten. Each line control register (PAC, PBC, PCC, PDC) control input/output configuration. With this control register, CMOS output Schmitt Trigger input with without pull-high resistor structures reconfigured dynamically under software control. function input, corresponding latch control register must write input source also depends control register. control register input will read state. control register contents latches will move instruction. output function, CMOS only configuration. These control registers mapped locations 13H, 15H, 19H. After chip reset, these input/output lines remain high levels floating state (depending pull-high options). Each these input/output latches cleared (m=12H, 14H, 18H) instructions.
frequency timer/event counter overflow frequency divided
descriptions control signal output frequency listed following table. Timer Data Timer Preload Register State Value Note: Frequency
stands unused stands unknown PFD0 PFD1 preload value timer/event counter input clock frequency timer/event counter
pins pin-shared with signal, respectively. BZ/BZ option selected, output signal output mode PA0/PA1 will buzzer signal generated multi-function timer. input mode always remains original function. Once BZ/BZ option selected, buzzer output signal controlled PA0/PA1 data register only.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Input/Output Ports
function PA0/PA1 shown below. Mode Mode Data Data Status Status Note:
recommended that unused bonded lines should output pins software instructions avoid consuming power under input floating state. microcontroller provides channel (6+2)/(7+1) (dependent options) bits output shared with PD0/PD1. channels have their data registers denoted PWM0 (1AH), PWM1 (1BH). frequency source counter comes from fSYS. registers 8-bit registers. waveforms outputs shown. Once PD0/PD1 selected outputs output function PD0/PD1 enabled (PDC.0/PDC.1 writing PD0/PD1 data register will enable output function writing will force PD0/PD1 remain (6+2) bits mode cycle divided into four modulation cycles (modulation cycle 0~modulation cycle Each modulation cycle input clock period. (6+2) function, contents register divided into groups. Group register denoted which value PWM.7~PWM.2. group denoted which value PWM.1~PWM.0.
input; output Data buzzer option, care CMOS output
PB0~PB3 also used converter inputs. function will described later. There function shared with PD0/PD1. function enabled, PWM0/PWM1 signal will appear PD0/PD1 PD0/PD1 operating output mode). Writing PD0~PD1 data register will enable output function writing will force PD0~PD1 remain functions PD0/PD1 shown. Mode (Normal) Logical Input (Normal) Logical Output (PWM) Logical Input (PWM) PWM0 PWM1
Rev. 1.20
April 2006
HT49RV5/HT49CV5
(6+2) bits mode cycle, duty cycle each modulation cycle shown table. Parameter (0~3) i<AC Modulation cycle (i=0~3) Duty Cycle (7+1) bits mode cycle, duty cycle each modulation cycle shown table. Parameter (0~1) i<AC Modulation cycle (i=0~1) Duty Cycle
(7+1) bits mode cycle divided into modulation cycles (modulation cycle0~modulation cycle Each modulation cycle input clock period. (7+1) bits function, contents register divided into groups. Group register denoted which value PWM.7~PWM.1. group denoted which value PWM.0.
modulation frequency, cycle frequency cycle duty output signal summarized following table. Modulation Frequency Cycle Cycle Frequency Duty [PWM]/256
fSYS/64 (6+2) bits mode fSYS/256 fSYS/128 (7+1) bits mode
(6+2) Mode
(7+1) Mode
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Converter channels resolution converter implemented these microcontrollers. reference voltage VDD. converter contains special registers which are; (25H), ADCR (26H) ACSR (27H). contain result register read-only. After conversion completed, should read conversion result data. ADCR converter control register, which defines channel number, analog channel select, start conversion control conversion flag. user wishes start conversion, they should define configuration, select converted analog channel, give START rising edge falling edge (0®1®0). conversion, EOCB cleared. ACSR clock setting register, which used select clock source. converter control register used control converter. Bits ADCR used select analog input channel. total four channels select. bit5~bit3 ADCR used PB0~PB3 configurations. analog input digital line determined these bits. Once line selected analog input, functions pull-high resistor this line disabled Label Selects converter clock source system clock/2 system clock/8 system clock/32 undefined Unused bit, read test mode used only ACSR (27H) Register Label ACS0 ACS1 PCR0 PCR1 Defines analog channel select. Unused bit, read Defines port configuration select. PCR0 PCR1 zero, circuit powered reduce power consumption Indicates conversion. conversion) Each time bits change state should initialised issuing START signal, otherwise EOCB flag have undefined condition. note Starts conversion. 0®1®0= Start 0®1= Reset converter EOCB ADCR (26H) Register Function converter circuit powered-on. EOCB (bit6 ADCR) conversion flag. Check this know when conversion completed. START ADCR used begin conversion converter. Giving START rising edge falling edge means that conversion started. order ensure that conversion completed, START should remain until EOCB cleared (end conversion). ACSR used testing purposes only. cannot used user. ACSR used select clock sources. When conversion completed, interrupt request flag will set. EOCB when START from Important Note initialisation: Special care must taken initialise converter each time Port channel selection bits modified, otherwise EOCB flag undefined condition. initialisation implemented setting START high then clearing zero within instruction cycles Port channel selection bits being modified. Note that Port channel selection bits cleared zero then initialisation required. Function
ADCS0 ADCS1 TEST
EOCB
START
Rev. 1.20
April 2006
HT49RV5/HT49CV5
ACS1 ACS0 Analog Input Channel Selection Register Note: Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Analog Channel
D0~D7 conversion result data LSB~MSB.
PCR1
PCR0
Port Configuration following programming example illustrates setup implement conversion. method polling EOCB ADCR register used detect when conversion cycle complete. Example: using EOCB Polling Method detect conversion EADI disable interrupt a,00000001B ACSR,a setup ACSR register select fSYS/8 clock a,00110000B ADCR,a setup ADCR register configure Port PB0~PB3 inputs select connected converter Port channel bits have changed following START signal (0-1-0) must issued within instruction cycles Start_conversion: START START START Polling_EOC: EOCB polling_EOC a,ADR adr_buffer,a Start_conversion
reset start poll ADCR register EOCB detect conversion continue polling read conversion result from register save result user defined memory
start next conversion
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Conversion Timing Display Memory HT49RV5/HT49CV5 provides area embedded data memory display. This area located from Bank Bank Pointer (BP; located RAM) switch display memory. When data written into 40H~55H will affect display. When written data written into 40H~55H meant access general SEG15~ SEG12 Grid0 Grid1 Grid2 Grid3 Grid4 Grid5 Grid6 Grid7 Grid8 Grid9 Grid10 41HU 43HU 45HU 47HU 49HU 4BHU 4DHU 4FHU 51HU 53HU 55HU SEG11~ SEG8 41HL 43HL 45HL 47HL 49HL 4BHL 4DHL 4FHL 51HL 53HL 55HL SEG7~ SEG4 40HU 42HU 44HU 46HU 48HU 4AHU 4CHU 4EHU 50HU 52HU 54HU SEG3~ SEG0 40HL 42HL 44HL 46HL 48HL 4AHL 4CHL 4EHL 50HL 52HL 54HL Display Memory purpose data memory. display memory read written only indirect addressing mode using MP1. When data written into display data area, automatically read driver which then generates corresponding driving signals. turn display off, written corresponding display memory, respectively. figure illustrates mapping between display memory pattern HT49RV5/ HT49CV5. Higher bits Lower bits
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Display Control Register VFDC Label Function Voltage Reset There voltage reset circuit (LVR) implemented microcontroller. This function enabled/disabled options. supply voltage device within range 0.9V~VLVR, such changing battery, will automatically reset device internally. includes following specifications:
voltage (0.9V~VLVR) remain origi-
Selects display mode 000= grids, segments 001= grids, segments 010= grids, segments VGS2~ 011= grids, segments VGS0 100= grids, segments 101= grids, segments 110= grids, segments 111= grids, segments VFDE Unused bit, read Controls display (1=enable; 0=disable)
state longer than 1ms. voltage state does exceed 1ms, will ignore will perform reset function.
uses function with external
Sets dimming quantity 000= pulse width 1/16. 001= pulse width 2/16. 010= pulse width 4/16. VDM2~V 011= pulse width 10/16. 100= pulse width 11/16. 101= pulse width 12/16. 110= pulse width 13/16. 111= pulse width 14/16. VFDC (28H) Register
signal perform chip reset. relationship between VLVR shown below.
power-on initial, 11-grid, 11-segment 1/16 pulse width display disabled. clock source come from system clock/4 (fSYS/4). Note:
VOPR voltage range proper chip operation 4MHz system clock.
Driver Output
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Voltage Reset Note: make sure that system oscillator stabilized, provides extra delay 1024 system clock pulses before starting normal operation. Since voltage maintain original state longer than 1ms, therefore delay enters reset mode. Options following shows configuration options HT49RV5/HT49CV5. these options should defined order ensure properly functioning system. Options type selection. This option decide crystal 32768Hz crystal oscillator chosen system clock. fWDT: clock source selection. There three types selections: system clock/4 VFD, Buzzer clock source selection. There types selections: system clock/4 enable/disable selection. enabled disabled option. time-out period selection. There four types selection: clock source divided fWDT/212~fWDT/213, fWDT/213~fWDT/214, fWDT/214~fWDT/215 fWDT/215~fWDT/216 times selection. This option defines method clear instruction. means that instructions clear WDT. means only both instructions have been executed, cleared. Buzzer output frequency selection. There eight types frequency signals buzzer output: fS/2~fS/28, means clock source selected options. Wake-up selection. This option defines wake-up capability. External pins only) have capability wake-up chip from HALT falling edge. (bit option) Pull-high selection. This option determine whether pull-high resistance viable input mode ports. PB0~PB3, PC6~PC7, PD0~PD1 PD4~PD7 independently selected. (bit option) Pull-high selection. This option determine whether pull-high resistance viable input pin. pins shared with other function selections. PA0/BZ, PA1/BZ, PA3/PFD: PA0, pins buzzer outputs. driver clock selection. There types frequency signals driver circuits: fS/20~fS/27. stands clock source selection options. ON/OFF HALT selection, HALT works only when clock source selects
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Options selection enable disable options selection. output, there types selections; PFD0 output, other PFD1 output. PFD0, PFD1 timer overflow signals Timer/Event Counter Timer/Event Counter respectively. selection: (7+1) (6+2) mode PD0: level output PWM0 output PD1: level output PWM1 output INT0 INT1 triggering edge: Disable; high low; high; high high SIOCLK: Serial interface clock. There falling edge, rising edge triggering edge CSEN: Serial selection: enable disable WCOL: SBDR write conflict
Application Circuits
illa
illa illa
Note:
resistance capacitance reset circuit should designed such ensure that stable remains within valid operating voltage range before bringing high.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Instruction Summary
Mnemonic Arithmetic A,[m] ADDM A,[m] A,[m] ADCM A,[m] A,[m] SUBM A,[m] A,[m] SBCM A,[m] data memory data memory immediate data data memory with carry data memory with carry Subtract immediate data from Subtract data memory from Subtract data memory from with result data memory Subtract data memory from with carry Subtract data memory from with carry result data memory Decimal adjust addition with result data memory 1(1) 1(1) 1(1) 1(1) 1(1) Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Z,C,AC,OV Description Instruction Cycle Flag Affected
Logic Operation A,[m] A,[m] A,[m] ANDM A,[m] A,[m] XORM A,[m] CPLA data memory data memory Exclusive-OR data memory data memory data memory Exclusive-OR data memory immediate data immediate data Exclusive-OR immediate data Complement data memory Complement data memory with result 1(1) 1(1) 1(1) 1(1)
Increment Decrement INCA DECA Rotate RRCA RLCA Data Move A,[m] [m],A Operation [m].i [m].i Clear data memory data memory 1(1) 1(1) None None Move data memory Move data memory Move immediate data 1(1) None None None Rotate data memory right with result Rotate data memory right Rotate data memory right through carry with result Rotate data memory right through carry Rotate data memory left with result Rotate data memory left Rotate data memory left through carry with result Rotate data memory left through carry 1(1) 1(1) 1(1) 1(1) None None None None Increment data memory with result Increment data memory Decrement data memory with result Decrement data memory 1(1) 1(1)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Mnemonic Branch addr [m].i [m].i SIZA SDZA CALL addr RETI Table Read TABRDC TABRDL Miscellaneous WDT1 WDT2 SWAP SWAPA HALT Note: operation Clear data memory data memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles data memory Swap nibbles data memory with result Enter power down mode 1(1) 1(1) 1(1) None None None TO,PDF TO(4),PDF(4) TO(4),PDF(4) None None TO,PDF Read code (current page) data memory TBLH Read code (last page) data memory TBLH 2(1) 2(1) None None Jump unconditionally Skip data memory zero Skip data memory zero with data movement Skip data memory zero Skip data memory zero Skip increment data memory zero Skip decrement data memory zero Skip increment data memory zero with result Skip decrement data memory zero with result Subroutine call Return from subroutine Return from subroutine load immediate data Return from interrupt 1(2) 1(2) 1(2) 1(2) 1(3) 1(3) 1(2) 1(2) None None None None None None None None None None None None None Description Instruction Cycle Flag Affected
Immediate data Data memory address Accumulator number bits addr: Program memory address Flag affected Flag affected
loading register occurs, execution cycle instructions will delayed more cycle (four system clocks). skipping next instruction occurs, execution cycle instructions will delayed more cycle (four system clocks). Otherwise original instruction cycle unchanged. flags affected execution status. Watchdog Timer cleared executing instruction, cleared. Otherwise flags remain unchanged.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Instruction Definition
A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) data memory carry accumulator contents specified data memory, accumulator carry flag added simultaneously, leaving result accumulator. ACC+[m]+C
accumulator carry data memory contents specified data memory, accumulator carry flag added simultaneously, leaving result specified data memory. ACC+[m]+C
data memory accumulator contents specified data memory accumulator added. result stored accumulator. ACC+[m]
immediate data accumulator contents accumulator specified data added, leaving result accumulator. ACC+x
accumulator data memory contents specified data memory accumulator added. result stored data memory. ACC+[m]
Rev. 1.20
April 2006
HT49RV5/HT49CV5
A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s) CALL addr Description Logical accumulator with data memory Data accumulator specified data memory perform bitwise logical_AND operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_AND operation. result stored accumulator.
Logical data memory with accumulator Data specified data memory accumulator perform bitwise logical_AND operation. result stored data memory.
Subroutine call instruction unconditionally calls subroutine located indicated address. program counter increments once obtain address next instruction, pushes this onto stack. indicated address then loaded. Program execution continues with instruction this address. Stack Program Counter+1 Program Counter addr
Operation
Affected flag(s)
Description Operation Affected flag(s)
Clear data memory contents specified data memory cleared
Rev. 1.20
April 2006
HT49RV5/HT49CV5
[m].i Description Operation Affected flag(s) Description Operation Clear data memory specified data memory cleared [m].i
Clear Watchdog Timer cleared (clears WDT). power down (PDF) time-out (TO) cleared.
Affected flag(s)
WDT1 Description
Preclear Watchdog Timer Together with WDT2, clears WDT. also cleared. Only execution this instruction without other preclear instruction just sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
WDT2 Description
Preclear Watchdog Timer Together with WDT1, clears WDT. also cleared. Only execution this instruction without other preclear instruction, sets indicated flag which implies this instruction been executed flags remain unchanged. 00H*
Operation
Affected flag(s)
Description Operation Affected flag(s)
Complement data memory Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
CPLA Description Complement data memory place result accumulator Each specified data memory logically complemented complement). Bits which previously contained changed vice-versa. complemented result stored accumulator contents data memory remain unchanged. Description
Operation Affected flag(s)
Decimal-Adjust accumulator addition accumulator value adjusted (Binary Coded Decimal) code. accumulator divided into nibbles. Each nibble adjusted code internal carry (AC1) will done nibble accumulator greater than adjustment done adding original value original value greater than carry set; otherwise original value remains unchanged. result stored data memory only carry flag affected. ACC.3~ACC.0 AC=1 then [m].3~[m].0 (ACC.3~ACC.0)+6, AC1=AC else [m].3~[m].0 (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+AC1 then [m].7~[m].4 ACC.7~ACC.4+6+AC1,C=1 else [m].7~[m].4 ACC.7~ACC.4+AC1,C=C
Operation
Affected flag(s)
Description Operation Affected flag(s)
Decrement data memory Data specified data memory decremented [m]-1
DECA Description Operation Affected flag(s)
Decrement data memory place result accumulator Data specified data memory decremented leaving result accumulator. contents data memory remain unchanged. [m]-1
Rev. 1.20
April 2006
HT49RV5/HT49CV5
HALT Description Enter power down mode This instruction stops program execution turns system clock. contents registers retained. prescaler cleared. power down (PDF) time-out (TO) cleared. Program Counter Program Counter+1 Description Operation Affected flag(s) INCA Description Operation Affected flag(s) addr Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Directly jump program counter replaced with directly-specified address unconditionally, control passed this destination. Program Counter
Operation
Affected flag(s)
Increment data memory Data specified data memory incremented [m]+1
Increment data memory place result accumulator Data specified data memory incremented leaving result accumulator. contents data memory remain unchanged. [m]+1
Move data memory accumulator contents specified data memory copied accumulator.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Description Operation Affected flag(s) [m],A Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) A,[m] Description Operation Affected flag(s) operation operation performed. Execution continues with next instruction. Program Counter Program Counter+1 Move immediate data accumulator 8-bit data specified code loaded into accumulator.
Move accumulator data memory contents accumulator copied specified data memory (one data memories).
Logical accumulator with data memory Data accumulator specified data memory (one data memories) perform bitwise logical_OR operation. result stored accumulator.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical_OR operation. result stored accumulator.
Logical data memory with accumulator Data data memory (one data memories) accumulator perform bitwise logical_OR operation. result stored data memory.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Description Operation Affected flag(s) Description Operation Return from subroutine program counter restored from stack. This 2-cycle instruction. Program Counter Stack
Return place immediate data accumulator program counter restored from stack accumulator loaded with specified 8-bit immediate data. Program Counter Stack
Affected flag(s)
RETI Description Operation
Return from interrupt program counter restored from stack, interrupts enabled setting bit. enable master (global) interrupt bit. Program Counter Stack
Affected flag(s)
Description Operation
Rotate data memory left contents specified data memory rotated left with rotated into [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7
Affected flag(s)
Description Operation
Rotate data memory left place result accumulator Data specified data memory rotated left with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Description Operation Rotate data memory left through carry contents specified data memory carry flag rotated left. replaces carry bit; original carry flag rotated into position. [m].(i+1) [m].i; [m].i:bit data memory (i=0~6) [m].0 [m].7 RLCA Description
Affected flag(s)
Rotate left through carry place result accumulator Data specified data memory carry flag rotated left. replaces carry original carry flag rotated into position. rotated result stored accumulator contents data memory remain unchanged. ACC.(i+1) [m].i; [m].i:bit data memory (i=0~6) ACC.0 [m].7
Operation
Affected flag(s)
Description Operation
Rotate data memory right contents specified data memory rotated right with rotated [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Description Operation
Rotate right place result accumulator Data specified data memory rotated right with rotated into leaving rotated result accumulator. contents data memory remain unchanged. ACC.(i) [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0
Affected flag(s)
Description Operation
Rotate data memory right through carry contents specified data memory carry flag together rotated right. replaces carry bit; original carry flag rotated into position. [m].i [m].(i+1); [m].i:bit data memory (i=0~6) [m].7 [m].0
Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
RRCA Description Rotate right through carry place result accumulator Data specified data memory carry flag rotated right. replaces carry original carry flag rotated into position. rotated result stored accumulator. contents data memory remain unchanged. ACC.i [m].(i+1); [m].i:bit data memory (i=0~6) ACC.7 [m].0 A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) Description
Operation
Affected flag(s)
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result accumulator. ACC+[m]+C
Subtract data memory carry from accumulator contents specified data memory complement carry flag subtracted from accumulator, leaving result data memory. ACC+[m]+C
Skip decrement data memory contents specified data memory decremented result next instruction skipped. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
SDZA Description
Decrement data memory place result ACC, skip contents specified data memory decremented result next instruction skipped. result stored accumulator data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]-1)=0, ([m]-1)
Operation Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Description Operation Affected flag(s) [m]. Description Operation Affected flag(s) Description data memory Each specified data memory
data memory specified data memory [m].i
Skip increment data memory contents specified data memory incremented result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
SIZA Description
Increment data memory place result ACC, skip contents specified data memory incremented result next instruction skipped result stored accumulator. data memory remains unchanged. result following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip ([m]+1)=0, ([m]+1)
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory next instruction skipped. data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip
Operation Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) SWAP Description Operation Affected flag(s) SWAPA Description Operation Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result accumulator. ACC+[m]+1
Subtract data memory from accumulator specified data memory subtracted from contents accumulator, leaving result data memory. ACC+[m]+1
Subtract immediate data from accumulator immediate data specified code subtracted from contents accumulator, leaving result accumulator. ACC+x+1
Swap nibbles within data memory low-order high-order nibbles specified data memory data memories) interchanged. [m].3~[m].0 [m].7~[m].4
Swap data memory place result accumulator low-order high-order nibbles specified data memory interchanged, writing result accumulator. contents data memory remain unchanged. ACC.3~ACC.0 [m].7~[m].4 ACC.7~ACC.4 [m].3~[m].0
Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Description Skip data memory contents specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
Description
Move data memory ACC, skip contents specified data memory copied accumulator. contents following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m]=0
Operation Affected flag(s)
[m].i Description
Skip data memory specified data memory following instruction, fetched during current instruction execution, discarded dummy cycle replaced proper instruction cycles). Otherwise proceed with next instruction cycle). Skip [m].i=0
Operation Affected flag(s)
TABRDC Description Operation
Move code (current page) TBLH data memory byte code (current page) addressed table pointer (TBLP) moved specified data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
TABRDL Description Operation
Move code (last page) TBLH data memory byte code (last page) addressed table pointer (TBLP) moved data memory high byte transferred TBLH directly. code (low byte) TBLH code (high byte)
Affected flag(s)
Rev. 1.20
April 2006
HT49RV5/HT49CV5
A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) Description Operation Affected flag(s) Logical accumulator with data memory Data accumulator indicated data memory perform bitwise logical Exclusive_OR operation result stored accumulator.
Logical data memory with accumulator Data indicated data memory accumulator perform bitwise logical Exclusive_OR operation. result stored data memory. flag affected.
Logical immediate data accumulator Data accumulator specified data perform bitwise logical Exclusive_OR operation. result stored accumulator. flag affected.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Package Information
56-pin SSOP (300mil) Outline Dimensions
Symbol
Dimensions Min. Nom. Max.
Rev. 1.20
April 2006
HT49RV5/HT49CV5
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) Floor, Building No.889, Shan Rd., Shanghai, China 200233 Tel: 021-6485-5560 Fax: 021-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 43F, Plaza, Shen Zhong Road, Shenzhen, China 518031 Tel: 0755-8346-5589 Fax: 0755-8346-5590 ISDN: 0755-8346-5591 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Street, Xicheng District, Beijing, China 100031 Tel: 010-6641-0030, 6641-7751, 6641-7752 Fax: 010-6641-0125 Holmate Semiconductor, Inc. (North America Sales Office) 46712 Fremont Blvd., Fremont, 94538 Tel: 510-252-9880 Fax: 510-252-9885 http://www.holmate.com Copyright 2006 HOLTEK SEMICONDUCTOR INC. information appearing this Data Sheet believed accurate time publication. However, Holtek assumes responsibility arising from specifications described. applications mentioned herein used solely purpose illustration Holtek makes warranty representation that such applications will suitable without further modification, recommends products application that present risk human life malfunction otherwise. products authorized critical components life support devices systems. Holtek reserves right alter products without prior notification. most up-to-date information, please visit site http://www.holtek.com.tw.
Rev. 1.20
April 2006
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