HYB5116160BSJ-50/-60/-70 words 16-bit organization operating temp

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HYB5116160BSJ-50/-60/-70 words 16-bit organization operating temp

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16-Bit Dynamic (4k-Refresh)
HYB5116160BSJ-50/-60/-70
words 16-bit organization operating temperature Performance: tRAC tCAC access time access time Access time from address Read/Write cycle time Fast page mode cycle time
Single supply power dissipation max. active (-50 version) max. active (-60 version) max. active (-70 version) standby (TTL) 5.5. standby (MOS) Output unlatched cycle allows two-dimensional chip selection Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh self refresh Fast page mode capability inputs, outputs clocks fully TTL-compatible 4096 refresh cycles/64 Plastic Package: P-SOJ-42-1
Semiconductor Group
1.96
5116160BSJ-50/-60/-70 16-DRAM
5116160BSJ MBit dynamic organized words bits. 5116160BSJ utilizes submicron CMOS silicon gate process technology, well advanced circuit techniques provide wide operating margins, both internally system user. Multiplexed address inputs permit 5116160BSJ packaged standard plastic package. These packages provide high system densities compatible with commonly used automatic testing insertion equipment. System-oriented features include single power supply, direct interfacing with high-performance logic device families such Schottky TTL. Ordering Information Type 5116160BSJ-50 5116160BSJ-60 5116160BSJ-70 Names I/O1-I/O16 UCAS LCAS Address Inputs Column Addess Inputs Address Strobe Output Enable Data Input/Output Upper Column Address Strobe Lower Column Address Strobe Read/Write Input Power Supply Ground connected Ordering Code request request request Package Descriptions
P-SOJ-42-1 DRAM (access time P-SOJ-42-1 DRAM (access time P-SOJ-42-1 DRAM (access time
N.C.
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
P-SOJ-42 (400 mil) I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 N.C. N.C. I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 N.C. LCAS UCAS
Configuration Truth Table LCAS UCAS I/O1-I/O8 High-Z High-Z Dout High-Z Dout Don't care High-Z I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
I/O1 I/O2
I/O16
UCAS LCAS
Data Buffer
Clock Generator
Data Buffer
Column Address Buffer(8)
Column Decoder
Refresh Controller
Sense Amplifier Gating
Refresh Counter (12)
Address Buffers(12)
Decoder 4096
Memory Array 4096x256x16
Clock
Generator
Voltage Down Generator
(internal)
Block Diagram
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Absolute Maximum Ratings Operating temperature range Storage temperature range.- Input/output voltage .-0.5 (Vcc+0.5,7.0) Power supply voltage.-1.0V Power dissipation. Data current (short circuit) Note: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability.
Characteristics Parameter Input high voltage Input voltage Output high voltage (IOUT Output voltage (IOUT Input leakage current,any input 0.3V, other pins Output leakage current disabled, VOUT 0.3V) Average supply current: version version version (RAS, CAS, address cycling, min.) Symbol Limit Values min. max. Vcc+0.5 Unit Test Condition
II(L) IO(L) ICC1
Standby supply current (RAS VIH) ICC2
Average supply current, during RAS-only refresh cycles: version version version (RAS cycling: VIH, min.) Semiconductor Group
ICC3
5116160BSJ-50/-60/-70 16-DRAM
Characteristics (cont'd) Parameter Symbol Limit Values min. max. Unit Test Condition
Average supply current, during fast page mode: version version version
(RAS VIL, CAS, address cycling, min.)
ICC4
Standby supply current (RAS
Average supply current, during CASbefore-RAS refresh mode: version version version (RAS, cycling, min.)
ICC5 ICC6
Average Self Refresh Current
(CBR cycle with tRAS>TRASSmin., held low, WE=Vcc-0.2V, Address Din=Vcc-0.2V 0.2V)
ICC7
Capacitance °C,VCC Parameter Input capacitance A11) Input capacitance (RAS, UCAS, LCAS, capacitance (I/O1-I/O16) Symbol Limit Values min. max. Unit
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Characteristics 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
common parameters
Random read write cycle time precharge time pulse width pulse width address setup time address hold time Column address setup time Column address hold time delay time column address delay time hold time hold time precharge time Transition time (rise fall) Refresh period tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tREF
Read Cycle
Access time from Access time from access time Read command setup time Read command hold time Read command hold time referenced output low-Z Output buffer turn-off delay tRAC tCAC tOEA tRCS tRCH tRRH tCLZ tOFF 8,10
Access time from column address Column address lead time tRAL
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Output buffer turn-off delay from Data delay high data delay high data delay
tOEZ tDZO tCDD tODD
Write Cycle
Write command hold time Write command pulse width Write command setup time tWCH tWCS
Write command lead time tRWL Write command lead time tCWL Data setup time Data hold time Data delay tDZC
Read-Modify-Write Cycle
Read-write cycle time delay time delay time command hold time tRWC tRWD tCWD tOEH
Column address delay time tAWD
Fast Page Mode Cycle
Fast page mode cycle time precharge time Access time from precharge pulse width precharge Delay tCPA tRAS tRHPC
200k
200k
200k
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Characteristics (cont'd) 5)6) °C,VCC Parameter
Symbol
Limit Values min. max. max. min. max. min.
Unit Note
Fast Page Mode Read-Modify-Write Cycle
Fast page mode read-write cycle time precharge tPRWC tCPWD
CAS-before-RAS Refresh Cycle
setup time hold time precharge time Write precharge time tCSR tCHR tRPC tWRP
Write hold time referenced tWRH
CAS-before-RAS Counter Test Cycle
precharge time tCPT
Self Refresh Cycle
pulse width precharge time hold time tRASS tRPS tCHS 100k 100k 100k
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Notes:
voltages referenced VSS. ICC1, ICC3, ICC4 ICC6 depend cycle rate. ICC1 ICC4 depend output loading. Specified values measured with output open. Address changed once less while VIL. case ICC4 changed once less during fast page mode cycle (tPC). initial pause required after power-up followed cycles which least cycle refresh cycle, before proper device operation achieved. case using internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. measurements assume (min.) (max.) reference levels measuring timing input signals. Transition times also measured between VIL. Measured with load equivalent loads Operation within tRCD (max.) limit ensures that tRAC (max.) met. tRCD (max.) specified reference point only: tRCD greater than specified tRCD (max.) limit, then access time controlled tCAC. 10)Operation within tRAD (max.) limit ensures that tRAC (max.) met. tRAD (max.) specified reference point only: tRAD greater than specified tRAD (max.) limit, then access time controlled tAA. 11)Either tRCH tRRH must satisfied read cycle. 12)tOFF (max.) tOEZ (max.) define time which outputs achieve open-circuit condition referenced output voltage levels. 13)Either tDZC tDZO must satisfied. 14)Either tCDD tODD must satisfied. 15)tWCS, tRWD, tCWD, tAWD tCPWD restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min.), cycle early write cycle will remain open-circuit (high impedance) through entire cycle; tRWD tRWD (min.), tCWD tCWD (min.), tAWD tAWD (min.) tCPWD tCPWD (min.) cycle read-write cycle pins will contain data read from selected cells. neither above sets conditions satisfied, condition pins access time) indeterminate. 16)These parameters referenced leading edge early write cycles leading edge read-write cycles. 17)When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refreshed evenly distributed manner over refresh interval using refresh cycles, then only cycle must performed immediately after exit from Self Refresh. addresses being refreshed other manner (ROR Distributed/Burst; CBR-Burst) over refresh interval, then full refreshes must performed immediately before entry immediately after exit from Self Refresh.
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
UCAS LCAS
tRAD tASR tASC tCAH
Column Address
tASR
Address
Address
Address
tRCH tRAH tRCS tRRH tOEA
tDZC tDZO tCAC tCLZ
tCDD tODD
I/O1-I/O16 (Inputs)
tOFF tOEZ
Valid Data
I/O1-I/O16
(Outputs)
tRAC
Read Cycle
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
UCAS LCAS
tRAD tASR tASC tCAH
Column Address
tASR
Address
Address
Address
tRAH
tWCS
tCWL tWCH tRWL
I/O1-I/O16 (Inputs)
Valid Data
I/O1-I/O16 (Outputs)
Write Cycle (Early Write) Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tCSH tRCD tRSH tCAS tRAL
tCRP
UCAS LCAS
tRAD tASR tASC tCAH
Column Address
tASR
Address
Address
Address
tRAH
tCWL tRWL
tOEH
tODD tDZO tDZC tOEZ
I/O1-I/O16 (Inputs)
Valid Data
tCLZ tOEA
Hi-Z Hi-Z
I/O1-I/O16 (Outputs)
Write Cycle Controlled Write) Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRWC tRAS
tCSH tRCD tRSH tCAS tCRP
UCAS LCAS
tRAH tASR
tCAH tASC
Column Address
tASR
Address
Address
Address
tRAD
tAWD tCWD tRWD
tCWL tRWL
tRCS
tOEA
tOEH
tDZO tDZC
Valid Data
I/O1-I/O16 (Inputs)
tCLZ tCAC
Data
tODD tOEZ
I/O1-I/O16
(Outputs)
tRAC
Read-Write (Read-Modify-Write) Cycle Semiconductor Group
tRASP tPRWC tCAS tCAS tCAH tASC tASC
Column Address Column Address
tCSH tRCD tCAS tRAL tASR
Address
tRSH tCRP
Semiconductor Group
UCAS LCAS
tASR tASC
Column Address
tRAD tRAH tCAH tCAH
Address
Address
Fast Page Mode Read-Modify-Write Cycle
tRCS tAWD tOEA tOEA tOEA tAWD tAWD
tRWD tCWD tCWL tCWL
tCPWD tCWD
tCPWD tCWD
tRWL tCWL
tCPA tDZC
Data
tCPA tODD
Data
tDZC tCLZ tDZO tCLZ tCAC tRAC tOEZ
Data Data
tDZC tCLZ tOEH
tODD
Data
I/O1-I/O16 (Inputs)
tODD tCAC
tOEH tOEZ
tOEH
Data
I/O1-I/O16 (Outputs)
5116160BSJ-50/-60/-70 16-DRAM
5116160BSJ-50/-60/-70 16-DRAM
tRASP
tRCD
UCAS LCAS
tCAS tCSH tCAS
tRHCP tRSH tCAS tCRP
tRAH tASR
Address
Addr
tCAH
Column Address
tASC
tASC
tCAH tASC
tCAH tASR
Address Column Address
Column Address
tRAD tRCH tRCS tRCS tRCS
tRCH
tOEA
tCPA tOEA
tCPA tOEA tDZC tDZO tODD
tRRH
tDZC tDZO tODD tCAC tOFF tCLZ tOFF tOEZ
Valid Data
tDZC tDZO
tCDD tODD
I/O1-I/O16 (Inputs)
tCAC tOFF tCLZ tOEZ
Valid Data
tCAC tCLZ
tOFF tOEZ
Valid Data
I/O1-I/O16 (Outputs)
Fast Page Mode Read Cycle Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRASP
tCAS tRCD
tCAS
tRSH tCAS tCRP
UCAS LCAS
tRAL tRAH tASR tCAH tASC
Column Address
tASC tCAH
Column Address
tASC
tCAH
tASR
Column Address
Address
Addr
Column Address
tRAD
tCWL tWCS tWCH
tCWL tWCS tWCH
tCWL tRWL tWCS tWCH
I/O1-I/O16 (Inputs)
Valid Data
Valid Data
Valid Data
I/O1-I/O16 (Outputs)
HI-Z
Fast Page Mode Early Write Cycle Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tCRP tRPC
UCAS LCAS
tRAH tASR
tASR
Address
Address
Address
I/O1-I/O16 (Outputs)
HI-Z
RAS-Only Refresh Cycle
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tRPC tCSR
UCAS LCAS
tCRP tCHR tRPC
tWRP tWRH
tOEZ
tCDD
I/O1-I/O16 (Inputs)
tODD
I/O1-I/O16 (Outputs)VOL
HI-Z
tOFF
CAS-Before-RAS Refresh Cycle Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tRAS
tRCD
UCAS LCAS
tRSH tCHR tCRP
tRAD tRAH tASR tASC tWRP tCAH tWRH tASR
Address
Address
Addr
Column Address
tRCS
tRRH
tOEA
tDZC tDZO
tCDD tODD
I/O1-I/O16 (Inputs)
tCAC tCLZ tRAC tOEZ
Valid Data
tOFF
I/O1-I/O16 (Outputs)
HI-Z
Hidden Refresh Cycle (Read) Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tRAS
tRCD
UCAS LCAS
tRSH
tCHR
tCRP
tRAD tRAH tASR tASC tCAH
Column Address
tASR
Address
Address
Addr
tWCS
tWCH
tWRP
tWRH
I/O1-I/O16 (Input)
Valid Data
I/O1-I/O16 (Output)
HI-Z
Hidden Refresh Cycle (Early Write) Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRASS
tRPS
tRPC tCSR
tCHS
tCRP
tWRP tWRH
UCAS LCAS
tOEZ
tCDD
I/O1-I/O16 (Inputs)
tODD
I/O1-I/O16 (Outputs)
HI-Z
tOFF
before Self Refresh Cycle
Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
tRAS
tRSH tCAS tRAL tASR
Address
tCSR
UCAS LCAS
tCHR
tCPT
tASC
tCAH
Address
Column Address
Read Cycle
tWRP tWRH
tRCS
tCAC
tRRH tRCH
tOEA
I/O1-I/O16 (Inputs)
tDZC tDZO
tODD tCLZ tOEZ
Valid Data
tCDD tOFF
I/O1-I/O16 (Outputs)
Write Cycle
tWRP tWRH
tWCS
tWCH
tRWL tCWL
I/O1-I/O16 (Inputs) I/O1-I/O16 (Outputs)
HI-Z
Valid Data
Read-Modify-Write Cycle
tWRP
tWRH
tRCS
tAWD tCWD tCAC tOEA
tCWL tRWL tOEH
I/O1-I/O16 (Inputs)
tDZC tDZO
Data
I/O1-I/O16 (Outputs)
HI-Z
tCLZ
tCAC
D.Out
tODD tOEZ
HI-Z
CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group
5116160BSJ-50/-60/-70 16-DRAM
Package Outlines
Plastic Package P-SOJ-42 (400 mil) (Small Outline J-lead, SMD)
10.3
-0.3
1.27 0.43
0.81 max. 0.18 0.08 11.2
0.25
0.15
0.18
25.4
GPJ05853
27.43
-0.25
Index marking
does include plastic metal protusion 0.15 side
Semiconductor Group

HYB5116160BSJ-50/-60/-70 words 16-bit organization operating temp

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