74HC/HCT4024 7-stage binary ripple counter Product specification

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74HC/HCT4024 7-stage binary ripple counter Product specification

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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4024 7-stage binary ripple counter
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4024 high-speed Si-gate CMOS devices compatible with "4024" "4000B" series. They specified compliance with JEDEC standard 74HC/HCT4024 7-stage binary ripple counters with clock input (CP), overriding asynchronous master reset input (MR) seven fully buffered parallel outputs Q6). QUICK REFERENCE DATA Tamb
74HC/HCT4024
counter advances HIGH-to-LOW transition HIGH clears counter stages forces outputs LOW, independent state Each counter stage static toggle flip-flop. Schmitt-trigger action clock input makes circuit highly tolerant slower clock rise fall times. APPLICATIONS Frequency dividing circuits Time delay circuits
TYPICAL SYMBOL tPHL/ tPLH fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay maximum clock frequency input capacitance power dissipation capacitance package notes CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
DESCRIPTION SYMBOL n.c. NAME FUNCTION clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) parallel outputs ground connected positive supply voltage
74HC/HCT4024
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
FUNCTION TABLE INPUTS Notes
74HC/HCT4024
OUTPUTS change count
HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER +125 +125 max.
74HC/HCT4024
TEST CONDITIONS UNIT WAVEFORMS Fig.6
min. typ. max. min. max. min. tPHL/ tPLH propagation delay propagation delay propagation delay Qn+1 output transition time
tPHL
Fig.6
tPHL/ tPLH
Fig.6
tTHL/ tTLH
Fig.6
clock pulse width HIGH master reset pulse width HIGH removal time maximum clock pulse frequency
Fig.6
Fig.6
trem
Fig.6
fmax
Fig.6
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT4024
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below.
INPUT
UNIT LOAD COEFFICIENT 0.75 0.85
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER +125 +125 max. Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 Fig.6 UNIT WAVEFORMS TEST CONDITIONS
min. typ. max. min. max. min. tPHL/ tPLH tPHL tPHL/ tPLH tTHL/ tTLH trem fmax propagation delay propagation delay propagation delay Qn+1 output transition time clock pulse width HIGH master reset pulse width HIGH removal time maximum clock pulse frequency
December 1990
Philips Semiconductors
Product specification
7-stage binary ripple counter
WAVEFORMS
74HC/HCT4024
Also showing master reset (MR) pulse width, master reset output (Qn) propagation delays master reset clock (CP) removal time. 50%; VCC. HCT:
Fig.6
Waveforms showing clock (CP) output (Qn) propagation delays, clock pulse width, output transition times maximum clock frequency.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990

74HC/HCT4024 7-stage binary ripple counter Product specification

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