74HC/HCT4020 14-stage binary ripple counter Product specification
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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4020 14-stage binary ripple counter
Product specification File under Integrated Circuits, IC06 September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4020 high-speed Si-gate CMOS devices compatible with "4020" "4000B" series. They specified compliance with JEDEC standard QUICK REFERENCE DATA Tamb
74HC/HCT4020
74HC/HCT4020 14-stage binary ripple counters with clock input (CP), overriding asynchronous master reset input (MR) twelve fully buffered parallel outputs (Q0, Q13). counter advanced HIGH-to-LOW transition HIGH clears counter stages forces outputs LOW, independent state Each counter stage static toggle flip-flop.
TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay Qn+1 fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". maximum clock frequency input capacitance power dissipation capacitance package notes CONDITIONS UNIT
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
DESCRIPTION SYMBOL parallel outputs ground
74HC/HCT4020
NAME FUNCTION
clock input (HIGH-to-LOW, edge-triggered) master reset input (active HIGH) positive supply voltage
fpage
RCTR14
CT=0
MGA829
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
FUNCTION TABLE INPUTS Notes OUTPUTS change count
Fig.4 Functional diagram.
HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay Qn+1 propagation delay output transition time typ. max. min. max. +125 min. max.
74HC/HCT4020
TEST CONDITIONS UNIT WAVEFORMS Fig.7
tPHL/ tPLH
Fig.7
tPHL
Fig.8
tTHL/ tTLH
Fig.7
clock pulse width HIGH
Fig.7
master reset pulse width HIGH removal time maximum clock pulse frequency
Fig.8
trem
Fig.8
fmax
Fig.7
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category: Note types
74HC/HCT4020
value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below.
INPUT
UNIT LOAD COEFFICIENT 0.85 1.10
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tPHL tTHL/ tTLH trem fmax propagation delay propagation delay Qn+1 propagation delay output transition time clock pulse width HIGH typ. max. min. max. +125 min. max. Fig.7 Fig.7 Fig.8 Fig.7 Fig.7 Fig.8 Fig.8 Fig.7 UNIT WAVEFORMS TEST CONDITIONS
master reset pulse width HIGH removal time maximum clock pulse frequency
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
WAVEFORMS
74HC/HCT4020
50%; VCC. HCT:
Fig.7
Waveforms showing clock (CP) output (Qn) propagation delays, clock pulse width, output transition times maximum clock frequency.
50%; VCC. HCT:
Fig.8
Waveforms showing master reset (MR) pulse width, master reset output (Qn) propagation delays master reset clock (CP) removal time.
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
September 1993
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