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IBM01174004M 411/11, 5.0VMMDD29DSU-011010527. IBM0117400P4M 411/11, 3.


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Discontinued (9/98 last order; 3/99 last ship)
IBM01174004M 411/11, 5.0VMMDD29DSU-011010527. IBM0117400P4M 411/11, 3.3V, SRMMDD29DSU-011010527. IBM0117400M4M 411/11, 5.0V, SRMMDD29DSU-011010527. IBM0117400B4M 411/11, 3.3VMMDD29DSU-011010527.
IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
4,194,304 word organization Single 3.3V 0.3V 5.0V 0.5V power supply Standard Power (SP) Power (LP) 2048 Refresh Cycles Refresh Rate version) Refresh Rate version) High Performance:
tRAC Access Time tCAC Access Time Column Address Access Time Cycle Time Fast Page Mode Cycle Time Units
Power Dissipation Active (max) Standby: Inputs (max) Standby: CMOS Inputs (max) version) version) Self Refresh version only) 200µA (3.3 Volt) 300µA (5.0 Volt) Fast Page Mode Read-Modify-Write Only before Refresh Hidden Refresh
Package: TSOP-26/24 (300mil 675mil) SOJ-26/24 (300mil 675mil)
Description
IBM0117400 dynamic organized 4,194,304 words bits, which very "sleep mode" power consumption option. These devices fabricated IBM's advanced 0.5µm CMOS silicon gate process technology. circuit process have been carefully designed provide high performance, power dissipation, high reliability. devices operate with single 3.3V 0.3V 5.0V 0.5V power supply. addresses required access data multiplexed strobed with RAS, strobed with CAS).
Assignments (Top View)
I/O0 I/O1
Description
Address Strobe Column Address Strobe Read/Write Input Address Inputs Output Enable Data Input/Output Power (+3.3V +5.0V) Ground
I/O3 I/O2
I/O0 I/O3
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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Discontinued (9/98 last order; 3/99 last ship)
IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Ordering Information
Part Number IBM0117400J1 IBM0117400J1 IBM0117400T1 IBM0117400T1 IBM0117400BJ1 IBM0117400BJ1 IBM0117400BT1 IBM0117400BT1 IBM0117400MT1 IBM0117400MT1 IBM0117400PT1 IBM0117400PT1 Self Refresh Power Supply 5.0V 5.0V 5.0V 5.0V 3.3V 3.3V 3.3V 3.3V 5.0V 5.0V 3.3V 3.3V Speed 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns Package 300mil 26/24 300mil 26/24 300mil TSOP 26/24 300mil TSOP 26/24 300mil 26/24 300mil 26/24 300mil TSOP 26/24 300mil TSOP 26/24 300mil TSOP 26/24 300mil TSOP 26/24 300mil TSOP 26/24 300mil TSOP 26/24 Notes
Standard Power version (IBM0117400 IBM0117400B); Power version (IBM0117400M IBM00117400P)
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Block Diagram
(5.0 Volt version) OCDs)
I/O0
I/O1
I/O2
I/O3
Regulator
(internal)
Data Buffer
Data Buffer
Clock Generator
Column Address Buffer (11)
Column Decoder Gate
Sense Amplifiers
Refresh Controller
2048
Refresh Counter (11) Decoder
Memory Array 2048 2048 2048
Address Buffer (11)
Clock Generator
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Truth Table
Function Standby Read Early-Write Delayed-Write Read-Modify-Write Fast Page Mode Read Fast Page Mode Write Fast Page Mode Read-Modify-Write RAS-Only Refresh CAS-Before-RAS Refresh Read Hidden Refresh Write Self Refresh version only) Data High Impedance Cycle Cycle Cycle Cycle Cycle Cycle Address Address I/O0 I/O3 High Impedance Data Data Data Data Out, Data Data Data Data Data Data Out, Data Data Out, Data High Impedance High Impedance Data
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Absolute Maximum Ratings
Rating Symbol VOUT TOPR TSTG IOUT Parameter Volt Device Power Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Power Dissipation Short Circuit Output Current -0.5 +4.6 -0.5 (VCC+0.5, 4.6) -0.5 (VCC+0.5, 4.6) +150 Volt Device -1.0 +7.0 -0.5 (VCC+0.5, 7.0) -0.5 (VCC+0.5, 7.0) +150 Units Notes
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Recommended Operating Conditions (TA= 70°C)
Volt Device Symbol Parameter Min. Supply Voltage Input High Voltage Input Voltage -0.5 Typ. Max. Min. -0.5 Typ. Max. Volt Device Units Notes
voltages referenced VSS. overshoot 1.2V pulse widths 4.0ns with Volt, 2.0V pulse widths 4.0ns 1.0V 8.0ns) with Volt. Additionally, undershoot -2.0V pulse widths 4.0ns with Volt, -2.0V pulse widths 4.0ns -1.0V 8.0ns) with Volt. Pulse widths measured points with amplitude measured peak reference.
Capacitance (TA= 25°C, VCC= 3.3V 0.3V VCC= 5.0V 0.5V)
Symbol Parameter Input Capacitance A10) Input Capacitance (RAS, CAS, Output Capacitance (I/O0 I/O3) Min. Max. Units Notes
Input capacitance measurements made with rise time shift method with disable output.
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Electrical Characteristics (TA= +70°C, VCC= 3.3V 0.3V VCC= 5.0V 0.5V)
Symbol ICC1 Parameter Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: min.) Standby Current (TTL) Power Supply Standby Current (RAS VIH) Only Refresh Current Average Power Supply Current, Only Mode (RAS Cycling, VIH: min) Fast Page Mode Current Average Power Supply Current (RAS VIL, CAS, Address Cycling: min) Standby Current (CMOS) Power Supply Standby Current (RAS 0.2V) Before Refresh Current Average Power Supply Current, Before Mode (RAS, CAS, Cycling: min) Self Refresh Current, version only Average Power Supply Current during Self Refresh cycle with tRASS (min); held low; 0.2V; Addresses 0.2V 0.2V. Input Leakage Current Input Leakage Current, input (0.0 (VCC 0.3V)), Other Pins Under Test Output Leakage Current (DOUT disabled, VOUT VCC) Output Level (TTL) Output Level Voltage (IOUT -2.0mA 3.3V, IOUT -5mA 5.0V) Output Level (TTL) Output Level Voltage (IOUT +2.0mA 3.3V, IOUT +4.2mA 5.0V) version version 3.3V 5.0V Min. Max. Units Notes
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
II(L)
IO(L)
ICC1, ICC3, ICC4 ICC6 depend cycle rate. ICC1 ICC4 depend output loading. Specified values obtained with output open. Address changed once less while =VIL. case ICC4, changed once less when =VIH.
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Characteristics (TA= +70°C, VCC= 3.3V 0.3V VCC= 5.0V 0.5V)
initial pause 200µs required after power-up followed only refresh cycles before proper device operation achieved. case using internal refresh counter, minimum before refresh cycles instead only refresh cycles required. measurements assume tT=5ns. VIH(min.) VIL(max.) reference levels measuring timing input signals. Also, transition times measured between VIL.
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tDZO tDZC Parameter Min. Random Read Write Cycle Time Precharge Time Precharge Time Pulse Width Pulse Width Address Setup Time Address Hold Time Column Address Setup Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time from Delay Time from Transition Time (Rise Fall) Max. Min. Max. Units Notes
Operation within tRCD(max.) limit ensures that tRAC(max.) met. tRCD(max.) specified reference point only. tRCD greater than specified tRCD(max.) limit, then access time controlled tCAC. Operation within tRAD(max.) limit ensures that tRAC(max.) met. tRAD(max.) specified reference point only. tRAD greater than specified tRAD(max.) limit, then access time controlled tAA. Either tDZC tDZO must satisfied. measurements assume tT=5ns.
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Write Cycle
Symbol tWCS tWCH tRWL tCWL tOED Parameter Min. Write Command Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Delay Time Setup Time Hold Time Max. Min. Max. Units Notes
tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) through entire cycle. tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min), tCPW tCPW (min)(Fast Page Mode), cycle Read-Modify-Write cycle data will contain data read from selected cell. neither above sets conditions satisfied, condition data access time) indeterminate. Either tCDD tOED must satisfied. These parameters referenced leading edge early write cycles leading edge Read-Modify-Write cycles.
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Read Cycle
Symbol tRAC tCAC tOEA tRCS tRCH tRRH tRAL tCAL tCLZ tOHO tOFF tOEZ tCDD Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Column Address Lead Time Output Low-Z Output Data Hold Time Output Data Hold from Output Buffer Turn-Off Delay Output Buffer Turn-Off Delay from Delay Time Parameter Min. Max. Min. Max. Units Notes
Operation within tRCD(max.) limit ensures that tRAC(max.) met. tRCD(max.) specified reference point only. tRCD greater than specified tRCD(max.) limit, then access time controlled tCAC. Operation within tRAD(max.) limit ensures that tRAC(max.) met. tRAD(max.) specified reference point only. tRAD greater than specified tRAD(max.) limit, then access time controlled tAA. Measured with specified current load 100pF. Either tRCH tRRH must satisfied read cycle. tOFF (max) tOEZ (max) define time which output achieves open circuit condition referenced output voltage levels. Either tCDD tOED must satisfied.
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Read-Modify-Write Cycle
Symbol tRWC tRWD tCWD tAWD tOEH Parameter Min. Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Command Hold Time Max. Min. Max. Units Notes
tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) through entire cycle. tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min), tCPW tCPW (min)(Fast Page Mode), cycle Read-Modify-Write cycle data will contain data read from selected cell. neither above sets conditions satisfied, condition data access time) indeterminate.
Fast Page Mode Cycle
Symbol tRASP tCPA tCPRH Parameter Min. Fast Page Mode Cycle Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge Max. 200K Min. Max. 200K Units Notes
Measured with specified current load 100pF.
Fast Page Mode Read-Modify-Write Cycle
Symbol tPRWC tCPW Parameter Min. Fast Page Mode Read-Modify-Write Cycle Time Delay Time from Precharge Max. Min. Max. Units Notes
tWCS, tRWD, tCWD, tAWD tCPW restrictive operating parameters. They included data sheet electrical characteristics only. tWCS tWCS (min), cycle early write cycle data will remain open circuit (high impedance) through entire cycle. tRWD tRWD (min), tCWD tCWD (min), tAWD tAWD (min), tCPW tCPW (min)(Fast Page Mode), cycle Read-Modify-Write cycle data will contain data read from selected cell. neither above sets conditions satisfied, condition data access time) indeterminate.
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Refresh Cycle
Symbol tCSR tCHR tWRP tWRH tRPC Parameter Min. Setup Time (CAS before Refresh Cycle) Hold Time (CAS before Refresh Cycle) Setup Time (CAS before Refresh Cycle) Hold Time (CAS before Cycle) Precharge Hold Time Max. Min. Max. Units Notes
Self Refresh Cycle Power Version Only
Symbol tRASS tRPS tCHS tCHD Parameter Min. Pulse Width During Self Refresh Cycle Precharge Time During Self Refresh Cycle Hold Time From Rising During Self Refresh Cycle Hold Time From Falling During Self Refresh Cycle Max. Min. Max. Units Notes
When using Self Refresh mode, following refresh operations must performed ensure proper DRAM operation: addresses being refreshed EVENLY DISTRIBUTED manner over refresh interval using refresh cycles, then only cycle must performed immediately after exit from Self Refresh. addresses being refreshed other manner (ROR- Distributed/Burst; CBR-Burst) over refresh interval, then full refreshes must performed immediately before entry immediately after exit from Self Refresh. tRASS tCHD (min) then tCHD applies. tRASS tCHD (min) then tCHS applies.
Refresh
Symbol Parameter Min. tREF 2048 cycles. version Refresh Period version Max. Min. Max. Units Notes
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Read Cycle
tRAS tCSH tRCD tRAD tCAL tASR tRAH Address tRCH tRCS tRRH Column tASC tCAH tRAL tCAS tRSH tCRP
tDZC tCLZ DOUT Hi-Z tRAC "H": tDZO
tOEA
tCDD tOED Hi-Z tCAC tOEZ tOFF
Valid Data tOHO
Hi-Z
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Write Cycle (Early Write)
tRAS tCSH tRCD tRAD tASR tRAH Address Column tASC tCAH tCAS tRSH tCRP
tWCS
tWCH
Valid Data
DOUT Hi-Z
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Write Cycle (Delayed Write)
tRAS tCSH tRCD tRAD tASR tRAH Address tRCS tRWL tOED tDZO tDZC Hi-Z tOEZ tCLZ DOUT Hi-Z tOEA Hi-Z Valid Data tOEH tCWL Column tASC tCAH tCAS tRSH tCRP
tOEH greater than equal tCWL
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Read-Modify-Write Cycle
tRWC tRAS tRCD tASR tRAH Address tCWD tAWD tRWD tRCS tOEH tDZC tDZO Hi-Z tCAC tCLZ DOUT Hi-Z tRAC tOHO tOEH greater than equal tCWL DOUT Hi-Z tOED tOEZ tOEA tRWL tCWL Column tRAD tASC tCAH tCSH tRSH tCAS tCRP
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Fast Page Mode Read Cycle
tRASP tRCD tCSH tASR tRAH Address tRAD tOEA tOHO tDZC tDZO tDZO tRAC tCLZ DOUT
DOUT Column Column Column
tCPRH
tCAS tCAS
tRSH tCAS tCAL
tCRP
tASC
tCAH
tASC
tRAL tCAH tASC tCAH
tRCS tRCH tRCH
tRCS
tRCH
tRRH tCPA tOEA tCPA tOEA
tOHO tDZC
tDZC
tOHO tCDD tOED
tDZO tOED tCAC
tOED tCAC tOFF tOEZ tCLZ
tCAC tOFF tOEZ tCLZ
DOUT DOUT
tOFF tOEZ
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Fast Page Mode Write Cycle
tRASP tRCD tCSH tASR tRAH Address tRAD tCWL tWCH tWCS DOUT Hi-Z
Column Column Column
tCAS
tRSH tCAS
tCRP
tASC
tCAH
tASC
tCAH
tASC
tCAH
tCWL
tCWL tRWL
tWCH tWCS tWCS
tWCH
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Fast Page Mode Read-Modify-Write Cycle
tRASP tPRWC tRCD tCSH tASR Address
Column Column Column
tCAS tCAS tCWL tCAH tCWL tASC tCAH
tRSH tCAS tCWL
tCRP
tRAH
tASC
tASC
tCAH
tRWL
tRWD tAWD tRCS tRAD tOEA tCAC tCWD
tRCS
tCPW tAWD tCWD tCAC
tRCS
tCPW tAWD tCWD tCAC
tCPA
tCPA
tOEH tOEA tDZC tOED tOEZ tOHO tCLZ tOEZ tOHO tOED
tOEH tOEA tOED tOEZ tOHO tCLZ
tOEH
tCLZ DOUT tRAC DOUT DOUT DOUT tOEH greater than equal tCWL
Hi-Z
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Only Refresh Cycle
tRAS tRPC tASR tRAH Address tCRP
DOUT Hi-Z
NOTE:
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Before Refresh Cycle
tRAS tRPC tCSR tWRH tWRP tWRP tWRH tCSR
tOED tCDD tOEZ tOFF Hi-Z Hi-Z
DOUT
NOTE: Address
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Hidden Refresh Cycle (Read)
tRAS tRCD tRAD tASR tRAH Address tRCS tRRH Column tASC tCAH tRAL tWRH tWRP tRSH tCHR tCRP tRAS
tDZC tDZO
tOEA
tCDD tOED Hi-Z tCAC tCLZ tOFF tOEZ
DOUT Hi-Z tRAC tOHO Valid Data Hi-Z
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Hidden Refresh Cycle (Write)
tRAS tRCD tCHR tCRP tRAS
tASR tRAH Address
tASC tCAH
Column tWCS tWCH tWRH
Valid Data
DOUT Hi-Z
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Self Refresh Cycle (Sleep Mode) Power version only
tRASS tRPC tCSR tWRH tWRP tCHD tCHS tCRP tRPS
tOFF
DOUT
Hi-Z
NOTES:
Address Once (min) provided remains low, DRAM will Self Refresh, commonly known "Sleep Mode." tRASS tCHD (min) then tCHD applies. tRASS tCHD (min) then tCHS applies.
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Package Dimensions (300mil; 26/24 lead; Small Outline J-Lead)
3.50 0.25 2.083 17.145 0.127 0.76
7.620 0.127
8.547 Basic
6.858 Basic
Lead 0.200
0.054 0.022
Seating Plane
0.10 1.27 Basic 0.123 0.690 0.030 0.088 0.420 0.014
NOTE: dimensions millimeters; Packages diagrams drawn scale.
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Package Dimensions (300mil 26/24 lead; Thin Small Outline Package)
17.14
0.10
Detail
7.62 0.10
9.22 0.20
Lead
0.125
0.075 0.005
Seating Plane
0.10 1.27 Basic 0.40
0.10
0.95
Detail
1.20 1.00 0.05 0.25 Basic Gage Plane
+0.10 0.05 -0.00
NOTE: dimensions millimeters; Package diagrams drawn scale.
43G9649 SA14-4201-07 Revised 4/97
©IBM Corporation. rights reserved. further subject provisions this document.
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IBM0117400 IBM0117400M IBM0117400B IBM0117400P 11/11 DRAM
Revision
Revision 05/18/94 Initial Release Iout changed +2.0 -2.0 Electrical Characteristics table. Packaging diagrams modified clarify lead thickness standoff height. tRPC changed from 5ns. tCHR changed from 10ns. Currents Electrical Characteristics table revised. Test Modes Test Circuit Diagram removed. 12/10/95 Rename tODD tOED. tOED, tCDD, tOEZ, tOFF changed from 15ns, 70ns part. tRRH changed from speed sorts. tOEH changed from 15ns 70ns part. tCSR changed from speed sorts. tCAHmin changed from 10ns 70ns parts. tOFF changed from 15ns 70ns parts. Power Standard Power Specifications were combined. 43G9648 43G9649 were combined into 43G9649. Added part numbers. reduced from 15ns 12ns speed sort. 12/10/95 tCHD added Self Refresh Cycle with value 350µs speed sorts. Self Refresh timing diagram changed allow high tCHD (350µs) after falls entering Self Refresh. timing diagram changed allow remain back-to-back cycles. Hidden Refresh Write cycle Truth Table changed from 08/06/96 Changed Refresh Rate from 256ms 128ms, version only. None diagrams were changed. ICC2 changed from 1mA. II(L) IO(L) were altered from 10uA 5uA. 09/01/96 initially 30ns. been modified 50ns speed sorts. tCPA decreased from 30ns 28ns speed sort. tRASP 125K raised 200K speed sorts. changed from 35ns 30ns speed sort. Hidden Refresh Write cycle Truth Table changed from "LH". tOED moved from Common Parameters table Write Cycle Parameters Table. tODD before timing diagram renamed tOED. speed sort timings were removed. 03/19/97 Icc1, Icc3, Icc6 speed sort were reduced from 95mA 70mA. Icc4 speed sort reduced from 75mA 25mA. Icc1, Icc3, Icc6 speed sort were reduced from 85mA 60mA. Icc4 speed sort reduced from 65mA 25mA. 04/23/97 Icc5 changed from 200µA 100µA Power Parts. Contents Modification
©IBM Corporation. rights reserved. further subject provisions this document.
43G9649 SA14-4201-07 Revised 4/97
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International Business Machines Corp.1997
Printed United States America rights reserved
logo registered trademarks Corporation.
This document contain preliminary information subject change without notice. assumes responsibility liability information contained herein. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. products described this document intended implantation other direct life support applications where malfunction result direct physical harm injury persons. WARRANTIES KIND, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE, OFFERED THIS DOCUMENT.
more information contact your Microelectronics sales representative visit World Wide http://www.chips.ibm.com
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SA14-4201-07

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