74HC/HCT4017 Johnson decade counter with decoded outputs Product
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IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications IC06 74HC/HCT/HCU/HCMOS Logic Package Information IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4017 Johnson decade counter with decoded outputs
Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
FEATURES Output capability: standard category: GENERAL DESCRIPTION 74HC/HCT4017 high-speed Si-gate CMOS devices compatible with "4017" "4000B" series. They specified compliance with JEDEC standard 74HC/HCT4017 5-stage Johnson decade counters with decoded active HIGH outputs Q9), active output from most significant flip-flop (Q5-9), active HIGH active clock inputs (CP0
74HC/HCT4017
CP1) overriding asynchronous master reset input (MR). counter advanced either LOW-to-HIGH transition while HIGH-to-LOW transition while HIGH (see also function table). When cascading counters, Q5-9 output, which while counter states used drive input next counter. HIGH resets counter zero Q5-9 HIGH; LOW) independent clock inputs (CP0 CP1). Automatic code correction counter provided internal circuit: following illegal code counter returns proper counting mode within clock pulses.
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/ tPLH fmax Notes used determine dynamic power dissipation µW): VCC2 VCC2 where: input frequency output frequency VCC2 outputs output load capacitance supply voltage condition condition ORDERING INFORMATION "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP0, maximum clock frequency input capacitance power dissipation capacitance package notes CONDITIONS UNIT
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
DESCRIPTION SYMBOL Q5-9 NAME FUNCTION decoded outputs ground carry output (active LOW)
74HC/HCT4017
clock input (HIGH-to-LOW, edge-triggered) clock input (LOW-to-HIGH, edge-triggered) master reset input (active HIGH) positive supply voltage
Fig.1 configuration.
Fig.2 Logic symbol.
Fig.3 logic symbol.
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
74HC/HCT4017
Fig.4 Functional diagram.
FUNCTION TABLE Notes HIGH voltage level voltage level don't care LOW-to-HIGH clock transition HIGH-to-LOW clock transition OPERATION Q5-9 counter advances counter advances change change change change
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
74HC/HCT4017
Fig.5 Logic diagram.
Fig.6 Timing diagram.
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
CHARACTERISTICS 74HC characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category:
74HC/HCT4017
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
CHARACTERISTICS 74HC Tamb (°C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay propagation delay Q5-9 propagation delay propagation delay Q5-9 propagation delay Q1-9 propagation delay Q5-9, output transition time clock pulse width HIGH master reset pulse width; HIGH removal time CP0, set-up time CP0; hold time CP1; maximum clock pulse frequency typ. to+85 max. min. max. to+125 min. max.
74HC/HCT4017
TEST CONDITIONS UNIT WAVEFORMS Fig.9
tPHL/ tPLH
Fig.9
tPHL/ tPLH
Fig.9
tPHL/ tPLH
Fig.9
tPHL
Fig.8
tPLH
Fig.8
tTHL/ tTLH
Fig.9
Fig.8
Fig.8
trem
Fig.8
Fig.7
Fig.7
fmax
Fig.8
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
CHARACTERISTICS 74HCT characteristics "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard category:
74HC/HCT4017
Note types value additional quiescent supply current (ICC) unit load given family specifications. determine input, multiply this value unit load coefficient shown table below. INPUT UNIT LOAD COEFFICIENT 0.40 0.25 0.50
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
CHARACTERISTICS 74HCT Tamb (°C) 74HCT SYMBOL PARAMETER
min. typ. max.
74HC/HCT4017
TEST CONDITIONS UNIT WAVEFORMS
to+85
min. max.
to+125
min. max.
tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL/ tPLH tPHL tPLH tTHL/ tTLH trem
propagation delay propagation delay Q5-9 propagation delay propagation delay Q5-9 propagation delay Q1-9 propagation delay Q5-9, output transition time clock pulse width HIGH master reset pulse width; HIGH removal time CP0, set-up time CP0; hold time CP1;
Fig.9 Fig.9 Fig.9 Fig.9 Fig.8 Fig.8 Fig.9 Fig.8 Fig.8 Fig.8 Fig.7
Fig.7
fmax
maximum clock pulse frequency
Fig.8
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
WAVEFORMS
74HC/HCT4017
50%; VCC. HCT:
Fig.7 Waveforms showing hold set-up times CP0.
Conditions: while triggered LOW-to-HIGH transition HIGH, while triggered HIGH-to-LOW transition. 50%; VCC. HCT:
Fig.8
Waveforms showing minimum pulse widths CP0, inputs; recovery time propagation delays Q5-9 outputs.
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
74HC/HCT4017
Conditions: while triggered LOW-to-HIGH transition HIGH, while triggered HIGH-to-LOW transition. 50%; VCC. HCT:
Fig.9 Waveforms showing propagation delays CP0, Q5-9 outputs output transition times.
December 1990
Philips Semiconductors
Product specification
Johnson decade counter with decoded outputs
APPLICATION INFORMATION Some applications "4017" are: Decade counter with decimal decoding decoding counter (when cascaded) Sequential controller Timer
74HC/HCT4017
Figure shows technique extending number decoded output states "4017". Decoded outputs sequential within each stage from stage stage, with dead time (except propagation delay).
essential enable counter when HIGH, when LOW, this would cause extra count.
Fig.10 Counter expansion
Figure shows example divide-by through divide-by circuit using "4017". Since "4017" asynchronous reset, output pulse widths narrow (minimum expected pulse width ns). output pulse widths enlarged inserting network input.
Fig.11 Divide-by through divide-by
PACKAGE OUTLINES "74HC/HCT/HCU/HCMOS Logic Package Outlines".
December 1990
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