10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference S

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10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference S

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19-4802; 9/04
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference
Single 3.3V Operation Excellent Dynamic Performance 58.5dB 20MHz 72dBc SFDR 20MHz Power 62mA (Normal Operation) (Shutdown Mode) Fully Differential Analog Input Wide 2Vp-p Differential Input Voltage Range 400MHz -3dB Input Bandwidth On-Chip 2.048V Precision Bandgap Reference CMOS-Compatible Three-State Outputs 32-Pin TQFP Package Evaluation Available (MAX1448 Kit)
MAX1449
MAX1449 3.3V, 10-bit analog-to-digital converter (ADC) features fully differential input, pipelined 10stage architecture with wideband track-and-hold (T/H), digital error correction incorporating fully differential signal path. optimized lowpower, high-dynamic performance imaging digital communications applications. converter operates from single 2.7V 3.6V supply, consuming only 186mW while delivering 58.5dB (typ) signal-to-noise ratio (SNR) 20MHz input frequency. fully differential input stage -3dB 400MHz bandwidth operated with single-ended inputs. addition operating power, MAX1449 features power-down mode idle periods. internal 2.048V precision bandgap reference used ADC's full-scale range. flexible reference structure allow's user supply buffered, direct, externally derived reference applications requiring increased accuracy different input voltage range. Lower speed, pin-compatible versions MAX1449 also available. Refer MAX1444 data sheet 40Msps version, MAX1446 data sheet 60Msps version, MAX1448 data sheet 80Msps. MAX1449 parallel, offset binary, CMOS-compatible, three-state outputs that operated from 1.7V 3.6V allow flexible interfacing. device available 32-pin TQFP package specified over extended industrial (-40°C +85°C) temperature range.
Ordering Information
PART MAX1449EHJ TEMP RANGE -40°C +85°C PIN-PACKAGE TQFP
Pin-Compatible, Lower Speed Selection Table
PART MAX1444 MAX1446 MAX1448 SAMPLING SPEED (Msps)
_Applications
Ultrasound Imaging Imaging Baseband Digitization Digital Set-Top Boxes Video Digitizing Applications
Functional Diagram
MAX1449 CONTROL
PIPELINE
OUTPUT DRIVERS
D9-D0
SYSTEM BIAS
OVDD OGND
Configuration appears data sheet.
REFOUT REFIN REFP REFN
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD .-0.3V +3.6V OGND GND.-0.3V +0.3V IN+, GND.-0.3V REFIN, REFOUT, REFP, REFN, GND.-0.3V (VDD 0.3V) GND.-0.3V (VDD 0.3V) D9-D0 GND.-0.3V (OVDD 0.3V) Continuous Power Dissipation +70°C) 32-Pin TQFP (derate 18.7mW/°C above +70°C).1495.3mW Operating Temperature Range .-40°C +85°C Junction Temperature .+150°C Storage Temperature Range .-60°C +150°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD 3.3V, OVDD 0.1µF capacitors from REFP, REFN, GND, VREFIN 2.048V, REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs, fCLK 105MHz, TMIN TMAX, unless otherwise noted. +25°C guaranteed production test, +25°C guaranteed design characterization; typical values +25°C.)
PARAMETER ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT Input Differential Range Common-Mode Voltage Range Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS (fCLK 105.26MHz, 4096-point FFT) 7.5MHz Signal-to-Noise Ratio 20MHz (Note 50MHz Signal-to-Noise Distortion Harmonic) (Note 7.5MHz SINAD 20MHz 50MHz Spurious-Free Dynamic Range (Note 7.5MHz SFDR 20MHz 50MHz 55.9 55.5 55.3 54.5 fCLK 58.5 58.5 58.2 58.1 57.6 Cycles VDIFF VCOM Switched capacitor load Differential single-ended inputs ±1.0 VDD/2 +25°C, +25°C 7.5MHz, +25°C 7.5MHz, missing codes guaranteed, +25°C ±0.75 ±0.5 ±2.4 ±1.0 ±1.7 Bits SYMBOL CONDITIONS UNITS
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V, OVDD 0.1µF capacitors from REFP, REFN, GND, VREFIN 2.048V, REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs, fCLK 105MHz, TMIN TMAX, unless otherwise noted. +25°C guaranteed production test, +25°C guaranteed design characterization; typical values +25°C.)
PARAMETER Third-Harmonic Distortion (Note Intermodulation Distortion (First Odd-Order IMDs) (Note Third-Order Intermodulation Distortion (Note Total Harmonic Distortion (First Harmonics) (Note Small-Signal Bandwidth Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time Differential Gain Differential Phase Output Noise INTERNAL REFERENCE Reference Output Voltage Reference Temperature Coefficient Load Regulation BUFFERED EXTERNAL REFERENCE (VREFIN 2.048V) REFIN Input Voltage Positive Reference Output Voltage Negative Reference Output Voltage Common-Mode Level Differential Reference Output Voltage Range REFIN Resistance VREFIN VREFP VREF VREFP VREFN, +25°C 0.98 2.048 2.012 0.988 1.024 1.07 REFOUT TCREF 2.048 1.25 ppm/°C mV/mA FPBW full-scale input SYMBOL 7.5MHz 20MHz 50MHz 38MHz -6.5dB 42MHz -6.5dB 38MHz -6.5dB 42MHz -6.5dB 7.5MHz 20MHz 50MHz Input -20dB differential inputs Input -0.5dB differential inputs CONDITIONS UNITS
±0.25
psRMS Degrees LSBRMS
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V, OVDD 0.1µF capacitors from REFP, REFN, GND, VREFIN 2.048V, REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs, fCLK 105MHz, TMIN TMAX, unless otherwise noted. +25°C guaranteed production test, +25°C guaranteed design characterization; typical values +25°C.)
PARAMETER Maximum REFP, Source Current Maximum REFP, Sink Current Maximum REFN Source Current Maximum REFN Sink Current SYMBOL VREFN VCOM ISOURCE ISINK RREFP, RREFN VREF VCOM VREFP VREFN VREF VREFP VREFN Measured between REFP REFN CONDITIONS -250 UNITS
UNBUFFERED EXTERNAL REFERENCE (VREFIN AGND, reference voltage applied REFP, REFN, COM) REFP, REFN Input Resistance REFP, REFN, Input Capacitance Differential Reference Input Voltage Range Input Voltage Range REFP Input Voltage REFN Input Voltage DIGITAL INPUTS (CLK, Input High Threshold Input Threshold Input Hysteresis Input Leakage Input Capacitance VHYST OVDD 1.024 ±10% ±10% VCOM+ VREF VCOMVREF
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD 3.3V, OVDD 0.1µF capacitors from REFP, REFN, GND, VREFIN 2.048V, REFOUT connected REFIN through resistor, 2VP-P (differential with respect COM), 10pF digital outputs, fCLK 105MHz, TMIN TMAX, unless otherwise noted. +25°C guaranteed production test, +25°C guaranteed design characterization; typical values +25°C.)
PARAMETER DIGITAL OUTPUTS (D9-D0) Output Voltage Output Voltage High Three-State Leakage Current Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Output Supply Voltage Analog Supply Current SYMBOL ILEAK COUT ISINK 200µA ISOURCE 200µA OVDD OVDD OVDD CONDITIONS UNITS
MAX1449
OVDD IVDD Operating, 20MHz -0.5dB Shutdown, clock idle, OVDD Operating, 15pF 20MHz -0.5dB Shutdown, clock idle, OVDD Offset Gain Figure (Note Figure Figure Figure clock period 9.52ns Figure clock period 9.52ns (Note
±0.1 ±0.1 4.76 ±0.47 4.76 ±0.47
Output Supply Current
IOVDD
mV/V
Power Supply Rejection TIMING CHARACTERISTICS Rise-to-Output Data Valid Fall-to-Output Enable Rise-to-Output Disable Pulse Width High Pulse Width Wake-Up Time
PSRR
tENABLE tDISABLE tWAKE
Note SNR, SINAD, THD, SFDR, based analog input voltage -0.5dB referenced 1.024V full-scale input voltage range. Note Intermodulation distortion total power intermodulation products relative individual carrier. This number better referenced two-tone envelope. Note Digital outputs settle VIH,VIL. Note With REFIN driven externally, REFP, COM, REFN left floating while powered down.
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Typical Operating Characteristics
(VDD 3.3V, OVDD 2.0V, internal reference, differential input -0.5dB fCLK 106.2345MHz, 10pF, +25°C, unless otherwise noted.)
PLOT (fIN 7.5MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1449 toc01
PLOT (fIN 19.99MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
MAX1449 toc02
PLOT (fIN 50.12MHz, 8192-POINT FFT, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 HARMONIC HARMONIC 57.9dB SINAD 56.7dB -71.3dBc SFDR 71.1dBc
MAX1449 toc03
AMPLITUDE (dB) -100 HARMONIC HARMONIC 58.6dB SINAD 58.4dB -72.7dBc SFDR 73.6dBc
AMPLITUDE (dB) -100
58.5dB SINAD 58.4dB -73.7dBc SFDR 75.9dBc HARMONIC HARMONIC
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
PLOT (fIN 7.5MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
MAX1449 toc04
PLOT (fIN 19.99MHz, 8192-POINT FFT, SINGLE-ENDED INPUT)
AMPLITUDE (dB) -100 HARMONIC HARMONIC 57.7dB SINAD 57.2dB -67dBc SFDR 67.7dBc
MAX1449 toc05
TWO-TONE INTERMODULATION (8192-POINT IMD, DIFFERENTIAL INPUT)
AMPLITUDE (dB) -100 ANALOG INPUT FREQUENCY (MHz) 3RD-ORDER 2ND-ORDER 38MHz -6.5dB 42MHz -6.5dB
MAX1449 toc06
AMPLITUDE (dB) -100 HARMONIC HARMONIC 57.7dB SINAD 57.5dB -71.8dBc SFDR 74.4dBc
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT FREQUENCY
MAX1449 toc07
SIGNAL-TO-NOISE RATIO ANALOG INPUT FREQUENCY
MAX1449 toc08
TOTAL HARMONIC DISTORTION ANALOG INPUT FREQUENCY
MAX1449 toc09
DIFFERENTIAL SFDR (dBc)
DIFFERENTIAL SINGLE ENDED
SINGLE ENDED
SINGLE ENDED
(dBc)
(dB)
DIFFERENTIAL
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Typical Operating Characteristics (continued)
(VDD 3.3V, OVDD 2.0V, internal reference, differential input -0.5dB fCLK 106.2345MHz, 10pF, +25°C, unless otherwise noted.)
SIGNAL-T0-NOISE DISTORTION ANALOG INPUT FREQUENCY
MAX1449 toc10
FULL-POWER INPUT BANDWIDTH ANALOG INPUT FREQUENCY, SINGLE ENDED
MAX1449 toc11
SMALL-SIGNAL INPUT BANDWIDTH ANALOG INPUT FREQUENCY, SINGLE ENDED
100mVp-p
MAX1449 toc12
DIFFERENTIAL
AMPLITUDE (dB)
SINAD (dB)
1000 1000 ANALOG INPUT FREQUENCY (MHz) ANALOG INPUT FREQUENCY (MHz)
SINGLE-ENDED
ANALOG INPUT FREQUENCY (MHz)
SPURIOUS-FREE DYNAMIC RANGE ANALOG INPUT POWER (fIN 19MHz)
MAX1449 toc13
SIGNAL-TO-NOISE RATIO ANALOG INPUT POWER (fIN 19MHz)
MAX1449 toc14
TOTAL HARMONIC DISTORTION ANALOG INPUT POWER (fIN 19MHz)
MAX1449 toc15
SFDR (dBc) ANALOG INPUT POWER
(dBc)
(dB)
ANALOG INPUT POWER ANALOG INPUT POWER
SIGNAL-TO-NOISE DISTORTION ANALOG INPUT POWER (fIN 19MHz)
MAX1449 toc16
SPURIOUS-FREE DYNAMIC RANGE TEMPERATURE
MAX1449 toc17
SIGNAL-TO-NOISE TEMPERATURE
26.1696MHz
MAX1449 toc18
26.1696MHz SFDR (dBc)
SINAD (dB)
(dB)
ANALOG INPUT POWER
TEMPERATURE (°C)
TEMPERATURE (°C)
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Typical Operating Characteristics (continued)
(VDD 3.3V, OVDD 2.0V, internal reference, differential input -0.5dB fCLK 106.2345MHz, 10pF, +25°C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION TEMPERATURE
MAX1449 toc19
SIGNAL-TO-NOISE DISTORTION TEMPERATURE
MAX1449 toc20
INTEGRAL NONLINEARITY DIGITAL OUTPUT CODE (BEST STRAIGHT LINE)
(LSB)
MAX1449 toc21
26.1696MHz
26.1696MHz SINAD (dB)
(dBc)
-0.1
-0.2 -0.3
TEMPERATURE (°C)
TEMPERATURE (°C)
-0.4 1000 1200 DIGITAL OUTPUT CODE
DIFFERENTIAL NONLINEARITY DIGITAL OUTPUT CODE
MAX1449 toc22
(LSB) -0.1 -0.2 -0.3 -0.4 1000
GAIN ERROR TEMPERATURE, EXTERNAL REFERENCE, VREFIN +2.048V
MAX1449 toc23
OFFSET ERROR TEMPERATURE, EXTERNAL REFERENCE, VREFIN +2.048V
MAX1449 toc24
0.10
OFFSET ERROR (LSB)
0.08 GAIN ERROR (LSB) 1200
0.06
0.04
0.02
TEMPERATURE (°C)
DIGITAL OUTPUT CODE
TEMPERATURE (°C)
ANALOG SUPPLY CURRENT ANALOG SUPPLY VOLTAGE
MAX1449 toc25
ANALOG SUPPLY CURRENT TEMPERATURE
MAX1449 toc26
DIGITAL SUPPLY CURRENT TEMPERATURE
MAX1449 toc27
IVDD (mA) 2.70 2.85 3.00 3.15 3.30 3.45
IOVDD (mA)
IVDD (mA)
TEMPERATURE (°C) TEMPERATURE (°C)
3.60
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Typical Operating Characteristics (continued)
(VDD 3.3V, OVDD 2.0V, internal reference, differential input -0.5dB fCLK 106.2345MHz, 10pF, +25°C, unless otherwise noted.)
DIGITAL SUPPLY CURRENT TEMPERATURE
MAX1449 toc28
ANALOG POWER-DOWN CURRENT ANALOG SUPPLY VOLTAGE
MAX1449 toc29
DIGITAL POWER-DOWN CURRENT DIGITAL SUPPLY VOLTAGE
MAX1449 toc30
3.00
IOVDD (mA) IVDD (µA)
2.80
IOVDD (µA) 2.70 2.85 3.00 3.15 3.30 3.45 3.60
2.60
2.40
2.20
TEMPERATURE (°C)
2.00
OVDD
SNR/SINAD, THD/SFDR CLOCK FREQUENCY
50.123MHz SNR/SINAD, THD/SFDR (dB, dBc) 2.025 CLOCK FREQUENCY (MHz) SINAD VREFOUT 2.050 SFDR
MAX1449 toc31
INTERNAL REFERENCE VOLTAGE ANALOG SUPPLY VOLTAGE
MAX1449 toc32
2.100
2.075
2.000 2.70 2.85 3.00 3.15 3.30 3.45 3.60
INTERNAL REFERENCE VOLTAGE TEMPERATURE
MAX1449 toc33
OUTPUT NOISE HISTOGRAM INPUT)
64676
MAX1449 toc34
2.10
70,000 60,000 50,000
2.08 VREFOUT
COUNTS
2.06
40,000 30,000 20,000
2.04
2.02 10,000 2.00 TEMPERATURE (°C)
DIGITAL OUTPUT CODE
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Description
NAME REFN INCLK FUNCTION Lower Reference. Conversion range ±(VREFP VREFN). Bypass with 0.1µF capacitor. Common-Mode Voltage Output. Bypass with 0.1µF capacitor. Analog Supply Voltage. Bypass with capacitor combination 2.2µF parallel with 0.1µF. Analog Ground Positive Analog Input. single-ended operation connect signal source IN+. Negative Analog Input. single-ended operation connect COM. Conversion Clock Input Power Down Input. High: Power-down mode Low: Normal operation Output Enable Input. High: Digital outputs disabled Low: Digital outputs enabled Three-State Digital Outputs D9-D5. MSB. Output Driver Supply Voltage. Bypass with capacitor combination 2.2µF parallel with 0.1µF. Test Point. connect. Output Driver Ground Three-State Digital Outputs D4-D0. LSB. Internal Reference Voltage Output. connected REFIN through resistor resistordivider. Reference Input. VREFIN (VREFP VREFN). Bypass with 0.1µF capacitor. Upper Reference. Conversion range ±(VREFP VREFN). Bypass with 0.1µF capacitor.
16-20 24-28
D9-D5 OVDD T.P. OGND D4-D0 REFOUT REFIN REFP
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference
Detailed Description
MAX1449 uses 10-stage, fully differential, pipelined architecture (Figure that allows highspeed conversion while minimizing power consumption. Each sample moves through pipeline stage every half-clock cycle. Counting delay through output latch, clock-cycle latency 5.5. 1.5-bit (2-comparator) flash converts held input voltage into digital code. following digitalto-analog converter (DAC) converts digitized result back into analog voltage, which then subtracted from original held input signal. resulting error signal then multiplied two, product passed along next pipeline stage where process repeated until signal been processed stages. Each stage provides 1bit resolution. Digital error-correction compensates comparator offsets each pipeline stage ensures missing codes. open simultaneously with sampling input waveform. Switches then opened before switches connect capacitors output amplifier switch closed. resulting differential voltage held capacitors C2b. amplifier used charge capacitors same values originally held C2b. This value then presented first stage quantizer isolates pipeline from fast-changing input. wide input bandwidth amplifier allows MAX1449 track sample/hold analog inputs high frequencies beyond Nyquist. analog inputs driven either differentially single-ended. recommended match impedance common-mode voltage mid-supply (VDD/2) optimum performance.
MAX1449
Analog Input Reference Configuration
full-scale range MAX1449 determined internally generated voltage difference between REFP (VDD/2 VREFIN/4) REFN (VDD/2 VREFIN/4). ADC's full-scale range user-adjustable through REFIN pin, which provides high input impedance this purpose. REFOUT, REFP, (VDD/2), REFN internally buffered low-impedance outputs.
INTERNAL BIAS
Input Track-and-Hold (T/H) Circuit
Figure displays simplified functional diagram input track-and-hold (T/H) circuit both track hold mode. track mode, switches S2a, S2b, S4a, S4b, S5a, closed. fully differential circuit samples input signal onto capacitors through switches S4b. Switches common mode amplifier input,
MDAC VOUT
FLASH BITS INS4b STAGE STAGE STAGE INTERNAL BIAS TRACK HOLD TRACK
DIGITAL CORRECTION LOGIC D9-D0 INPUT VOLTAGE BETWEEN (DIFFERENTIAL SINGLE ENDED)
INTERNAL HOLD NONOVERLAPPING CLOCK SIGNALS
Figure Pipelined Architecture-Stage Blocks
Figure Internal Circuit
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
MAX1449 provides three modes reference operation: Internal reference mode Buffered external reference mode Unbuffered external reference mode internal reference mode, internal reference output REFOUT tied REFIN through resistor (e.g., 10k) resistor-divider, application requires reduced full-scale range. stability purposes recommended bypass REFIN with >10nF capacitor GND. buffered external reference mode, reference voltage levels adjusted externally applying stable accurate voltage REFIN. this mode, REFOUT left open connected REFIN through >10k resistor. unbuffered external reference mode, REFIN connected thereby deactivating on-chip buffers REFP, COM, REFN. With their buffers shut down, these pins become high impedance driven external reference sources. Clock jitter especially critical undersampling applications. clock input should always considered analog input routed away from analog input other digital signal lines. MAX1449 clock input operates with voltage threshold VDD/2. Clock inputs with duty cycle other than must meet specifications high periods stated Electrical Characteristics. (See Figures (3a, (4a, relationship between spurious-free dynamic range (SFDR), signal-to-noise ratio (SNR), total harmonic distortion (THD), signal-to-noise plus distortion (SINAD) duty cycle.)
Output Enable Power Down (PD), Output Data (D0-D9)
data outputs, (LSB) through (MSB), TTL/CMOS logic-compatible. There clock-cycle latency between particular sample valid output data. output coding straight offset binary (Table With high, digital outputs enter high-impedance state. held with high, outputs latched last value prior power down. capacitive load digital outputs through should kept possible (<15pF), avoid large digital currents that could feed back into analog portion MAX1449, thereby degrading dynamic performance. buffers digital outputs further isolate digital outputs from heavy capacitive loads. further improve dynamic performance MAX1449, small series resistors (e.g., 100) added digital output paths, close ADC. Figure displays timing relationship between output enable data output valid well power-down/wake-up data output valid.
Clock Input (CLK)
MAX1449's input accepts CMOS-compatible clock signals. Since inter-stage conversion device depends repeatability rising falling edges external clock, clock with jitter fast rise fall times (<2ns). particular, sampling occurs falling edge clock signal, mandating this edge provide lowest possible jitter. significant aperture jitter would limit performance follows: where represents analog input frequency time aperture jitter.
Table MAX1449 Output Code Differential Inputs
DIFFERENTIAL INPUT VOLTAGE* VREF 511/512 VREF 510/512 VREF 1/512 VREF 1/512 VREF 511/512 VREF 512/512 DIFFERENTIAL INPUT +Full Scale -1LSB +Full Scale -2LSB +1LSB Bipolar Zero -1LSB Negative Full Scale 1LSB Negative Full Scale STRAIGHT OFFSET BINARY 1111 1111 1111 1110 0000 0001 0000 0000 1111 1111 0000 0001 0000 0000
*VREF VREFP VREFN
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
25.123MHz -0.5dB SFDR (dBc) (dBc) CLOCK DUTY CYCLE CLOCK DUTY CYCLE 25.123MHz -0.5dB
Figure Spurious Free Dynamic Range Clock Duty Cycle (Differential Input)
Figure Total Harmonic Distortion Clock Duty Cycle (Differential Input)
25.123MHz -0.5dB
SINAD (dB)
25.123MHz -0.5dB
(dB)
CLOCK DUTY CYCLE
CLOCK DUTY CYCLE
Figure Signal-to-Noise Ratio Clock Duty Cycle (Differential Input)
Figure Signal-to-Noise Plus Distortion Clock Duty Cycle (Differential Input)
tENABLE OUTPUT DATA D9-D0 HIGH-Z
tDISABLE HIGH-Z
VALID DATA
Figure Output Enable Timing
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
System Timing Requirements
Figure depicts relationship between clock input, analog input, data output. MAX1449 samples falling edge input clock. Output data valid rising edge input clock. output data internal latency clock cycles. Figure also determines relationship between input clock parameters valid output data.
Using Transformer Coupling
transformer (Figure provides excellent solution convert single-ended source signal fully differential signal, required MAX1449 optimum performance. Connecting center transformer provides VDD/2 level shift input. Although transformer shown, stepup transformer selected reduce drive requirements. reduced signal swing from input driver, such amp, also improve overall distortion. general, MAX1449 provides better SFDR with fully differential input signals than singleended drive, especially very high input frequencies. differential input mode, even-order harmonics lower both inputs (IN+, IN-) balanced, each inputs only requires half signal swing compared single-ended mode.
Applications Information
Figure depicts typical application circuit containing single-ended differential converter. internal reference provides VDD/2 output voltage level shifting purposes. input buffered then split voltage follower inverter. low-pass filter, suppress some wideband noise associated with high-speed amps, follows amps. user select RISO values optimize filter performance, suit particular application. application Figure RISO placed before capacitive load prevent ringing oscillation. 22pF capacitor acts small bypassing capacitor.
Single-Ended AC-Coupled Input Signal
Figure shows AC-coupled, single-ended application. MAX4108 provides high speed, high bandwidth, low-noise, low-distortion maintain integrity input signal.
CLOCK-CYCLE LATENCY
ANALOG INPUT
CLOCK INPUT
DATA OUTPUT
Figure System Output Timing Diagram
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
0.1µF LOWPASS FILTER MAX4108 0.1µF RISO 0.1µF 22pF
MAX1449
0.1µF 0.1µF INPUT 0.1µF MAX4108 0.1µF MAX4108 INRISO 0.1µF 22pF LOWPASS FILTER
Figure Typical Application Circuit Using Internal Reference
22pF 0.1µF N.C. 2.2µF 0.1µF
REFN 0.1µF RISO REFP
MAX1449
MAX4108 0.1µF
RISO
MAX1449
MINI-CIRCUITS ADT1-1WT IN22pF
RISO 22pF
INCIN
Figure Using Transformer AC-Coupling
Figure Single-Ended AC-Coupled Input
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
3.3V 0.1µF
3.3V N.C. 0.1µF 2.048V 0.1µF 16.2k 10Hz LOWPASS FILTER MAX4250 100µF 10Hz LOWPASS FILTER 0.1µF 0.1µF 0.1µF REFOUT REFIN REFP MAX1449
REFN
MAX6062
0.1µF N.C. 0.1µF 0.1µF 0.1µF 0.1µF
2.2µF
REFOUT REFIN REFP MAX1449
1000
REFN
NOTE: FRONT-END REFERENCE CIRCUIT DESIGN USED WITH 1000 ADCs.
Figure Buffered External Reference Drives 1000 ADCs
Buffered External Reference Drives Multiple ADCs
Multiple-converter systems based MAX1449 well suited with common reference voltage. REFIN those converters connected directly external reference source. precision bandgap reference like MAX6062 generates external level 2.048V (Figure 10), exhibits noise voltage density 150nV/Hz. output passes through 1-pole lowpass filter (with 10Hz cutoff fre16
quency) MAX4250, which buffers reference before output applied second 10Hz lowpass filter. MAX4250 provides offset voltage (for high-gain accuracy) noise level. passive 10Hz filter following buffer attenuates noise produced voltage reference buffer stages. This filtered noise density, which decreases higher frequencies, meets noise levels specified precision operation.
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
3.3V 0.1µF N.C. 2.0V 21.5k 3.3V
MAX4252
REFOUT REFIN REFP MAX1449
2.0V
REFN
MAX6066
21.5k
10µF 1.47k
330µF
0.1µF
0.1µF
0.1µF
1.5V
MAX4252
3.3V 1.5V
3.3V 0.1µF 21.5k MAX4254 POWER-SUPPLY BYPASSING. PLACE CAPACITOR CLOSE POSSIBLE AMP.
10µF 1.47k
330µF
1.0V
MAX4252
3.3V 1.0V -8mA 0.1µF N.C. 0.1µF 0.1µF 0.1µF 2.2µF
21.5k
10µF 1.47k 330µF REFOUT REFIN REFP MAX1449
21.5k
REFN
NOTE: FRONT-END REFERENCE CIRCUIT DESIGN USED WITH ADCs.
Figure Unbuffered External Reference Drives ADCs
Unbuffered External Reference Drives Multiple ADCs
Connecting each REFIN analog ground disables internal reference each device, allowing internal reference ladders driven directly external reference sources. Followed 10Hz lowpass filter precision voltage-divider (Figure 11), MAX6066 generates level 2.500V. buffered outputs this divider 2.0V, 1.5V, 1.0V, with accuracy that depends tolerance divider resistors. three voltages buffered MAX4252, which provides noise offset. individual voltage followers connected 10Hz lowpass filters, which fil-
both reference voltage amplifier noise level 3nV/Hz. 2.0V 1.0V reference voltages differential full-scale range associated ADCs 2VP-P. 2.0V 1.0V buffers drive ADC's internal ladder resistances between them. Note that common power supply active components removes concern regarding power-supply sequencing when powering down. With outputs MAX4252 matching better than 0.1%, buffers subsequent lowpass filters replicated support many ADCs. applications that require more than matched ADCs, voltage reference divider string common converters highly recommended.
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Grounding, Bypassing, Board Layout
MAX1449 requires high-speed board layout design techniques. Locate bypass capacitors close device possible, preferably same side ADC, using surface mount devices minimum inductance. Bypass VDD, REFP, REFN, with parallel 0.1µF ceramic capacitors 2.2µF bipolar capacitor GND. Follow same rules bypass digital supply (OVDD) OGND. Multi-layer boards with separated ground power planes produce highest level signal integrity. Consider split ground plane arranged match physical location analog ground (GND) digital output driver ground (OGND) ADC's package. ground planes should joined single point, such that noisy digital ground currents interfere with analog ground plane. ideal location this connection determined experimentally point along between ground planes, which produces optimum results. Make this connection with low-value, surface-mount resistor ferrite bead direct short. Alternatively, ground pins could share same ground plane, ground plane sufficiently isolated from noisy digital systems ground plane (e.g., downstream output buffer ground plane). Route high-speed digital signal traces away from sensitive analog traces. Keep signal lines short free turns.
Dynamic Parameter Definitions
Aperture Jitter Figure depicts aperture jitter (tAJ), which sample-to-sample variation aperture delay. Aperture Delay Aperture delay (tAD) time defined between falling-edge sampling clock instant when actual sample taken (Figure 12). Signal-to-Noise Ratio (SNR) waveform perfectly reconstructed from digital samples, theoretical maximum ratio fullscale analog input (RMS value) quantization error (residual error). ideal, theoretical minimum analog-to-digital noise caused quantization error only results directly from ADC's resolution Bits): SNR(MAX) 6.02 1.76 reality, there other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. computed taking ratio signal noise, which includes spectral components minus fundamental, first five harmonics, offset. Signal-to-Noise Plus Distortion (SINAD) SINAD computed taking ratio signal spectral components minus fundamental offset. Effective Number Bits (ENOB) ENOB specifies dynamic performance specific input frequency sampling rate. ideal ADC's error consists quantization noise only. ENOB computed from:
ENOB
Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity deviation values actual transfer function from straight line. This straight line either best straight-line line drawn between endpoints transfer function, once offset gain errors have been nullified. static linearity parameters MAX1449 measured using best straight-line method.
(SINAD 1.76)
6.02
Total Harmonic Distortion (THD) typically ratio first five harmonics input signal fundamental itself. This expressed (V22 where fundamental amplitude, through amplitudes 2nd- through 5th-order harmonics.
Differential Nonlinearity (DNL) Differential nonlinearity difference between actual step width ideal value 1LSB. error specification less than 1LSB guarantees missing codes monotonic transfer function.
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference
Configuration
REFOUT
MAX1449
VIEW
REFIN REFP ANALOG INPUT SAMPLED DATA (T/H) REFN TRACK HOLD TRACK
OGND T.P. OVDD
MAX1449
Figure Aperture Timing
INGND
Spurious-Free Dynamic Range (SFDR) SFDR ratio expressed decibels amplitude fundamental (maximum signal component) value next largest spurious component, excluding offset. Intermodulation Distortion (IMD) two-tone ratio expressed decibels either input tone worst 3rd-order higher) intermodulation products. individual input tone levels -6.5dB full scale their envelope -0.5dB full scale.
TQFP
Chip Information
TRANSISTOR COUNT: 5684 PROCESS: CMOS
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference MAX1449
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.) TQFP, 5x5x01.0.EPS
PACKAGE OUTLINE, TQFP, 5x5x1.0mm
21-0110
10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
MAX1449
PACKAGE OUTLINE, TQFP, 5x5x1.0mm
21-0110
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2004 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

10-Bit, 105Msps, Single 3.3V, Low-Power with Internal Reference S

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