16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM

Datasheet Thumbnail

Top Searches for this datasheet

M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
This document preliminary Target Spec. some contents subject change without notice.
PINCONFIGURATION (TOP VIEW) DQCl DQCu CC1# CC0# CMd# CMs# VddQ VccQ RAS# CAS# DTD#
DESCRIPTION
M5M4V16169DTP/RT 16M-bit Cached DRAM which integrates input registers, 1,048,576-word 16-bit dynamic memory array 1024- word 16-bit static array Cache memory (block size 8x16) onto single monolithic circuit. block data transfer between DRAM data transfer buffers (RB1/RB2/WB1/WB2) performed instruction cycle, fundamental advantage over conventional DRAM/SRAM cache. fabricated with high performance CMOS process, ideal large-capacity memory systems where high speed, power dissipation, cost essential. quadruple-layer polysilicon process combined with silicide double layer aluminum wiring technology, single-transistor dynamic storage stacked capacitor cell, six-transistor static storage cache cell provide high circuit density reduced costs.
70Pin TSOP Type 0.65mm Lead Pitch
Ad11 Ad10 DQ15 DQ14 DQ13 VccQ DQ12 DQ11 VccQ DQ10 ADF#
FEATURES
Type name
M5M4V16169TP/RT-7 M5M4V16169TP/RT-8 M5M4V16169TP/RT-10 M5M4V16169TP/RT-15 SRAM Access/cycle 5.6ns/7ns 6.4ns/8ns 8.0ns/10ns 8.0ns/15ns DRAM Access/cycle 49ns/70ns 56ns/80ns 60ns/90ns 75ns/120ns Power Dissipation (Typ) DRAM: SRAM: DRAM: SRAM: DRAM: SRAM: DRAM: SRAM:
Package code:70P3S-L Ad11 Ad10 DQ15 DQ14 DQ13 VccQ DQ12
70-pin,400-mil TSOP (type with 0.65mm lead pitch 23.49mm package length. Multiplexed DRAM address inputs reduced count higher system densities. Selectable output operation (transparent latched registered) using command register cycle. Single 3.3V 0.3V Power Supply. (3.3V 0.15V part) 2048 refresh cycles every 64ms (Ad0->Ad10). Programmable burst length (1,2,4,8) burst sequence (sequential,interleave) with latency. Synchronous design precise control with external clock (K). Output retention advanced mask clock (CMs#). inputs/outputs capacitance LVTTL compatible. Separate DRAM SRAM address inputs fast SRAM access. Page Mode capability. Auto Refresh capability. Self Refresh capability.
Master Clock Chip Select DRAM Clock Mask CMd# Addr. Strobe RAS# Column Addr. Strobe CAS# Data Transfer Direction DTD# DRAM Address SRAM Clock Mask CMs# CC0#,CC1# Control Clocks Write Enable Byte Control DQC(u/l) SRAM Address DQ11 Output Enable VccQ Data DQ10 Power Supply Power Supply VccQ Ground :Address Fetch clock ADF# This None-Connect. :Must Connect :Must Connect High ADF#
70Pin TSOP Type 0.65mm Lead Pitch
DQCl DQCu CC1# CC0# CMd# CMs# VccQ VccQ RAS# CAS# DTD#
Package code:70P3S-M
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
BLOCK DIAGRAM
Ad11 Ad10 Col.3-7
DRAM Address Input
VccQ
RAS#
(Row Address strobe)
0-11
Column Block Decoder
CAS#
(Column Address strobe)
DTD#
(Data Transfer Direction)
DRAM Array
Mask
CMd#
(Clock Mask DRAM)
DRAM KBuffer
Command (0-6)
Timing control
(Chip Select) (Master ClocK)
Sense Amplifier control Mask Read Buffer1
CMs#
(Clock Mask SRAM)
(Write Enable) (Control Clock
CC0# CC1#
(Control Clock
Mask Mask
SRAM Address input
WB2M
Read Buffer2 Write Buffer Write Buffer
WB1M
ADF#
(Address Fetch)
DQCu(Enable upper) DQCl(Enable lower) As3-9
As0-2
Col.Decoder
Buffer
1KBit SRAM Array
1Kx16=16K SRAM
Main Amp.
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 (Output Enable)
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
BLOCK DIAGRAM DRAM 1MX16
Ad3-7 Decode 8X16 Block
DRAM Decoder 8X16
8X16
Ad0-11 4096 Decode
Lower Byte Upper Byte Lower Byte Upper Byte
DQ0-7
DQ8-15
As0-2 1of8 Decode
As0-2 1of8Decode
Lower Byte Upper Byte
8X16
bits bits bits
Lower Byte Upper Byte
8X16 8X16 Block
8X16 bits
SRAM 1KX16
As0-2 1of8Decode
SRAM Decoder
Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
FUNCTION TRUTH TABLE
Mnemonic
SRAM
CMs# CC0# CC1# (u/l)
Previous
(SRAM address) Previous
DRAM
CMd# RAS# CAS# DTD#
(DRAM address)
CODE BRTR BWTW DNOP DWT1 DWT1R DWT2 DWT2R DWT3 DWT3R DWT4 DWT4R
As0-9 As0-9 As0-9 As3-9 As3-9
Ad0-11
Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad3-7 (Col.Block) Ad0-11 (Row Add.)
As0-9 As0-9 As0-2 As0-2
Command
NOTES function, RAS#, CAS# DTD# inputs DON'T CARE except L,L,H combination. (Respectively). unused addresses must Low. New: BWTW initiated same cycle DWT1 DWT1R, data loaded into buffer transferred DRAM. Clear Transfer Mask Bits addressed As0-2 DQCU/L).
Actual number bits transfer depends state DTBW Mask DQCU/DQCL inputs. Note: DQC(U/L) Low, corresponding DQ(s) is(are) disabled (Input Output Buffer). SR,SW,BR cycles with DQCU DQCL result Deselect SRAM operation. Following DWT1 DWT1R cycle, entire Transfer Mask (i.e. data longer transferred from DRAM.) Succeeding Buffer-Writes Buffer Write Transfers will Clear Mask bits. CMd# during current cycle must High (see timing diagram Auto-Refresh). CMd# during current cycle must (see timing diagram Self-Refresh).
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
FUNCTION TRUTH TABLE
Data Transfer Buffers
Write Buffers Load Load Load Load/ Load/ Load/ Load/ Xfer Masks Mask Mask Clear Mask Clear Mask Clear bits
Read Buffer RB1,2
Dout Hi-Z
Suspend
Function
Operation SRAM Power Down& Data retention DRAM Power Down Deselect SRAM SRAM Read SRAM Write Buffer Read Xfer Buffer Write Xfer Buffer Read Xfer Read Buffer Read Xfer Read Buffer Read Buffer Write DRAM Power Down DRAM OPeration DRAM Read Xfer DRAM Write Xfer1
DRAM Write Xfer1& Read
operation operation operation SRAM->DO DIN->SRAM RB2->SRAM SRAM->WB1 RB2->SRAM->DO DIN->SRAM->WB1 RB2->DO DIN->WB1 operation operation DRAM->RB1->RB2 WB1->WB2->DRAM WB1->WB2 ->DRAM->RB1->RB2 WB2->DRAM WB2->DRAM ->RB1->RB2 WB1->WB2->DRAM WB1->WB2 ->DRAM->RB1->RB2 WB2->DRAM WB2->DRAM->RB
Byte mask
Hi-Z Hi-Z Valid Hi-Z Hi-Z Hi-Z Valid Hi-Z Valid Hi-Z
Valid
Valid
Valid
Load
Load/ Load/
Load
DRAM Write Xfer2
DRAM Write Xfer2& Read
Load
Load
DRAM Write Xfer3
DRAM Write Xfer3& Read
Load Load
DRAM Write Xfer4
DRAM Write Xfer4& Read
Load
DRAM Activate DRAM Precharge Auto Refresh Self Refresh Entry Command Register
Function DRAM Dout SRAM
Page Call
Function SRAM SRAM DRAM
Data Transferred (max) 8/16 bits 8/16bits bits (8X16bit-block) bits (8X16bit-block) bits (8X16bit-block)
Data Transferred (max) bits (8X16bit-block) bits (8X16bit-block) 8/16 bits bits (8X16bit-block)
Data DIN: Data WB1: Write Buffer WB2: Write Buffer Read Buffer
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DESCRIPTIONS(1)
Input Master Clock Provides fundamental timing internal clock frequency CDRAM. external timing parameters (with exception read cycle CMd# Self refresh cycle) specified with respect rising edge DRAM Clock Mask controls operation internal DRAM master clock (K). When CMd# rising edge internal DRAM master clock following cycle ceased input stages powered-off, resulting DRAM Power Down. Address Strobe used conjunction with Master clock (depending states CMd#, CAS#, DTD#) activate DRAM (latching Address lines accessing 4096 rows), initiate DRAM precharge cycle, perform DRAM Read Write Transfer, DRAM Write Transfer Read, command registers, start Auto-Refresh cycle, enter Self-Refresh cycle,create DRAM cycle, power down DRAM. Column Address Strobe used conjunction with Master Clock latch Column addresses. When preceded RAS# DRAM access cycle, CAS# initiates DRAM Write Transfer (WB1/2 DRAM, DTD#=L), DRAM Write Transfer Read (WB1/2 DRAM DTD#=L) DRAM Read Transfer (DRAM DTD#=H), depending state DTD# (see DTD# description). Data Transfer Direction controls DRAM-to-RB(read) WB-to-DRAM (write) direction. preceded RAS# cycle, both CAS# DTD# rising edge initiate DRAM Write Transfer cycle. DTD# stays High with above conditions, DRAM Read Transfer cycle results. DTD# also initiate DRAM Activate, DRAM Precharge, Auto-Refresh, Set-Command Register, Self Refresh cycles. DRAM Address Lines Multiplexed reduce count. Ad0-Ad11 RAS=low,CAS=high,DTD=high, K=Rising edge) specify Address DRAM activate refresh selected page Ad3-Ad7 RAS=high,CAS=low,K=Rising edge) specify Block Address DRAM. addition, Ad0-Ad2 RAS=high,CAS=low, K=Rising edge) specify transfer operation DRAM Also Ad0-Ad9 (@RAS=low,CAS=low, DTD=low, K=Rising Edge) used command command register cycle. Chip Select controls operation CDRAM. When CS#=H rising edge previous CMd# CMs# high, chip Operation mode. SRAM Clock Mask controls operation internal SRAM master clock (Ks). When CMs# asserted rising edge internal SRAM master clock following cycle suspended, resulting power down SRAM portion circuit, including Sense Amps. CMs# also used retain output data during SRAM power-down.
CMd#
Input
RAS#
Input
CAS#
Input
DTD#
Input
Ad0-Ad11
Input
Input
CMs#
Input
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DESCRIPTIONS(2)
DQCl,DQCu Input DQCu/l I/OByte control signals. G#=Low, DQCu/l have control output impedence: DQCu controls upper (DQ8-15) DQCl controls lower (DQ0-7). DQCu/l also control both input data during SRAM Writes Buffer Writes transfer mask during Buffer Writes. (WB1 transfer Masks each byte written (bits cleared) during Buffer Writes depending DQCu/l inputs.) Write Enable controls SRAM Buffer read write operations. high causes either Buffer Read, SRAM Read, Buffer Read Transfer and/or Buffer Read Transfer Read occur (depending state CC0# CC1# bits). causes either Buffer Write, SRAM Write, Buffer Write Transfer and/or Buffer Write Transfer Write occur (depending state CC0# CC1# inputs) Control Clock Inputs control SRAM Buffer operations. CC0# Buffer Writes, Reads, Transfers, High other SRAM operations. CC1# high Buffer Read Transfers Buffer Write Transfers Deselect SRAM. SRAM Addresses non-multiplexed, access 1024 16-bit words configured Rows Columns Bits, where Block Size SRAM array. As0-As3 select word address within block, As3-As9 select SRAM row(block). Output Enable asynchronous input. G#=high forces outputs high impedence. Output operation either transparent, latched, registered depending state command register. Data Lines CDRAM asynchronously controlled VccQ power supply allows device operate mixed voltage system (e.g., data bus). specified Table: Recommended Operating Conditions, VccQ must greater-than equal-to highest voltage experienced data bus. 3.3V system operation, VccQ tied Vcc.
Input
CC0#,CC1#
Inputs
As0-As9
Inputs
Input
DQ0-DQ15
Inputs Outputs
VccQ
Supply
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Operation. Outputs high-impedance. input buffers remain active. CMs#=Low rising edge SRAM enters SRAM Power Down next rising edge During this mode, internal SRAM clock becomes inactive. Output Buffers remain enabled controlled input buffers SRAM clocks SRAM addresses inactive. transfer functions input/output operations from SRAM Buffer disabled. This cycle useful output impedance control (Hi-Z,Low-Z) without Output buffers active during this cycle registered output mode control. Data read from SRAM pins. Addresses As0-As9 used select data read. As3-As9 decode SRAM (=Block), As0-As2 decode 16bit word. DQCu DQCl control impedence (High-Z/Low-Z) upper lower bytes, respectively. Data written from pins SRAM. Addresses As0-As9 used select location written. As3-As9 decode SRAM (=Block), As0-As2 decode (1of8) 16-bit word written. DQCUu DQCl control Upper Lower byte writes, respectively.
DRAM 1MX16
8X16
DRAM RowDecoder
SRAM Power-Down
Deselect SRAM
SRAM Read
8X16Block
Ad3-7 1of32 Decode
8X16
Ad0-9 1of4096Decode
SRAM Write
DQ0-7
Lower Byte Upper Byte
DQ8-15
Lower Byte Upper Byte
8X16
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
Lower Byte Upper Byte
As0-2 1of8 Decode
16bits 8X16
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data transferred from Read Buffer (RB2) SRAM. Addresses As3-9 select SRAM which 8X16 block written. Addresses As0-As2 must low.
DRAM
8X16
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
Ad0-11 1of4096Decode 8X16
Buffer Read Transfer
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
As0-2 1of8Decode
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data transferred from SRAM Write-Buffer1 (WB1). Addresses As3-As9 decode SRAM (=8X16 block) transferred. Addresses As0-As2 must low. Buffer Write Transfer cycle "clears" transfer mask bits Mask (allowing data transferred successive DRAM Write Transfer cycle).
DRAM
DRAM RowDecoder 8X16 8X16 Ad0-11 1of4096Decode 8X16Block
Ad3-7 1of32 Decode
Buffer Write Transfer
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte
Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data transferred from Read Buffer (RB2) SRAM, simultaneously, data word) read from pins. Addresses As3-9 select SRAM which 8X16 block written. Addresses As0-As2 decode 16-bit word read.
DRAM
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
8X16 8X16
Ad0-11 1of4096Decode
Buffer Read Transfer SRAM Read
DQ0-7
Lower Byte Upper Byte
DQ8-15
Lower Byte
Byte Upper
Upper Byte
As0-2 1of8Decode
8X16
Lower Byte
16bits
As0-2 1of8Decode
16bits 8X16
Lower Byte Upper Byte
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data first written from pins SRAM decoded As0-As9. Then, SRAM (=Block) decoded As3-As9 transferred Write-Buffer1 (WB1). Buffer Write Transfer cycle "clears" transfer mask bits Mask (allowing data transferred successive DRAM Write Transfer cycle). DQCu DQCl control Upper Lower byte writes respectively, however transfer mask bits cleared.
DRAM
DRAM RowDecoder 8X16 8X16
DQ0-7
8X16Block
Ad3-7 1of32 Decode
Buffer Write Transfer SRAM Write
Ad0-11 1of4096Decode
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
8X16
Lower Byte Upper Byte
As0-2 1of8 Decode
16bits 8X16
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data read from Read Buffer (RB2) pins. Addresses As0-As2 used select 16-bit word read. Addresses As3-As9 must this operation.
Ad3-7 1of32 Decode 8X16 8X16
DRAM
DRAM RowDecoder
8X16Block
Ad0-11 1of4096Decode
Buffer Read
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits
Lower Byte Upper Byte
8X16
16bits
8X16Block
8X16
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data written from pins Write-Buffer1. Addresses As0-A2 used select (1of8) 16-bit word written. Addresses As3-As9 must this operation. transfer mask bits associated with Upper Lower bytes cleared Mask. DQCu DQCl control Upper Lower byte writes (and associated tranfer mask bits), respectively.
DRAM
DRAM RowDecoder
8X16Block
Ad3-7 1of32 Decode
8X16 8X16
Ad0-11 1of4096Decode
Buffer Write
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
DRAM Power-Down CMd#=Low rising edge DRAM enters DRAM Power Down next rising edge During this mode, internal DRAM clock becomes inactive. Also input buffers DRAM clocks DRAM addresses inactive. Note that latency DRAM Read Transfer cycle counted this cycle. DNOP cycle used when other DRAM operations desired, holding DRAM present (precharge/activate) state. Block (8x16) transferred from DRAM Read Buffer1 (RB1,RB2) specified Addresses Ad3-Ad7. Addresses Ad8-Ad11 Ad0-Ad2 must Low. After Latency Period (specified Access Latency Table) data will present Read Buffer2. Prior Latency timeout, data will present RB2. (Notes 1,2,4)
DRAM
DRAM RowDecoder
DRAM
8X16Block
Ad3-7 1of32 Decode
8X16
Ad0-11 1of4096Decode 8X16
DRAM Read Transfer
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data (8X16 Block) transferred from through DRAM block specified Addresses Ad3-Ad7. Addresses Ad8-Ad11 must Low. Mask present also transferred controls data written DRAM. After data been transferred from present cycle, entire Mask Set. (Notes 3,4)
Ad3-7 1of32 Decode 8X16
DRAM
DRAM RowDecoder
8X16Block
DRAM Write Transfer1
DQ0-7
8X16
Ad0-11 1of4096Decode
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data (8X16 Block) transferred from through DRAM block specified Addresses Ad3-Ad7. Addresses Ad8-A11 must Low. transfer mask present also transferred controls data written DRAM. block which data written DRAM simultaneously transferred Read Buffer.(Notes 2,3,4)
Ad3-7 1of32 Decode
DRAM
DRAM RowDecoder
8X16Block
DRAM Write Transfer1 Read
8X16 8X16
Ad0-11 1of4096Decode
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data (8X16 Block) transferred from DRAM block specified Addresses Ad3Ad7. Addresses Ad8-Ad11 must Low. Mask controls data written DRAM. With DWT2 function, data transfer mask remain unchanged. (Note
DRAM
DRAM RowDecoder 8X16 Ad0-11 1of4096Decode 8X16Block
Ad3-7 1of32 Decode
DRAM Write Transfer2
8X16
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
Data (8X16 Block) transferred from DRAM block specified Addresses Ad3Ad7. Addresses Ad8-Ad11 must Low. transfer mask controls data written DRAM. With DWT2 function, data transfer mask remain unchanged. block which data written DRAM simultaneously transferred Read Buffer1 (Notes 1,2,4)
Ad3-7 1of32 Decode 8X16
DRAM 1MX16
8X16Block
DRAM RowDecoder Ad0-11 1of4096Decode
DRAM Write Transfer2 Read
8X16
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
8X16 As0-2 1of8 Decode
As0-2 1of8Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits SRAM 1KX16
SRAM RowDecoder
As0-2 1of8Decode
As3-9 1of128Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data (8X16 Block) transferred from through DRAM block specified Addresses Ad3-Ad7. Addresses Ad8-Ad9 must Low. Mask present Byte MaskRegister controls data written DRAM. Byte Mask Register Load Byte Mask cycle,where corresponding byte masks depending data cycle. (Note 4,5) data mask data WBM1 tranferred WBM2, however WBM1/2 used this cycle.
Ad3-7 1of32 Decode 8X16
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer3
DQ0-7 Lower Byte Upper Byte
Ad0-11 1of4096Decode 8X16
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
Data (8X16 Block) transferred from through DRAM block specified Addresses Ad3-Ad7. Addresses Ad8-Ad9 must Low. Mask present Byte MaskRegister controls data written DRAM. block which data written DRAM simultaneously transferred Read Buffer.(Notes 1,2,4,5)
Ad3-7 1of32 Decode 8X16
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer3 Read
Ad0-11 1of4096Decode 8X16
DQ0-7
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS
Data (8X16 Block) transferred from DRAM block specified Addresses Ad3Ad7. Addresses Ad8-Ad9 must Low. Mask present Byte MaskRegister controls data written DRAM. With DWT4 function, data Mask remain unchanged. (Note 4,5)
DRAM 256KX16
DRAM RowDecoder 8X16 8X16Block
Ad3-7 1of32 Decode
DRAM Write Transfer4
DQ0-7 Lower Byte Upper Byte
Ad0-11 1of4096Decode 8X16
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
Data (8X16 Block) transferred from DRAM block specified Addresses Ad3Ad7. Addresses Ad8-Ad9 must Low. Mask present Byte MaskRegister controls data written DRAM. With DWT4R function, data transfer mask remain unchanged. block which data written DRAM simultaneously transferred Read Buffer. (Notes 1,2,4,5)
Ad3-7 1of32 Decode
DRAM 256KX16
DRAM RowDecoder
8X16Block
DRAM Write Transfer4 Read
8X16 8X16
DQ0-7
Ad0-11 1of4096Decode
Lower Byte Upper Byte
DQ8-15 Lower Byte Upper Byte
As0-2 1of8Decode
8X16 As0-2 1of8 Decode
Lower Byte Upper Byte
16bits
16bits 8X16
Lower Byte Upper Byte
16bits
8X16 8X16Block
16bits
SRAM 1KX16
SRAM RowDecoder As3-9 1of128Decode
As0-2 1of8Decode
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
MODE DESCRIPTIONS (10)
DRAM Activate DRAM Precharge Addresses latched from Ad0-Ad11 inputs rising edge Internally, DRAM selected (Page Call) preparation DRAM Read Write Transfer cycle. DRAM Precharge cycle must separate DRAM Activate cycles. Internally, active DRAM deselected (completing refresh process) page-mode disabled. DRAM precharged prior another DRAM Activate cycle. Internally, DRAM selected refreshed addressed internal, self-incrementing counter), followed internally generated Precharge cycle. Auto refresh cycle implemented only DRAM Precharge state (i.e., Precharge Auto-Refresh cycle occurred more recently than Acitvate cycle). DRAM Auto-Refresh similar CAS-BeforeRAS (CBR) mode standard DRAMs. clock buffers suspended, CMd# asynchronously controls Self Refresh (CMd# rising edge initiates exit from Self Refresh). During Self Refresh, device enters power mode, with 2048 automatic refresh cycles. When initiated,the addresses present Ad0-Ad11 DRAM Address pins determine DRAM Read Transfer Latency, Output Mode (transparent latched registered), transfer mask mode (set-all/ change). DRAM operation executed this cycle. Refer Truth Table legal Address values. During cycle following clock cycles(totally clock cycles), only NOP,DNOP orDPD allowed DRAM portion only NOP,DES done SRAM portion. commands valid least after above clocks later previous function guaranteed work been completed.(i.e. ,DWT1&R,DWT2&R SR,BR BRTR with registered output mode.)
DRAM Auto-Refresh
DRAM Self Refresh
Command Register
Notes:
This function performed Latency period specified Access Latency Table. After Latency Period (specified Access Latency Table) data will present Read Buffer2. Prior Latency timeout, data will present RB2. After data been transferred from WB1, entire Mask Set. Valid Ad0-Ad2 addresses shown FUNCTION TRUTH TABLE.
Power-On sequence
Before starting normal operation, following power sequence necessary. Apply power maintain stable power (pause) 500us. Perform precharge (PCG) operation. After tRP, perform auto refresh commands (ARF) with adequate interval (tRC). Issue command register (SCR) initilize mode register. After this sequence, idle state ready normal operation. Note that DNOP command will stand-by command above power sequence. must powered-on same time before VccQ must powered-off same time after VccQ off.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Output Operations Output appears from rising edge clock. Transparent
tKHQX tKHA tKHQZ
tKHA
tGLA
DQ0-15
DQ0-15
tGLQ
tGHQ
Latched
Output appears from falling edge clock.
tKHA
tKLQX
tKLA
This outputmode deleted.
tKHA tKLA tKLQZ tGLA tGHQ
DQ0-15
DQ0-15
tGLQ
Registered
Output appears from rising edge clock.
tKHAR
tKHQX tKHQZ tKHAR
DQ0-15
tGLA
tKHQZ
tGHQ
DQ0-15
tGLQ
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
K,K#
tCMDH tCSH tDTH tCMSH tC0H tC1H tDQCH tHADF
CMd#
tCMDS tCSS tDTS tCMSS tC0S tC1S tDQCS tSADF
RAS#
CAS# DTD# CMs# CC0#
CC1# DQC(u ADF#
Ad0-11 As0-9
DQ0-15 (Input)
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Load Byte Mask
Byte mask allocation during DWT3 DWT4 Byte Mask Register Lower
Upper
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Lower Upper
Block address
Column Block byte)
mask, write unmask, write enable
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DWT3 DWT4 Write data Mask data
DRAM column
DRAM 1023
byte mask
written
Lower 8bit Upper8
SRAM
WB1/WB2
Byte mask
lower byte Byte mask
upper byte
DQ0-> ->DQ15
Write Mask logic
DWT2 DWT1
As0-2
addition DWT3/DWT4
DQCl DQCu
DQ0-15 Load Byte Mask (LBM)
SRAM
DRAM
DWT1/DWT3 DWT2/DWT4
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DWT3-DWT4 Window clear(Block Write)
shadow clear window clear
Window Boundary
Page boundary
DNOP DWT3 DNOP DWT4 DNOP DWT4 DNOP DWT4 DNOP DWT4
Color data transferred from DRAM column block with byte mask. Color data transferred from DRAM column block with byte mask. Color data transferred from through DRAM column block with byte mask, which loaded Load Byte Mask cycle(LBM). byte mask data valid from cycle immediately lasts until next cycle initiated. Color data loaded from SRAM cache WB1.(BWT) Page call.(ACT) (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Burst Mode
CMs#
ADF#
CC0#
CC1# DQC(u As0-2
Accept interrupt inputting address gap.
As3-11 DQ0-15
Q1+1 Q1+2 Q1+3
Q2+1
Q3+1 Q3+2 Q3+3
SRAM address DRAM address multiplexed using this duration DRAM control
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Burst Mode
CMs#
ADF#
CC0#
CC1# DQC(u As0-2
As3-11 DQ0-15
Q1+1 D1+2
Burst address incremented DES, SPD.
"Insert wait" possible.
ADF#=Low equal non-burst mode.
M5M4V16169D keeps compatibility setting ADF# setting Burst length=1 cycle. (Ad7, Ad9=0) MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
**-15 spec same M5M4V16169TP/RT-15
ABSOLUTE MAXIMUM RATINGS (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Conditions With respect Ratings -0.5 -0.5 -0.5 1000 Unit
RECOMMENDED OPERATING CONDITIONS (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Symbol VccQ
(LVTTL) (LVTTL) (LVTTL)
Parameter Supply Voltage Supply Voltage Supply Voltage Output High-level Input Voltage clock add. High-level Input Voltage master clock High-level Input Voltage data Low-level Input Voltage inputs
Limits Min. -0.3 Typ. Vdd+0.3 Vdd+0.3 VddQ+0.3 Unit
(LVTTL)
CAPACITANCE (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Symbol CI(A) CI(C) CI/O Parameter Input Capacitance, Address Input Capacitance, Clock Input Capacitance, Test Condition I=Vss f=1MHz =25mVrms Limits (MAX) Unit
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
**-15 spec same M5M4V16169TP/RT-15
AVERAGE SUPPLY CURRENT from (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Symbol IccS IccD IccD(PG) Condition
Average supply current SRAM operating, tK=min. DRAM=DPD output open data input=H
Limits (MAX)
Unit
Average supply current DRAM operating, tRC=min. SRAM=SPD
Average supply current DRAM page-mode tPC=min. SRAM=SPD LVTTL standby, tK=min, DRAM=DNOP&SRAM=DES, output open data input=H CMOS standby, tK=min, DRAM=DNOP&SRAM+DES, output open data input=H
Icc(STN1) input=stable. Icc(STN2) input=stable. Icc(PD) Icc(SRF)
CMOS Power Down current, CMd#=CMs#=L,tK=min. CMOS Self Refresh current, CMd#=CMs#=L,tK=
OPERATING CONDITIONS CHARACTERISTICS (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Symbol
VOH(DC)*(LVTTL) VOL(DC)*(LVTTL)
Parameter High-level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current
Test Condition IOH= -2mA IOL=
floating ~VddQ
Limits Min.
Unit
VddQ+0.3V
VOH(AC) VOL(AC) reference levels measurements. VOH(DC) VOL(DC) final levels outputs reach.
50ohm
VOUT 30pF
Condition
(Access Time)
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
**-15 spec same M5M4V16169TP/RT-15
TIMING REQUIREMENTS (CLK pulse, input signals setup hold time edge) (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL)
Limits Symbol Parameter Min. Clock Cycle Time Clock High Pulse Width Clock Pulse Width Setup Time Inputs Hold Time Inputs Min. Min. Min. Unit
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
**-15 spec same M5M4V16169TP/RT-15
TIMING REQUIREMENTS (Read, Write, Refresh) (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted) Input Pulse Levels: Input Timing Measurement Reference Level: VIH=3.0V,VIL=0.0V (LVTTL) 1.5V (LVTTL)
Limits Symbol tREF tRCD tRC* tWC* tRAS tRASP tRWL tRSH Parameter Min. Refresh Cycle Time Precharge Time Delay Time, Strb. Col. DRAM Activate-Read Cycle Time DRAM Activate-Write Cycle Time Page Cycle Time Activate Time Page mode Activate Time Write Precharge Lead Time Read Precharge Hold Time Min. Min. Min. Unit
12,000 100,000
10,000 100,000
10,000 100,000
10,000 100,000
*Note: When tRAS Min. values, tRAS.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
**-15 spec same M5M4V16169TP/RT-15
SWITCHING CHARACTERISTICS (Ta=0~70°C Vdd=3.3±0.3V -8,and -10, Vdd=3.3±0.15V Vss=0V, unless otherwise noted)
Limits Symbol Parameter Buffer-Fill from DRAM Read Transfer Access Time from K-High Edge Output Active Time from K-High Edge Output Disable Time from K-High Edge Access Time from K-High Edge Output Active Time from K-High Edge Output Disable Time from K-High Edge Access Time from G#-Low Edge Output Active Time from G#-Low Edge Output Disable Time from G#-High Edge
Min.
Min.
Min.
Min.
Unit
tCBF tKHA tKHQX tKHQZ tKHAR tKHQXR tKHQZR tGLA tGLQ tGHQ
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
non-G# controlled Write Read (DES control) SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down
CMs#
CC0#
CC1# DQC(u As0-2
As3-9 DQ0-15
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
controlled Write Read SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down
CMs# CC0#
CC1# DQC(u
As0-2 As3-9
DQ0-15
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
controlled Write Read SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down
CMs#
CC0#
CC1# DQCu DQCl As0-2
As3-9 DQ8-15
DQ0-7
(u/l)
(u/l)
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Registered Output control SRAM Read/Deselect SRAM/SRAM Write/SRAM Power-down
CMs#
CC0#
CC1# DQC(u As0-2
As3-9 DQ0-15
Note Output registered. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Buffer Read Transfer (RB2 SRAM) Buffer Read Transfer SRAM Read (RB2 SRAM Output)
CMs# CC0#
CC1# DQC(u
As0-2 As3-9
(C1)
(C1)
(C1)
(C1)
(C1)
(C5)
(C5)
(C5)
(C5)
DQ0-15
BRTR
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Buffer Write Transfer (SRAM WB1) Buffer Write Transfer SRAM Write (Input SRAM WB1)
CMs# CC0#
CC1# DQC(u
As0-2 As3-9
WB1(0-7)
DQ0-15
BWTW
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Buffer Write (Input WB1) Buffer Read (RB2 Output)
CMs# CC0#
CC1# DQC(u
As0-2 As3-9 WB1(0-7) Mask(0-7)
DQ0-15
Note Output transparent. MITSUBISHI ELECTRIC
DRAM operation freely performed.
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Operation SRAM
CMs#
CC0# CC1#
DQC(U
AS0-9
NO-Operation Mode
CMd# RAS# CAS# DTD# Ad0-11 DRAM operation freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Operation DRAM
CMd#
RAS#
CAS#
DTD#
Ad0-11
NO-Operation Mode
CMs# CC0# CC1# DQC(u/l) As0-9 DQ0-15 SRAM operation freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Power Down DRAM Activate DRAM Precharge
CMd#
RAS# CAS#
DTD# Ad0-11
DNOP DNOP DNOP DNOP
CMs# CC0# CC1# DQC(u/l) As0-9 DQ0-15 SRAM operation freely performed.
recommended during operation save power. MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
only Refresh cycle DRAM Power Down DRAM Activate DRAM Precharge
CMd#
tRAS
RAS# CAS#
DTD#
Ad0-11
DNOP DNOP DNOP DNOP
CMs# CC0# CC1# DQC(u/l) As0-9 DQ0-15 SRAM operation freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Auto Refresh
CMd#
RAS#
CAS# DTD#
Ad0-11
DNOP DNOP DNOP DNOP
CMs# CC0# CC1# DQC(u/l) As0-9 DQ0-15
Note: DRAM must Precharge state prior Auto-Refresh cycle. DRAM commands except NOP,DNOP after later from command input.
SRAM operation freely performed.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Self Refresh
Inhibit falling edge.
CMd#
RAS#
CAS# DTD#
DNOP DNOP Halt
Ad0-11
Halt
Halt DNOP DNOP DNOP DNOP DNOP
Recovery
Self Refresh Mode SRAM Power Down Mode Self Refresh Entry
Self Refresh SRAM Power Down Exit
Self Refresh Entry: (Note: DRAM must Precharge state prior Self-Refresh Entry) Previous CMd#=H, Present CMd#=L, CS#=RAS#=CAS#=L, DTD#=H (CMd# must remain maintain Self Refresh). Self Refresh Exit order): resume clock CMd#=H Wait recovery Resume normal operation
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Read Transfer (DRAM RB1-> RB2) Latency set=1
CMd#
tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**Col
tCBF
DRAM SRAM
Data Latency Data
DNOP
Data
Data
DNOP
DQ0-15
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Read Transfer (DRAM RB1-> RB2) Latency set=2
CMd#
tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2 Ad3-9
Ad0-Ad2=Low
**Col
tCBF
Data Latency
Data
DRAM SRAM
Data
DNOP
Data
DNOP
DQ0-15
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Read Transfer (DRAM RB1-> RB2) Latency set=3
CMd#
tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**Col
tCBF
Data Latency
Data
DRAM SRAM
Data
Data
DNOP
DNOP
DQ0-15
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Read Transfer (DRAM RB1-> RB2) Latency set=4
CMd#
tRAS
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**Col
tCBF
Data Latency Data
Data
Data
DRAM SRAM
DNOP
DNOP
DNOP
DQ0-15
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Read Transfer (Pipe-lined Page-Mode) Latency set=1
CMd#
tRASP
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**C1
**C2
**C3
**C4
**C5
**C6
tCBF
tCBF
tCBF tCBF tCBF tCBF
Data
Latency Latency
Latency Latency Latency Latency
DRAM SRAM
Data
DNOP
DNOP
DNOP
DNOP
DQ0-15
Pipe-lined Page mode
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=2
CMd#
tRASP
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**C1
**C2
**C3
**C4
**C5
**C6
tCBF
tCBF tCBF
tCBF tCBF tCBF tCBF tCBF
DNOP
Data
tCBF
DRAM SRAM
Data
DNOP
DNOP
DNOP
DQ0-15
next happens within latency, data does transferred However this operation guaranteed. SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=3
CMd#
tRASP
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2 Ad3-11
Ad0-Ad2=Low
**C1
**C2
**C3
**C4
tCBF
tCBF Latency
tCBF tCBF Latency
DNOP DNOP
DRAM SRAM
Data
Latency Data
DNOP
DNOP
DNOP DNOP
DQ0-15
next happens within latency, data does transferred However this operation guaranteed.
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Read Transfer Latency set=4
CMd#
tRASP
RAS#
tRCD tRSH
CAS#
DTD#
Ad0-2 Ad3-11
Ad0-Ad2=Low
**C1
**C2
**C3
tCBF
tCBF Latency
tCBF Latency
DRAM SRAM
Data
Data
DNOP
DNOP DNOP DNOP
DNOP
DNOP DNOP
DQ0-15
next happens within latency, data does transferred However this operation guaranteed.
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
CMd#
tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0-2 Ad3-11
Ad0-Ad2=Low
**Col
Data
Data[WB1(0-7)]
DRAM SRAM
DNOP
DWT1 DNOP
DQ0-15
Please refer next page detail.
SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
detail
CMd#
tRAS tRCD tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 [0-7] WB1[0] mask[0] WB1[1] mask[1] WB1[2] mask[2] WB1[3] masl[3] WB1[4] mask[4] WB1[5] mask[5] WB1[6] mask[6] WB1[7] mask[7]
DRAM SRAM
Ad0-Ad2=Low
Data
**Col
Data[from WB1(0-7)]
DNOP DWT1 DNOP
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1)
CMd#
tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low
Ad3-11
**Col
Data
Data[WB1(0-7)]
Data
Data
Next Data
DRAM SRAM
DNOP
DWT1 DNOP
DQ0-15
Please refer next page detail.
SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write Transfer (SRAM->WB1)
detail
CMd#
tRAS tRCD tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 [0-7] WB1[0] mask[0] WB1[1] mask[1] WB1[2] mask[2] WB1[3] masl[3] WB1[4] mask[4] WB1[5] mask[5] WB1[6] mask[6] WB1[7] mask[7]
DRAM SRAM
Ad0-Ad2=Low
Data
**Col
Data[from WB1(0-7)]
DNOP DWT1 DNOP
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
CMd#
tRASP tRCD tRWL
RAS#
CAS#
DTD#
Ad0-2
Ad0-Ad2=Low Ad0-Ad2=Low
Ad3-11
**Col
**Col
Data
Data[WB1(0-7)]
Next Data[WB1(0-1)]
DRAM SRAM
DNOP
DWT1 DNOP DWT1
DNOP
DQ0-15
Please refer next page detail.
SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Page-Mode DRAM Write Transfer (WB1->WB2->DRAM) Buffer Write (DIN->WB1)
detail
CMd#
tRASP tRCD tRWL
RAS# CAS# DTD# Ad0-2 Ad3-11 [0-7] WB1[0] mask[0] WB1[1] mask[1] WB1[2] mask[2] WB1[3] masl[3] WB1[4] mask[4] WB1[5] mask[5] WB1[6] mask[6] WB1[7] mask[7]
DRAM SRAM
DNOP
Ad0-Ad2=Low Ad0-Ad2=Low
Data
**Col
**Col
Data [from WB1(0-7)]
Next Data[WB1(0-1)]
DWT1 DNOP DWT1 DNOP
DQ0-15
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer 1&Read (WB1->WB2->DRAM->RB) Latency set=1 Buffer Write (DIN->WB1)
CMd#
tRAS
RAS#
tRCD tRWL
CAS#
DTD#
Ad0=High
Ad0-2 Ad3-11
Ad1-Ad2=Low
**Col
Data
Data[WB1(0-7)]
tCBF
tCBF
DRAM SRAM
Data tCBF Data Latency
Data[WB1(0-7)]
Data[WB1(0-7)]
DNOP DWT1R DNOP
DQ0-15
Data appears latency count. timing chart. SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer (WB2->DRAM)
CMd#
tRASP tRCD tRWL
RAS#
CAS#
DTD#
Ad1=High
Ad0-2 Ad3-11
Ad0-Ad2=Low Ad0,Ad2=Low
**Col
**Col
NoChange
Data
Data[WB1(0-7)]
DRAM SRAM
DNOP DWT1 DNOP DWT2 DNOP
DQ0-15
SRAM operation freely performed.
Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
DRAM Write Transfer2 Read (WB2->DRAM->RB1-> RB2) Latency set=1
CMd#
tRASP tRCD tRWL
RAS#
CAS#
DTD#
Ad0,Ad1=High
Ad0-2
Ad0-Ad2=Low Ad2=Low
Ad3-11
**Col
**Col
NoChange
Data
Data[WB1(0-7)]
tCBF
DRAM SRAM
Data
Data[WB1(0-7)] Latency
Data
Data[WB1(0-7)]
DNOP DWT1 DNOP DWT2 DNOP
DQ0-15
Data appears latency count. timing chart. SRAM operation freely performed. Ad3-Ad7 column block addresses (Ad8~Ad11=Low). (REV 1.0) Jul. 1998
MITSUBISHI ELECTRIC
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
This page left blank, that Command Register Timing Diagram next spread seen conveniently.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Command Register
CMd#
RAS#
CAS# DTD#
Ad0-11
DNOP DNOP DNOP
*Set Command Reg.
Inhibit command except DNOP,DPD DES,SPD NOP.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Command Register(2)
Address Input
Ad11 Ad10
Command
operation Xfer Masks Default Output ModeTransparent Output Mode Latched Output Mode Registered
Latency Latency Latency Latency Default BL=1 BL=2 BL=4 BL=8 Sequential Interleave
Default Default
CMd#
RAS#
CAS# DTD# Ad0~11
Command
Latency number clock cycles required transfer data from DRAM Read Buffer Therefore, adjusted clock frequency system. (Latency) (tK) should meet tCBF min. timing requirement.
Inhibit read write function during these clocks. MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
Burst Mode Address
Initial Address Sequential Interleaved
Note: When SRAM command executed more than burst length, Address repeats with same sequence.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998
M5M4V16169DTP/RT-7,-8,-10,-15
16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM
70P3S Package Dimension
70P3S-L
0.125 +0.05 -0.02
+0.02 (0.005 -0.0008
70P3S-M
0.5+-0.1 (0.02+-0.004) Detail 0.65+-0.1 (0.026+-0.004)
23.49+-0.1 UNIT (INCH)
+0.1 -0.05 +0.004 -0.05
(0.012
(0.925+-0.004)
(0.004)
Note)
Dimension include mold flash. Dimension does include remain.
MITSUBISHI ELECTRIC
(REV 1.0) Jul. 1998

16MCDRAM:16M(1M-WORD 16-BIT) CACHED DRAM WITH (1024-WORD 16-BIT) SRAM

Top Searches for this datasheet

Other recent searches