Operation From Very Slow Input Transitions Temperature-Compensated Thr

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Operation From Very Slow Input Transitions Temperature-Compensated Thr

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SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts 'HC32 Package Options Include Plastic Small-Outline Ceramic Flat Packages, Ceramic Chip Carriers (FK), Standard Plastic Ceramic 300-mil DIPs
SN54HC7032 PACKAGE SN74HC7032 PACKAGE (TOP VIEW)
description
these devices, each circuit functions quadruple gate. They perform Boolean positive function logic. However, because Schmitt action, inputs have different input threshold levels positive- negative-going signals.
SN54HC7032 PACKAGE (TOP VIEW)
SN54HC7032 characterized operation over full military temperature range -55°C 125°C. SN74HC7032 characterized operation from -40°C 85°C.
FUNCTION TABLE (each gate) INPUTS OUTPUT
internal connection
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 1997, Texas Instruments Incorporated
DALLAS, TEXAS 75265
These circuits temperature compensated triggered from slowest input ramps still give clean jitter-free output signals.
SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
logic symbol
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
logic diagram, each gate (positive logic)
absolute maximum ratings over operating free-air temperature range
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 127°C/W package 78°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD except through-hole packages, which trace length zero.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
recommended operating conditions
SN54HC7032 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage Operating free-air temperature 3.15 1.35 SN74HC7032 3.15 1.35 UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -5.2 1.55 3.98 5.48 25°C 1.998 4.499 5.999 0.002 0.001 0.001 0.17 0.15 ±0.1 0.26 0.26 3.15 2.45 ±100 1.55 SN54HC7032 3.15 2.45 ±1000 1.55 SN74HC7032 3.84 5.34 0.33 0.33 3.15 2.45 ±1000 UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54HC7032, SN74HC7032 QUADRUPLE POSITIVE-OR GATES WITH SCHMITT-TRIGGER INPUTS
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 25°C SN54HC7032 SN74HC7032 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance gate TEST CONDITIONS load UNIT
PARAMETER MEASUREMENT INFORMATION
From Output Under Test Test Point (see Note In-Phase Output Input tPLH tPHL Out-of-Phase Output Input tPLH tPHL
LOAD CIRCUIT
VOLTAGE WAVEFORM INPUT RISE FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
NOTES: includes probe test-fixture capacitance. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
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POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated

Operation From Very Slow Input Transitions Temperature-Compensated Thr

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