DDC101 20-BIT ANALOG-TO-DIGITAL CONVERTER FEATURES MONO
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DDC101
20-BIT ANALOG-TO-DIGITAL CONVERTER
FEATURES
MONOLITHIC CHARGE INPUT DIGITAL FILTER NOISE REDUCTION: 0.9ppm, DIGITAL ERROR CORRECTION: CONVERSION RATE: 15kHz USER FRIENDLY EVALUATION FIXTURE
APPLICATIONS
DIRECT PHOTOSENSOR DIGITIZATION PRECISION INSTRUMENTATION INFRARED PYROMETRY PRECISION PROCESS CONTROL SCANNER CHEMICAL ANALYZERS
DESCRIPTION
DDC101 precision, wide dynamic range, charge digitizing converter with 20-bit resolution. level current output devices, such photosensors, directly connected input. most stringent accuracy requirements many unipolar output sensor applications occur signal levels. meet this requirement, Burr-Brown developed adaptive delta modulation architecture DDC101 provide linearly improving noise linearity errors input signal level decreases. DDC101 combines functions current-to-voltage conversion, integration, input programmable gain amplification, conversion, digital filtering produce precision, wide dynamic range results. input signal level current connected directly into unit voltage connected through user selected resistor. Although DDC101 optimized unipolar signals, also accurately digitize bipolar input signals. patented delta modulaTest
tion topology combines charge integration digitization functions. Oversampling digital filtering reduce system noise dramatically. Correlated Double Sampling (CDS) captures eliminates steady state conversion cycle dependent offset switching errors that eliminated with conventional analog circuits. DDC101 block diagram shown below. During conversion, input signal collected internal integration capacitance user determined integration period. high precision, autozeroed comparator samples analog input node. Tracking logic updates internal high resolution converter 2MHz rate maintain analog input virtual ground. user programmable digital filter oversamples tracking logic's output. digital filter passes noise, high resolution digital output serial register. serial outputs multiple DDC101 units easily connected together series parallel desired minimize interconnections.
DDC101 Integrated Circuit
Test Current Reset
CDAC CINT Bits
Analog Input Ground Comparator
Digital Integration, Tracking Control Logic
Digital Filter Error Correction Oversampled Digital
Bits Serial Register
Serial Serial
VREF
Setup
International Airport Industrial Park Mailing Address: 11400, Tucson, 85734 Street Address: 6730 Tucson Blvd., Tucson, 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1993 Burr-Brown Corporation
PDS-1211E
Printed U.S.A. March, 1998
SBAS029
TABLE CONTENTS
Section Basic Theory Operation Specifications Descriptions Timing Diagrams Discussion Specifications Detailed Theory Operation Applications Information Mechanical
SECTION BASIC THEORY OPERATION
basic function DDC101 illustrated Simplified Equivalent Circuit shown Figure operation equivalent functions performed very high quality, bias current switched integrator followed precision floating point programmable gain amplifier ending with high resolution converter.
second block diagram, Figure shows DDC101 circuit architecture which implements these functions monolithically. During each conversion, input signal current collected internal integration capacitance, CINT, charge user determined integration period, TINT. integration capacitor collects input charge, tracking logic updates internal high resolution converter 2MHz rate maintain analog input node virtual ground. digital filter oversamples tracking logic's output beginning each integration period produce oversampled data points. DDC101 measures charge accumulated integration performs correlated double sampling (CDS) subtracting these data points. eliminates integration cycle dependent errors such charge injection, offset voltage, reset noise since these errors measured with signal each data points. number oversamples, thus frequency response digital filter, user programmable. digital filter passes noise, high resolution digital output serial register. Since timing control serial register independent DDC101 conversion process, outputs multiple DDC101 units connected together series parallel minimize interconnections.
Reset
Signal
CINT
Converter Control Logic
Data
Sensor
Switched Integrator
Programmable Gain Amplifier
FIGURE Simplified Equivalent Circuit DDC101 Illustrate Function.
Test DDC101 Integrated Circuit
Test Current Reset
CDAC CINT Bits
Analog Input Ground Comparator
Digital Integration, Tracking Control Logic
Digital Filter Error Correction Oversampled Digital
Bits Serial Register
Serial Serial
VREF
Setup
FIGURE DDC101 Block Diagram.
DDC101
internal test current source provided basic functionality testing diagnostics. This approximately 100nA current source activated sums with external input current. Figure shows more detailed circuit configuration DDC101. single integration capacitor, CINT, converter have been replaced with high resolution
Capacitor Digital-to-Analog Converter (CDAC). switching between ground VREF binary weighted capacitor array CDAC accumulates input signal's charge keep comparator input virtual ground.
DDC101
Test Current Reset CDAC
CINT
ANALOG
Buffer High Resolution Digital Order Digital Integration, Tracking Control Logic Bits Digital Filter Bits Serial Register
DATA INPUT
DATA OUTPUT Oversampled Digital
Sensor
ANALOG COMMON
Comparator
TEST
VREF
SYSTEM System Control CLOCK
DATA DATA TRANSMIT CLOCK
FIGURE DDC101 Detailed Circuit Diagram.
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
DDC101
SECTION SPECIFICATIONS
specifications with unipolar current input range, TINT 1ms, correlated double sampling enabled, System Clock 2MHz, VREF -2.5V, +25°C ±5VDC, unless otherwise noted. DDC101 PARAMETER INPUTS Charge Input(6) Unipolar Input Range Bipolar Input Range Input Current Current Input Range Examples(10) Unipolar Input Range Unipolar Input Range Bipolar Input Range Bipolar Input Range Voltage Input Examples(10) Unipolar Input Range(2) Bipolar Input Range(2) DYNAMIC CHARACTERISTICS Conversion Time Integration Time System Clock Input ACCURACY Unipolar Mode Noise Noise, Level Current Input(1) Noise, Level Current Input(1) Noise, Level Current Input(1) Noise, Level Current Input(1) Noise, Voltage Input(1, Differential Linearity Error Unipolar Input Range CONDITIONS UNITS
ELECTRICAL
Output Code Output Code Unipolar Bipolar Range TINT 100µs TINT TINT 100µs TINT 10M, TINT 10M, TINT
-1.95 -251.95
pC/Integration pC/Integration
-0.0195 -1.95 -2.5195 -251.95 -0.0195 -2.5195
CSENSOR 0pF, CSENSOR 0pF, CSENSOR 100pF, CSENSOR 500pF, Entire Range 0.1% Input Input Input
FSR, rms(3) FSR, FSR, FSR, FSR,
Unipolar Bipolar Input Range Integral Linearity Error Unipolar Input Range(11)
±0.005% Reading ±0.5ppm FSR, ±0.00006 ±0.00010 ±0.00055 ±0.0015 ±0.0244% Reading ±2.5ppm FSR, ±0.0244% Reading ±3.0ppm FSR, ±0.00028 ±0.00050 ±0.0027 ±0.003 ±0.5 ±0.5 ±0.5 -2.5 Compatible CMOS Bits Bits µV/°C µV/°C pA/°C ppm/°C
pc/Integration -1.95 pc/Integration 0.1% Input Input Input
Unipolar Bipolar Input Range(11) Missing Codes Unipolar Input Range Bipolar Input Range Input Bias Current Gain Error Output Offset Error(8) Input Offset Voltage(8) External Voltage Reference, VREF Internal Test Signal Internal Test Signal Accuracy Gain Sensitivity VREF PSRR
+25°C
VREF 2.5V ±0.1V
PERFORMANCE OVER TEMPERATURE Output Offset Drift(8) including bias current drift Input Offset Voltage Drift(8) Input Bias Current Drift +25°C +45°C Input Bias Current +85°C Gain Drift(4) DIGITAL INPUT/OUTPUT Logic Family Logic Level: Data Clock Data SETUP Code I/O(9) Data Format Straight Binary Two's Complement
+5µA +5µA Loads Loads
+2.0 -0.3 +2.4
+VCC +0.8 +VCC
Bits Bits
Unipolar Bipolar Range Unipolar Bipolar Range
DDC101
SPECIFICATIONS (CONT)
ELECTRICAL
specifications with unipolar current input range, TINT 1ms, correlated double sampling enabled, System Clock 2MHz, VREF -2.5V, +25°C ±5VDC, unless otherwise noted. DDC101 PARAMETER POWER SUPPLY REQUIREMENTS Operation(5) Quiescent Current, Positive Supply Analog, Digital, VDD+ Quiescent Current, Negative Supply Operating Power TEMPERATURE RANGE Operating Storage CONDITIONS ±4.75 +5VDC, VDD+ +5VDC 15.6 18.0 ±5.25 19.5 UNITS
-5VDC
22.5
+100
NOTES: Input level (less than Full Scale); Full Scale 500nA; TINT 1ms; Unipolar Input Range; Acquisition Time clock cycles, Oversampling 128. Voltage input converted through user provided input resistor, RIN. Full Scale Range. Gain Drift does include drift external reference. VDD+ must less than equal VS+. Section recommended connections. Straight Binary output code slightly different Charge Range. Section Input offset voltage nulled autozero circuitry causes output error. Section (Internal Error Correction). This maximum clock frequency which SETUP codes written read from DDC101. (10) other input current voltage configurations, Discussion Specifications Detailed Theory Operation sections. (11) best-fit straight line method used determine linearity. different best-fit straight lines used unipolar integral linearity specifications. Acquisition Time clock cycles, Oversampling 128.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER(1) THERMAL RESISTANCE (JA)
(°C/W)
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
PRODUCT DDC101U
PACKAGE 24-Lead SOIC
NOTE: detailed drawing dimension table, please data sheet, Appendix Burr-Brown Data Book.
ABSOLUTE MAXIMUM RATINGS
Analog Inputs Input Current 100mA, momentary Input Current 10mA, continuous Input Voltage +0.5V -0.5V Power Supply VDD+ must Maximum Junction Temperature +165°C
information provided herein believed reliable; however, BURR-BROWN assumes responsibility inaccuracies omissions. BURR-BROWN assumes responsibility this information, such information shall entirely user's risk. Prices specifications subject change without notice. patent rights licenses circuits described herein implied granted third party. BURR-BROWN does authorize warrant BURR-BROWN product life support devices and/or systems.
DDC101
CONFIGURATION
View
VS-, ANALOG ANALOG COMMON ANALOG ANALOG COMMON VS+, ANALOG VS+, ANALOG RESET SYSTEM (Final Data Point Start) SYSTEM CLOCK DATA CLOCK DATA INPUT VDD+, DIGITAL REFERENCE BUFFER BYPASS VREF TEST RESET SETUP SETUP READ DATA/SETUP DATA TRANSMIT OVERFLOW OVERFLOW DATA VALID DATA OUTPUT DIGITAL GROUND
24-Lead SOIC
SECTION DESCRIPTIONS
NUMBER NAME VS-, ANALOG ANALOG COMMON ANALOG INPUT ANALOG COMMON VS+, ANALOG VS+, ANALOG RESET SYSTEM DESCRIPTION Negative analog power supply voltage, -5VDC. Analog ground point. Input level current signal. Photosensor directly connected this input. With resistor series, DDC101 will convert voltage input. Analog ground point. Positive analog power supply voltage, +5VDC. Hardwire Positive analog power supply voltage, +5VDC. Hardwire This input resets DDC101, does reset SETUP register. DDC101 system reset when this active; reset action removed when inactive. This Final Data point Start input. This input basic user control integration conversion timing. When becomes active, DDC101 starts collection final data point samples. beginning next integration time exactly system clock periods after Final Data point Start command when operating continuous mode. This clock input sets basic sampling rate DDC101. DDC101 specified with clock speed 2MHz. clock speed 0.5MHz 2.0MHz. This clock input controls data transfer rate serial DATA INPUT DATA OUTPUT ports. DATA CLOCK independent SYSTEM CLOCK. This allows DATA CLOCK operated higher lower speeds than SYSTEM CLOCK. best noise performance, data should transmitted DATA CLOCK should active during initial final data point collection. data being transmitted during initial final data point collection periods, DATA CLOCK should synchronized SYSTEM CLOCK, minimize added noise. DATA CLOCK connected SYSTEM CLOCK, that same clock used both; however, best noise performance, DATA CLOCK input should active only when data transmitted. This input used "daisy chain" output several DDC101s together minimize wiring. output register DDC101 acts shift register pass through output previously connected DDC101 units. this way, multiple DDC101 units convert simultaneously then sequence data serially same data line with common control line common data line DDC101 units. Digital power supply, +5VDC. VDD+ must less than equal VS+. Digital ground point. This output provides serial digital data clocked user controlled DATA CLOCK rate. Output data format 21-bit Binary Two's Complement word 20-bit Straight Binary word. data word transmitted first. When DATA TRANSMIT active DATA OUTPUT tri-states. This output activated when conversion complete remains active until DATA TRANSMIT input activated. OVERFLOW output signals each provide open collector output that overflow outputs from several DDC101s easily connected (wire ORed) together common pull-up resistor. They activated when input beyond acceptable range during conversion. Specifically, they activated when internal converter input digital filter exceeds full scale. They Cleared conversion clock cycle after DATA VALID high. DATA VALID used capture OVERFLOW data into external register.
SYSTEM CLOCK DATA CLOCK
DATA INPUT
VDD+, DIGITAL DIGITAL GROUND DATA OUTPUT
DATA VALID OVERFLOW- OVERFLOW+
DDC101
DESCRIPTIONS (CONT)
NUMBER NAME DATA TRANSMIT DESCRIPTION This input controls transmission data from serial register DDC101. activated anytime after DATA VALID becomes active. must remain active until data been collected from serial register(s) DDC101s data path. This input used read back current SETUP data. When this input held high, output from DATA OUTPUT data collected DDC101. When this input pulled low, internal shift register loaded with current SETUP data rising edge DATA CLOCK. This SETUP data shift register logically connected between DATA INPUT DATA OUTPUT pins read same that data output read. SETUP data read back does invalidate data already stored DDC101's serial register data being collected DDC101, although digital noise concerns should considered discussed DATA CLOCK. This input controls DDC101 SETUP. 12-bit digital word transmitted into this controls Acquisition Time, Oversampling, Multiple Integrations, Input Range Output Data Format. DDC101 reads SETUP code this after RESET SETUP input transitions from active inactive. SETUP code read into SETUP register positive data clock transitions following that transition. Resets SETUP register only, does reset balance DDC101. DDC101 reads SETUP input data after this input transitions from active (reset) inactive. This digital input that controls connection internal current source DDC101's input. TEST exercises DDC101 intended test functionality only. typical test input current 100nA ±20nA. quiescent current DDC101 increases approximately when TEST active. When TEST HIGH, internal current source current flowing into DDC101 input. When TEST LOW, current source disconnected from input. external -2.5V reference must connected REFERENCE pin. external reference allows multiple DDC101s same system reference optimum channel matching. external reference should filtered minimize noise contribution (see Figure 24). external capacitor 10µF should connected this node provide proper operation internal BUFFER BYPASS converter. REFERENCE connected internal reference buffer amplifier. internal reference buffer drives internal CDAC. This buffer output intended external use.
READ DATA/ SETUP
SETUP
RESET SETUP TEST
VREF
REFERENCE
SECTION TIMING CHARACTERISTICS
specifications with Unipolar input range, TINT 1ms, Current Input, Correlated Double Sampling enabled, Clock 2MHz, VREF -2.5V, +25°C ±5VDC, unless otherwise noted. SYMBOL DESCRIPTION Setup width, Continuous Conversion width, Asynchronous Conversion HIGH start next integration, Asynchronous Conversion Setup time RESET SETUP HIGH DATA CLOCK HIGH Setup time Setup Codes data valid before rising edge DATA Clock Hold time Setup Codes data valid after rising edge DATA Clock Propagation delay from rising edge SYSTEM CLOCK DATA VALID Propagation delay from DATA TRANSMIT DATA VALID HIGH Setup time DATA CLOCK DATA TRANSMIT Propagation delay from DATA TRANSMIT valid data Hold time that Data output valid after falling edge DATA CLOCK Propagation delay from DATA TRANSMIT HIGH Data Output tri-stated Propagation delay from falling edge SYSTEM CLOCK OVERFLOW+ OVERFLOW-cleared SYSTEM CLOCK pulse width HIGH SYSTEM CLOCK pulse width DATA VALID DATA TRANSMIT LOW, Single DDC101 (LxN-21) Clocks Clocks+t1 (M-1) Clocks+t1+100ns UNITS
DDC101
Continuous Integration Timing
TINT' TINT SYSTEM CLOCK Internal Oversampling Interval Internal Reset DATA VALID should coincident with negative clock. initiates oversampling period. Clock Periods oversample period initiates reset next integration. Clock Periods
Next integration begins when clock period wide Internal Reset ends.
Non-Continuous Integration Timing
SYSTEM CLOCK should coincident with negative clock. Internal Oversampling Interval Internal Reset DATA VALID initiates oversampling period. oversample period initiates reset. initiates Internal Reset.
When Internal Reset period ends, next integration begins.
FIGURE Conversion Timing Diagrams.
RESET SETUP DATA CLOCK (4MHz, setup) SETUP Read Read Read Input Range Read Output Format
ACQMSB
ACQLSB
FIGURE Input/Output Timing Diagram-SETUP Timing Diagram.
SYSTEM CLOCK DATA VALID DATA TRANSMIT
DATA TRANSMIT resets DATA VALID Out.
Data read rising falling edge Data Clock
DATA CLOCK (8MHz, data) DATA OUTPUT Output Disabled DDC(1) Output Enabled Last DDC(n) (n+1) Output Disabled
FIGURE DATA TRANSMIT Timing Diagram.
DDC101
TIMING DIAGRAMS (CONT)
SYSTEM CLOCK DATA VALID Read
Clear
OVERFLOW Read Clear
OVERFLOW
DATA VALID used latch data from overflow status outputs.
FIGURE OVERFLOW Monitoring Timing Diagram.
SYSTEM CLOCK
SYSTEM CLOCK
FIGURE System Clock Timing.
DDC101
TYPICAL PERFORMANCE CURVES
ELECTRICAL
System Clock 2MHz, ±5VDC, VREF -2.5V, Integration/Conversion, +25°C, unless otherwise noted.
SINAD 10kHz CONVERSION, UNIPOLAR INPUT 100µs Integration Time Acquisition Clocks Oversamples
(dB)
SINAD 1kHz CONVERSION, UNIPOLAR INPUT Integration Time Acquisition Clocks Oversamples
(dB)
-60dB
-60dB
1000 1500 2000 2500 3000 3500 4000 4500 5000 Input Frequency (Hz)
Input Frequency (Hz)
NOISE INPUT LEVEL (UNIPOLAR) WITH Integration Time Acquisition Clocks Oversamples
Noise (ppm, rms)
NOISE INPUT LEVEL (UNIPOLAR) WITHOUT Integration Time Oversamples 500pF
Noise (ppm, rms)
Input Level 100pF 500pF
100pF
Input Level
NOISE RESISTOR VALUE 1000 Level, Unipolar Input Acquisition Clocks
Charge Injection (ppm)
CHARGE INJECTION INPUT CAPACITANCE
Noise (ppm, rms)
Int.,
100µs Int.,
0.01
(pF) 1000
DDC101
TYPICAL PERFORMANCE CURVES (CONT)
ELECTRICAL
System Clock 2MHz, ±5VDC, VREF -2.5V, Integration/Conversion, +25°C, unless otherwise noted.
NOISE INPUT CAPACITANCE, UNIPOLAR INPUT
Noise (ppm, rms)
NOISE OVERSAMPLING, UNIPOLAR INPUT Integration Time Acquisition Clocks
Noise (ppm, rms)
Integration Time Oversamples
(pF) 1000 2000
Integration/Conversion
Oversamples
CHANGE TEMPERATURE
NOISE TEMPERATURE, UNIPOLAR INPUT Integration Time Acquisition Clocks Oversamples
Noise (ppm, rms)
(pA)
-2.0
-4.0
-6.0
-8.0 Temperature (°C)
Temperature (°C)
NOISE INTEGRATION TIME, UNIPOLAR INPUT Acquisition Clocks
INPUT OFFSET VOLTAGE INPUT CAPACITANCE 0.050
0.000 -0.050
Noise (ppm, rms)
VBIAS (mV)
0.100 -0.150 -0.200 -0.250
Integration Time (ms)
-0.300 (pF)
DDC101
TYPICAL PERFORMANCE CURVES (CONT)
ELECTRICAL
System Clock 2MHz, ±5VDC, VREF -2.5V, Integration/Conversion, +25°C, unless otherwise noted.
NEGATIVE PSRR FREQUENCY
PSRR (dB) PSRR (dB)
POSITIVE PSRR FREQUENCY Integration Time Acquisition Clocks Oversamples
Frequency (kHz) Integration Time Acquisition Clocks Oversamples
Frequency (kHz)
NEGATIVE PSRR FREQUENCY
PSRR (dB) PSRR (dB)
POSITIVE PSRR FREQUENCY 100µs Integration Time Acquisition Clocks Oversamples
Frequency (kHz) 100µs Integration Time Acquisition Clocks Oversamples
Frequency (kHz)
DDC101
SECTION DISCUSSION SPECIFICATIONS
INPUT DDC101 charge digitizing converter. level current output sources, such photosensors, directly connected input. input signal also voltage connected through user selected resistor. CHARGE INPUT maximum charge that captured integration DDC101 500pC. unipolar input range mode, maximum positive charge that collected integration 500pC. DDC101 small negative range unipolar mode -1.95pC. This small negative underrange included allow small amount leakage current from user's board sensor. bipolar input range, maximum positive charge that collected +250pC. maximum negative charge that collected -251.95pC. addition normal mode integration conversion, DDC101 configured user integrations conversion. When multiple integrations conversion mode chosen, DDC101 circuitry internally averages multiple integration cycles provide conversion result. This result lower noise because average multiple integrations. this mode, maximum total charge that captured DDC101 integrations 128,000pC. TEST CURRENT INPUT internal test current connected under user control DDC101's input. test current nominally 100nA will summed with applied external input signal. derived resistive network from positive power supply. test current intended test functionality only. TEST DDC101 controls current. When TEST HIGH, internal current source current flowing into DDC101 input. When TEST LOW, current source disconnected from input. With TEST active, positive power supply current increases approximately 1mA. FULL SCALE RANGE full scale range (FSR), which referenced specification table, difference between positive full scale charge negative full scale charge DDC101 integration cycle. Specifications such noise linearity, which specified percent FSR, referring value 500pC both unipolar bipolar input ranges. full scale input current given integration time will result full scale input charge. example unipolar
input range, input current 0.5µA integrated will result full scale charge 500pC. voltage inputs, input resistor chosen achieve proper full scale input current. example, full scale input, input resistor selected achieve full scale input current 0.5µA (1ms integration time). Noise 1.6ppm equal 1.6ppm 500pC 0.8fC 1.6ppm 0.5µA 0.8pA 1.6ppm 8µV. Thus, this instance, noise 1.6pA 8µV. unipolar input range, following table shows full scale input current required different integration times collect 500pC charge equivalent current values 5ppm FSR.
TINT 50ms 500µs 100µs 10nA 100nA 500nA 2ppm 0.02pA 0.2pA 10pA 5ppm 0.5pA 2.5pA 25pA
TABLE Integration Time (TINT) Full Scale Current (IFS) Full Scale 500pC Integration. CURRENT INPUT maximum average input current that captured DDC101 ±7.8µA. This current will result integration time 64µs unipolar input range 32µs bipolar input range. longer integration times, average input current must less. maximum input current limited slew update rate internal tracking logic CDAC. largest input current that DDC101 accurately track 7.8µA. Input currents larger than 7.8µA high speed current input pulses accurately captured digitized DDC101 with external input sensor capacitance DDC101 input. average current during complete integration cycle cannot exceed 7.8µA. Likewise, total charge input must exceed 500pC unipolar, 250pC bipolar during integration time. external user provided input capacitance, shown Figure will capture input signal charge input current limit temporarily exceeded during integration cycle. DDC101 will then transfer charge completely CINT based upon conservation charge. additional
Voltage across input must exceed ±2.5V. Analog Input, DDC101 Analog Common External user provided capacitance, CSOURCE, store current pulses.
FIGURE Current Pulse Input Capture.
DDC101
constraint voltage that appears DDC101 input, must exceed 2.5V. this voltage exceeded, charge lost integration result invalid. input voltage calculated:
i(t) i(t)dt therefore,
maximum input voltage based upon several selections input current input resistor unipolar input range. accuracy input resistor will directly Gain Error DDC101; drift input resistor will directly Gain Drift DDC101. Note that DDC101 output noise decreases increases. This because DDC101 noise gain decreases input resistance current noise decreases increases. This effect shown "Noise Resistor Value" typical performance curve.
INPUT RESISTOR, INTEGRATION TIME Full Scale Input Current Full Scale Voltage 50mV 500mV 0.5µA 100k 100M 500µs 500k 100µs 100k
example, with user supplied input capacitance 100pF, current pulse 100µA could stored without exceeding 2.5V applied input:
(100µA
100pF
current pulse must occur completely during part DDC101 integration time, DDC101 must still have time discharge input capacitance ground maximum rate 7.8µA before DDC101 triggered (through input) integration. addition, total charge integrated must 500pC less unipolar range. current pulse 100µA creates 200pC charge. VOLTAGE INPUT SPECIFICATIONS DDC101 charge digitizing device. With user provided input resistor, DDC101 digitize voltage inputs. general charge/current input specifications apply voltage input situation. specification table shows typical noise DDC101 including effects input resistor, RIN. input DDC101 virtual ground. voltage input causes current, flow into input through shown Figure maximum input current determined integration time selected. Table shows
Current Input Configuration
TABLE Example Input Resistor Values Unipolar Input Range. UNIPOLAR LINEARITY ERRORS innovative design techniques, absolute level linearity error DDC101 improves input signal level decreases when used unipolar input mode. Therefore, unipolar input mode, integral linearity DDC101 specified small base error plus percentage reading error percentage full scale range. best-fit straight line method used determine integral linearity. different best-fit straight lines used unipolar integral linearity specifications. bipolar input mode, linearity specified only percentage full scale range. illustrate improvement unipolar mode linearity error, Figure shows maximum unipolar integral linearity error (ILE) DDC101 function input signal level. maximum integral linearity error ±0.0244% reading ±2.5ppm (ILE unipolar input -1.95 ±0.0244% reading ±3.0ppm FSR). Thus, maximum input level 0.0005%FSR.
Analog Input,
Linearity Error FSR)
DDC101 Analog Common
Data
0.01
Voltage Input Configuration
0.001
Input Resistor
Analog Input, DDC101 Analog Common
Data
0.0001 0.001
0.01
Unipolar Input Level FSR)
FIGURE DDC101 Input Configurations.
FIGURE Maximum Unipolar Integral Linearity Error Relative Full-Scale, Converted From Reading Specification.
DDC101
NOISE noise DDC101 improves input signal level decreases, thus very level signals resolved. Noise shown specification table level inputs. unipolar input range, DDC101 noise level inputs dominated comparator noise gained output; full scale inputs, noise dominated converter noise. noise level inputs function input capacitance; noise full scale relatively independent input capacitance. bipolar input operation, noise dominated converter noise higher than full scale unipolar noise. BIPOLAR INPUT ACCURACY Linearity-As bipolar input device, linearity DDC101 specified percentage full scale range that does improve with lower input signal levels. Performance generally limited linearity unit when operated bipolar input mode. Noise-In general, noise important linearity when determining total error. output noise DDC101 bipolar mode peaks midscale (zero input signal level). Output noise lower inputs above below zero. RESET CHARGE ERROR reset charge error (typically less than 250fC) offset error that could result from offset voltage, charge injection kT/C errors. DDC101 eliminates effects reset charge errors with correlated double sampling. BIAS VOLTAGE DDC101 generates small bias voltage (typically 500µV) input. This voltage impressed sensor that connected input. bias voltage actual virtual ground voltage DDC101. DDC101 input comparator circuitry includes autozero circuit which eliminates this offset internally that does produce output error. GAIN SENSITIVITY VREF DDC101 gain dependent upon external reference voltage, VREF. change value VREF will seen directly proportional change gain DDC101. FREQUENCY RESPONSE DDC101 sampling system whose transfer function three separate frequency components. These components multiplied together make total frequency characteristic DDC101. three components are: Basic Integration This characteristic sin(x)/x response basic integration function. This response controlled integration time DDC101.
Oversampling This pass filter characteristic digital filter's oversampling. This response reduces broadband noise input signal DDC101. Broadband noise decreases number oversamples increases. Multiple Integrations This pass filter characteristic that results when digital filter used average multiple integrations. This will determine primary response DDC101 more integrations internally averaged. Section more details.
SECTION DETAILED THEORY OPERATION
INTEGRATION CYCLE integration cycle, illustrated Figure includes Acquisition Time, Initial Data Point Sampling, Tracking Interval, Final Data Point Sampling. Acquisition Time clock periods. first clock cycle Acquisition Time used reset integrating capacitor, CINT, zero from previous integration. balance Acquisition Time insures that DDC101 system accurately tracking input signal prior initial data point acquisition. Close-ups Reset Acquisition time shown Figures Initial Data Point then sampled times. Integration cycle time consists primarily Tracking Interval during which time DDC101 "tracks" integration input signal. Tracking Interval followed measurement Final Data Point with same user selected number samples, user selectable. entire integration cycle consists clock periods controlled user. DDC101 operates continuous non-continuous integration modes. continuous mode, integration follows another with delay from integration beginning next conversion. noncontinuous mode, each integration started separately under user control. Final Data point Start (FDS) input primary user control integration cycle. input controls integration cycle start next integration cycle both continuous non-continuous integration modes. Measurement final data point samples begins when input activated. CONTINUOUS INTEGRATION MODE continuous integration mode, "Final Data Point Start" command (using pin) initiates measurement final data point samples. next integration cycle begins immediately after final data point sampling
DDC101
Aquisition Time,
Oversampled Initial Data Point
Time, Clock Cycles
Tracking Interval
Final Data Point Start
Measurement Time Digital Output DDC101 digital output precise integration input during measurement time.
Oversampled Final Data Point
FIGURE Equivalent Integrator Output Single Integration.
Aquisition Time
Time, Clock Cycles
Oversampled Initial Data Point Reset Previous Integration Tracking Interval
Digital Output
FIGURE Close-up Initial Oversampled Data Point DDC101. been completed; this occurs clock periods after transition "ON". Acquisition, Initial Data Point Tracking next integration follow automatically. DDC101 continues Tracking mode until next command initiates measurement final data point samples. command needed each integration cycle. continuous integration mode, pulse width must less than clock periods. pulse
held past this time clock periods, DDC101 will reset non-continuous mode (see also Figure continuous mode operation, tracking logic DDC101 "remembers" integration rate previous integration begins next integration rate previous integration. This allows faster acquisition signal next integration.
DDC101
Acquisition Time, Actual Integration Ideal Integration
Reset Previous Integration
Signal Acquired
Correlated Double Sampling implemented DDC101 subtracting Initial Data Point from Final Data Point. Thus, error correction updated automatically each integration. When operating unipolar input range, functions with either output data format-straight binary binary two's complement. When operating bipolar input range, functions with binary two's complement output data format only. errors that removes charge injection, kT/C DDC101 input voltage offset. These errors very difficult eliminate equivalent analog circuits. Charge injection errors result from charge that transferred through reset switch into integration capacitor. kT/C errors switching errors noise resistance reset switch. DDC101 voltage offset errors input offset input comparator. Both initial offset offset drift with time temperature corrected since correction performed each integration cycle. SINGLE CYCLE INTEGRATION DDC101 acquires charge integrating input current specific time (T). That
FIGURE Close-up Reset Acquisition Time DDC101.
Integration
Integration
Final Oversampled Data
Initial Oversampled Data Acquisition Reset
Tracking Interval
Final Data Point Start
FIGURE Close-up Integration Cycle Beginning Next. NON-CONTINUOUS INTEGRATION MODE non-continuous integration mode, controls start final data point samples integration discussed above. this mode, however, also used control start integration cycle asynchronously with previous integration. When transitions "ON", collection final data point samples begins. each integration, DDC101 automatically resets integration capacitance. remains "ON" past integration, DDC101 will stay integration reset state until transitions "OFF". Holding "ON" past integration will also reset DDC101's tracking logic zero integration rate. non-continuous integration mode, initial data point measurement less accurate since DDC101's internal tracking logic reset beginning integration tracking accurate initial data point measurement. this situation, Correlated Double Sampling (CDS) operation advantageous. INTERNAL ERROR CORRECTION DDC101 uses techniques gain optimum performance. removes internal DDC101 errors which occur given integration cycle such charge injection, kT/C, DDC101 offset errors. Correlated Double Sampling user selectable. recommended most continuous measurement applications.
DDC101 acquires 500pC full scale charge integration cycle unipolar input range, approximately ±250pC full scale charge bipolar input range. Therefore, DDC101, maximum values calculated. Unipolar Input Range Bipolar Input Range 500pC TINT ±250pC ±IFS TINT Where full scale input current TINT integration time DDC101. Examples TINT that equal 500pC ±250pC shown following tables. maximum average input current that DDC101 integrate 7.8µA. This results minimum integration time 64µs unipolar inputs 32µs bipolar inputs. Further flexibility possible with multiple integration cycles conversion described following text. INPUT RANGE Unipolar Input Range unipolar input range, range charge each integration cycle from positive full scale +500pC slightly negative charge -1/256 (approximately -0.4%) positive full scale charge. This +500pC -1.95pC. negative charge measurement capability allows level board parasitic leakages. Bipolar Input Range bipolar input range, range charge each integration cycle from positive full scale +250pC negative full scale -251.95pC.
DDC101
10nA 100nA 7.8µA
TINT 500ms 50ms 500µs 100µs 64µs
Conversion Cycle
Integration
Integration Time
TABLE III. Input Current Integration Time Examples Maximum Charge. Unipolar input range maximum charge 500pC.
±IFS
10nA 100nA 2.5µA 7.8µA TINT 250ms 25ms 2.5ms 250µs 100µs 32µs
CDAC Charge data output conversion cycle with integrations/conversion
TABLE Input Current Integration Time Examples Maximum Charge. Bipolar input range maximum charge ±250pC. MULTIPLE INTEGRATIONS CONVERSION CYCLE more than 500pC, unipolar ±250pC, bipolar) charge must integrated conversion cycle, DDC101 user programmed multiple integrations conversion cycle. This feature used provide longer conversion periods specific input current other than shown previous table. integration cycles forming conversion cycle continuous non-continuous. number integrations conversion cycle, 128, 256. multiple integrations automatically averaged DDC101 that conversion result output total conversion cycle. Note that each integration requires individual control signal. example, then four signals conversion required. FINAL DATA POINT CONFIGURATION LIMITS each conversion cycle, maximum number final data points which collected 256. This means that extremes, DDC101 setup perform integration cycle with oversamples, DDC101 setup perform integration cycles with sample integration cycle. total number integrations, multiplied number samples final data point, must less. example, integration cycles, used, number samples final data point must less. NOTE: When used, initial data points impose additional conversion sampling limitations. FREQUENCY RESPONSE DDC101 charge digitizing Converter sampled system whose frequency response three separate components. These components multiplied together make total frequency characteristic DDC101. three frequency response components shown below. Each
FIGURE Conversion Cycle with Integrations.
INTEGRATIONS CONVERSION
10nA 10nA 10nA 10nA 10nA 10nA 10nA 10nA 10nA
CONVERSION TIME 50ms 100ms 200ms 400ms 800ms 1.6s 3.2s 6.4s 12.8s
CHARGE/ CONVERSION 500pC 1000pC 2000pC 4000pC 8000pC 16000pC 32000pC 64000pC 128000pC
TABLE Integrations/Conversion Conversion Time. Example multiple integrations with unipolar input range. individual component sinc (sinx/x) frequency response function. Basic Integration This characteristic sin(x)/x response basic integration function. This response controlled measurement time DDC101, TMEAS; Figure Oversampling This pass filter characteristic digital filter's oversampling. This response reduces broadband noise input signal DDC101. Broadband noise decreases number oversamples increases. This response controlled number oversamples, Figure Multiple Integrations This pass filter characteristic that results when digital filter used average multiple integrations. This will determine primary response DDC101 more integrations internally averaged. This response controlled total conversion time DDC101; Figure Input frequencies multiplied DDC101 frequency response. Nyquist frequency fCONV/2, where fCONV DDC101 conversion rate. highest frequency that reconstructed from output data fCONV/2. Input frequencies above Nyquist multiplied DDC101 frequency response then aliased into fCONV/2.
DDC101
Basic Integration Frequency Response sin(x)/x basic integration characteristic controlled digital filter's measurement time (TMEAS). measurement frequency, fMEAS l/TMEAS. input frequency response DDC101 down -3dB fMEAS/2.26 with null fMEAS. Subsequent nulls harmonics 2fMEAS, 3fMEAS, 4fMEAS, etc. shown frequency response curve below. This characteristic often used eliminate known interference setting fMEAS harmonic exactly frequency interference. Table illustrates frequency characteristics DDC101 integration function various measurement times. example, 2272, 256: TMEAS (N-M-K)/fCLK (2272256-16)/2MHz fMEAS 1kHz. TINT 2272/2MHz 1.14ms; fCONV l/TINT 880Hz.
MEASUREMENT TIME 100µs 10ms 16.66ms 20ms -3dB FREQUENCY 4.42kHz 442Hz 44.2Hz 26.5Hz 22.1Hz fMEAS 10kHz 1kHz 100Hz 60Hz 50Hz
Nyquist (fCONV/2)
Gain (dB)
-20dB/decade Slope
fCONV 0.1fMEAS fMEAS Frequency 10fMEAS
FIGURE Basic Integration Frequency Response. 1/TOS. oversample time, TOS, M/fCLK. fCLK 2MHz, approximately 7.8kHz. Subsequent nulls harmonics 2fOS, 3fOS, 4fOS, etc. -3dB point fOS/2.26. Table illustrates DDC101 oversampling frequency characteristics with approximate values -3dB frequency. oversampling frequency response graph shown below Figure This figure shows frequency response oversamples with fCLK 2MHz slope attenuation curve decreases approximately 20dB/decade.
OVERSAMPLES -3dB FREQUENCY 3.5kHz 6.9kHz 13.9kHz 55kHz 7.8kHz 15.6kHz 31.2kHz 125kHz
TABLE Basic Integration Frequency Response Examples. Oversampling Frequency Response oversamples initial final data points create oversampling sin(x)/x type pass filter response. oversampling function reduces broadband noise input signal DDC101. Broadband noise reduced approximately proportion square root number oversamples, example, conversion with oversamples will have approximately noise conversion with oversamples (32/128 1/2) oversampling pass filter response creates null
TABLE VII. Oversample Frequency Response Examples.
Normalized DDC101 Frequency Response normalized frequency response, H(f), DDC101 that applied input signal consists product three frequency response components:
Basic Integration
sin(fM/ sin(fLN/
Msin
Oversampling
Lsin
Multiple Integrations
Linear Phase
Where:
fCLK (N-M-K)/fCLK signal frequency system clock frequency, typically 2MHz total number clock periods each integration time, TINT N/fCLK, TINT DDC101 CDAC's integration time number oversamples oversampled data point number clocks used acquisition time digital filters measurement time, TMEAS, (TMEAS TINT -(M+K)/fCLK)
oversample time, M/fCLK LN/fCLK total conversion time multiple integrations, TCONV DDC101's transfer response linear phase characteristic indicated exponential term.
DDC101
Gain (dB) 100k Frequency (Hz)
fCONV Frequency (Hz)
1000 fCONV 31Hz
FIGURE Oversampling Frequency Response (fCLK 2MHz). Multiple Integration Frequency Response DDC101 operated multiple integrations conversion mode operation, additional sin(x)/x type pass filter created. filter creates initial null frequency conversion frequency, fCONV DDC101 multiples fCONV. -3dB point this filter also fCONV/2.26. conversion time, TCONV, integration times multiple integrations that averaged together DDC101. TCONV LN/fCLK. fCONV l/TCONV. multiple integrations conversion used, this filter will dominant frequency filter DDC101. Table VIII shows examples conversion time frequency different parameter selections. Figure shows example frequency response Multiple Integrations. case Figure integration time 500µs 1000 clock periods) integrations conversion.
INTEGRATION TIME 10ms 10ms 10ms 10ms 10ms CONVERSION -3dB TIME FREQUENCY 16ms 64ms 256ms 20ms 80ms 160ms 640ms 2560ms 221Hz 55Hz 27.5Hz 6.9Hz 1.73Hz 22.1Hz 5.5Hz 2.75Hz 0.69Hz 0.173Hz
FIGURE Multiple Integration Frequency Response Example. Signal Noise-The noise input signal filtered reduced manner similar DDC101 noise reduction through integrating oversampling functions DDC101. Figures show frequency response DDC101 product basic integration oversampling frequency response different values both examples, integration time 1ms, only difference number oversamples, Figure oversamples used; Figure oversamples used. first null frequency fMEAS subsequent nulls multiples fMEAS. first example with larger number oversamples 256) clearly reduces high frequency noise more than second example with 256, 7.8kHz, fMEAS 1.16kHz, -3dB frequency 507Hz. 62.4kHz, fMEAS 1.02kHz -3dB frequency 453Hz.
fCONV 500Hz 125Hz 62.5Hz 15.6Hz 3.91Hz 50.0Hz 12.5Hz 6.25Hz 1.56Hz 0.39Hz
2000
TABLE VIII. Multiple Integration Time Examples. System Noise implications noise digital output DDC101 consists system noise that included analog input signal noise from DDC101. DDC101 Noise-The noise DDC101 includes frequency broadband noise. frequency noise reduced integrating function function DDC101. This reflected basic integration frequency response multiple integration frequency response. broadband electronic noise reduced primarily oversampling function DDC101
Gain
Frequency (Hz) 100k
FIGURE Product Frequency Response Basic Integration Oversampling: Integration Time, Oversamples.
DDC101
2000
Frequency (Hz) 100k
SYSTEM SETUP After power Reset System signal inputs should held (active), while SETUP register loaded user. After SETUP register loaded, Reset System input should transition inactive while input remains active. should transition inactive start operation. Thereafter, Reset System should stay inactive should used control each integration cycle. SETUP INPUT Software Control Many options DDC101 through serial stream transmitted user into SETUP Input pin. 12-bit word transmitted into SETUP Input used following four options, sequence: Acquisition Time Control, bits Oversampling Control Samples/Integration, Multiple Integration Control Integrations/Conversion, Unipolar Bipolar Input Range bits bits
FIGURE Product Frequency Response Basic Integration Oversampling; Integration Time, Oversamples. Figure shows frequency response DDC101 ideal integrator with same integration time. this comparison, DDC101 greater bandwidth first null, also greater band attenuation which reduces broadband noise significantly. desired, frequency response ideal integrator produced passing DDC101 output through external digital filtering function which frequency response from Nyquist
Gain
Output Format Total SETUP bits Figure SETUP Timing Diagram. Acquisition Time Control, This signal sets acquisition time clock periods) controls Correlated Double Sampling. acquisition time occurs start each integration. acquisition time control four options: CDS", clock periods. typical continuous integration applications, recommended. acquisition time always begins with clock period reset. This reset clock period followed clock periods signal acquisition. Correlated Double Sampling activated initial acquisition time clock periods. Correlated Double Sampling disabled Initial Data Point acquired CDS" selected.
RESET CLOCKS ACQUISITION CLOCKS
MEAS sin(f sin(f sin(f MEAS sin(f
This effect further attenuating undesired signals (noise) outside "passband", further increasing signalto-noise ratio DDC101 closely emulating ideal integrator's signal accumulation characteristics.
Comparison DDC101 with Ideal Integrator
Gain (dB)
Nyquist (fCONV/2)
DDC101 with 2000; 256; TCONV TINT 2MHz/N fMEAS 2MHz/(N-M-K) 1.16kHz
CDS"
Disabled Enabled Enabled Enabled
Ideal Integrator with TINT
TABLE Acquisition Time Control, When Correlated Double Sampling activated, DDC101 acquires initial data point error correction part each conversion. conversion cycle, initial data point subtracted from final data point. errors that corrected with charge injection, kT/C noise, DDC101 voltage offset. When Correlated Double Sampling deactivated, initial data point taken.
fCONV fMEAS Frequency (Hz)
100k
FIGURE Comparison DDC101 with Ideal Integrator.
DDC101
When operating unipolar input range, functions with either output data format-straight binary binary two's complement. When operating bipolar input range, functions correctly only with binary two's complement output data format. Oversampling Control Samples/Integration, This control sets number samples, used DDC101 oversample initial final data points. these values: 128, 256. Broadband noise conversion reduced roughly proportion square root Therefore, conversion with oversamples will have broadband noise conversion with oversamples. previous frequency response discussion. Multiple Integration Control, This control sets number integrations conversion cycle, used reduce data rate, increase magnitude input signal range, and/or reduce noise. product must less. Output Format output formats available either unipolar bipolar input ranges: Binary Two's Complement (BTC) Straight Binary. UNIPOLAR INPUT RANGE Binary Two's Complement, output data format, output word 21-bit Two's Complement word. first sign followed Most Significant (MSB), etc. output range +100%FS -0.4%FS, where 500pC.
CODE 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 0000 0000 0000 INPUT SIGNAL +100%FS +100%FS -1LSB +1SLB Zero -1LSB -0.4%FS +500pC
BIPOLAR INPUT RANGE Binary Two's Complement, output data format, output word 21-bit Two's Complement word. first sign followed Most Significant (MSB), etc. output range +100%FS -100.8%FS, where 250pC. bipolar input range, output code table changes with Correlated Double Sampling (CDS). (There difference with without output code table when using unipolar input range.)
CODE 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 0001 1000 0000 0000 0000 0000 0111 1111 1111 1111 1111 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 1111 1111 0000 0000 0000 INPUT SIGNAL +100%FS +100%FS -1LSB +1LSB Zero -1LSB -100%FS 1SLB -100%FS -100.8%FS +250pC
-250pC -251.95pC
TABLE XII. Code Table Bipolar Input Range without CDS.
CODE 0111 1111 1111 1111 1111 0111 1111 1111 1111 1110 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1000 0000 0000 0000 0001 1000 0000 0000 0000 0000 0111 1111 0000 0000 0000 INPUT SIGNAL +100%FS +100%FS 1LSB +1LSB Zero -1LSB -100%FS 1LSB -100%FS -100.8%FS +250pC
-250pC -251.95pC
TABLE XIII. Code Table Bipolar Input Range with CDS. Straight Binary output data format with bipolar input range, output 20-bit straight binary word. first Most Significant (MSB), etc. output range +100%FS -100%FS which +100%FS represents positive full scale -100%FS represents negative full scale. When using straight binary output data format bipolar input range, CDS. This will cause negative overflow occur.
CODE 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 0001 1000 0000 0000 0000 0000 0111 1111 1111 1111 1111 0000 0000 0000 0000 0000 INPUT SIGNAL +100%FS +100%FS 1LSB +1LSB Zero -1LSB -100%FS +250pC
-1.95pC
TABLE Code Table-Unipolar Input Range. Straight Binary output data format, output 20-bit straight binary word. first Most Significant (MSB), etc. output range +99.6%FS -0.4%FS which +99.6%FS represents positive full scale -0.4%FS represents minimum input.
CODE 1111 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0001 0000 0000 0001 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000 INPUT SIGNAL +99.6%FS +99.6%FS -1LSB +1LSB Zero -0.4%FS 498.05pC
-250pC
TABLE XIV. Straight Binary Code Table Bipolar Input Range without CDS. SETUP INPUT CODE Acquisition Time Control-K bits
CODE RESULT Reset clock period, clock period Acquisition Time, disabled, initial data point, Reset clock period, clock period Acquisition Time Reset clock period, clock period Acquisition Time Reset clock period, clock period Acquisition Time
-1.95pC
TABLE Straight Binary Code Table Unipolar Input Range.
10(1)
NOTE: Recommended continuous integration mode.
DDC101
Oversampling Control Samples/Integration-M bits
CODE 0000 0001 0010 0011 0100 0101 0110 0111 1XXX SAMPLES INTEGRATION
Guard Pattern
DDC101
Analog Common Analog Input Analog Common
FIGURE Board Layout Showing "Guard" Traces Surrounding Analog Input Traces. Power Supplies ±5VDC supplies DDC101 should bypassed with 10µF solid tantalum capacitors 0.1µF ceramic capacitors. supplies should each have 10µF solid tantalum capacitor central point board. Each DDC101 power supply lines (VS+, VS-, VDD+) should have separate 0.1µF ceramic capacitor placed close DDC101 package possible. digital power supply voltage, VDD+ must equal less than analog power supply voltage, VS+. analog power supply, VS+, connected pins these pins should hardwired together printed circuit board pins best performance. VDD+ should quiet possible with minimal noise coupling. particularly important eliminate noise from VDD+ that non-synchronous with DDC101 operation. Figure illustrates acceptable ways supply VDD+ power DDC101. first case shows separate +5VDC supplies VDD+ VS+. second case shows VDD+ power supply derived from supply used DDC101 Evaluation Fixture Device Under Test (DUT) board.
Multiple Integration Control Integrations/Conversion-L bits
CODE 0000 0001 0010 0011 0100 0101 0110 0111 1XXX INTEGRATIONS CONVERSION
Input Range
CODE INPUT RANGE Unipolar Bipolar
Output Format
CODE OUTPUT FORMAT Binary Two's Complement Straight Binary
SECTION APPLICATIONS INFORMATION
BASIC PRINTED CIRCUIT BOARD LAYOUT with precision circuit, careful printed circuit layout will ensure best performance. Make short, direct interconnections avoid stray wiring capacitance-particularly analog input pin. Digital signals should kept from analog input signals possible board. Leakage currents between board traces exceed input bias current DDC101 care taken. circuit board "guard" pattern analog input board trace that connects analog input recommended. guard pattern reduces leakage effects surrounding analog input trace with impedance analog ground. Leakage currents from other portions circuit will flow harmlessly impedance analog ground rather than into analog input DDC101. Analog ground pins placed either side analog input DDC101 package allow convenient layout guard patterns. Figure illustrates guard patterns protect analog input.
VDD+
10µF 0.1µF DDC101
10µF 0.1µF
Separate +5VDC Supplies 10µF 0.1µF DDC101
0.1µF
+5VDC Supply
FIGURE Positive Supply Connection Options.
DDC101
-5VDC
10µF
Reference Buffer Bypass
0.1µF
ANALOG ANALOG COMMON ANALOG INPUT ANALOG COMMON VS+, ANALOG VS+, ANALOG
VREF
10µF
REF1004 -2.5 -2.5V 10µF Reference Noise Filter Reference Bias Resistor
Analog Input +5VDC Guard 10µF
0.1µF
0.1µF VDD+, DIGITAL 24-Lead SOIC view
DIGITAL GROUND
Analog Common Digital Common
FIGURE Example Basic DDC101 Circuit Connections. Reading Data Output Data from previous conversion read time after DATA VALID output activated before next conversion. Data held internal serial shift register until next conversion. data must completely read before next conversion will overwritten with data. Recommended Setup following Setup parameters recommended, general, with DDC101 with integration times longer. Multiple integrations conversion, where practical, will provide lowest noise illustrated typical performance curves. Measurement Time Calculation
FUNCTION Acquisition Clocks, Oversamples, RECOMMENDED Enabled
time between "Final Data point Start" commands Integration Time, TINT. Measurement Time, TMEAS, Integration time reduced Acquisition Time Oversampling Time, TOS. TMEAS TINT TACQ TOS. When used; TOS, oversampling time, time required collect data point clock periods). Each group samples averaged with result midpoint each sample group. Therefore, with CDS, clock periods. This shown Figure calculations Measurement Time shown
USER CONTROLLED
FUNCTION Acquisition Time, Initial Data Point Samples, M(1) Tracking Interval Final Data Point Samples, M(1)
CLOCK CYCLES 32,64, 128, Variable 128,
Continuous Integration Cycle consists Acquisition Time, Initial Data Point Collection, Tracking Interval, Final Data Point Collection. user select these functions illustrated Table
NOTE: Will same mode, initial Data Point Samples nonCDS mode.
TABLE Components Integration Cycle.
DDC101
Aquisition Time,
Oversampled Initial Data Point
Time Clock Cycles
Tracking Interval
Final Data Point Start
Measurement Time Digital Output DDC101 digital output precise integration input during measurement time.
Oversampled Final Data Point
FIGURE DDC101 Equivalent Integrator Output Single Integration with CDS.
USER SETTING (Clock Cycles) MEASUREMENT (Calculated) USER SETTING (Clock Cycles) MEASUREMENT (Calculated)
FUNCTION Integration Time (TINT) Acquisition Time (TACQ) Initial Data Point Samples, Measurement Time Final Data Point Samples,
TIME
FUNCTION Integration Time (TINT) Acquisition Time, (TACQ) CDS" Initial Data Point Samples
TIME
64µs 928µs
None
0.5µs 967.5µs
Measurement Time Final Data Point Samples, 64µs
64µs
TABLE XVI. Measurement Time with CDS. below: with Correlated Double Sampling (CDS) other without CDS. Each example assumes that recommended system clock frequency 2MHz used that time between "Final Data point Start" commands, (the integration time, TINT) 1ms. Example with CDS. Measurement Time with calculated Integration Time (TINT) less TACQ TOS. TOS, oversampling time, Initial Data Point time plus Final Data Point time since each group samples averaged with result midpoint each sample group. Therefore, Measurement Time 32)µs 928µs. Example without CDS. Measurement Time without calculated Total Integration Time (TINT) less TACQ TOS. TOS, oversampling time, Final Data Point time since this group samples averaged with result midpoint sample group. Therefore, Measurement Time -(0.5 32)µs 967.5µs.
TABLE XVII. Measurement Time without CDS. Input Current Calculation following formula calculates input current from actual output:
With CDS:
output 500pC MEAS output 500pC clock periods clock periods
Without CDS:
output 500pC MEAS output 500pC clock periods clock periods
DDC101
DATA INPUT
DDC101
DATA OUTPUT
DATA INPUT
DDC101
DATA OUTPUT
DATA INPUT
DDC101
DATA OUTPUT
DATA TRANSMIT
DATA TRANSMIT
DATA TRANSMIT
FIGURE Daisy Chained DDC101s.
DDC101 DATA INPUT DATA OUTPUT DATA TRANSMIT
DDC101 DATA INPUT DATA OUTPUT DATA TRANSMIT Data Output
DDC101 DATA INPUT DATA OUTPUT DATA TRANSMIT Enable
FIGURE DDC101 Parallel Operation. MULTIPLE DDC101 OPERATION Multiple DDC101 units connected serial parallel configuration illustrated Figures DATA OUTPUT used with DATA INPUT "daisy chain" output several DDC101 units together minimize wiring; this mode operation, serial data output shifted through multiple DDC101s (Figure 26). DATA OUTPUT high impedance state until DATA TRANSMIT active. this way, several DDC101 units connected parallel enabled DATA TRANSMIT line (Figure 27). DDC101 EVALUATION FIXTURE DEM-DDC101P-C Evaluation Fixture highly recommended initial evaluation DDC101. designed ease use. only additional equipment required complete evaluation performance DDC101 compatible with graphics, parallel interface port, laser printer (optional), ±5VDC power supply, signal source. DEM-DDC101P-C software mouse compatible retrieves data from DDC101s easy read, graphical format screen. DEM-DDC101P-C Evaluation Fixture includes Interface Board (with necessary parts), DDC101 Board, 25-pin ribbon connector 34-pin ribbon connector. Interface Board makes timing commands access from DDC101 test board possible through provided software. Data sheet, LI-439, provides complete information describing evaluation fixture.
DDC101
FIGURE Photo DEM-DDC101P-C Evaluation Fixture.
Cable
Interface Board Your Analog Input Board Assembly
Cable
±5VDC
+5VDC
Power Supply
FIGURE DEM-DDC101P-C Evaluation Fixture Connection Diagram.
DDC101
PACKAGE OPTION ADDENDUM
www.ti.com
6-May-2005
PACKAGING INFORMATION
Orderable Device DDC101U
Status ACTIVE
Package Type SOIC
Package Drawing
Pins Package Plan
Lead/Ball Finish NIPDAU
Peak Temp Level-3-220C-168
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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