IEEE-1394a Link Layer Controller Core Conforms implements functio

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IEEE-1394a Link Layer Controller Core Conforms implements functio

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C1394A
IEEE-1394a Link Layer Controller Core
Conforms implements functionality IEEE 13941995 IEEE 1394a-2000 standards Based Texas Instruments TSB12LV32 General Purpose Link Layer controller Supports device data transmission 400, Mbps Includes 32-bit AMBA Slave microprocessor interface (other standard interfaces available)
C139A core implements link layer controller high-speed, high-bandwidth serial known commercially FireWireand i.LinkTM. core conforms IEEE 1394-1995 1394a-2000 specifications. similar popular Texas Instruments TSB12LV32 General Purpose Link Layer Controller, includes 32-bit interface easy connection with AMBAbus host system. (AHB other standard interfaces also available.) C1394A interface with 1394-compliant physical layer (PHY) device, includes easy-to-apply C-language software functions basic operations (options provide serial management transaction layer). FPGA-proven been exercised FireWire video camera demonstration system. ASIC results show require less than 39,000 gates. C1394A testable, microcode-free design developed reuse ASICs FPGAs. fully synchronous internal three-state buses. complete verification environment helps designers verify functioning compliance core, additional aids system-on-chip simulation available.
Fast, direct, 16-bit Data Mover interface supervises data flow from external source Integrated receive transmit FIFOs configurable size Validates data with 32-bit generation transmission 32-bit checking reception Capable Manager, Isochronous Resource Manager Cycle Master modes Able receive incoming isochronous traffic, supports hardware filtering/acceptance (more available upon request) Supports IEEE 1394 acceleration enhancement methods selective enabling/disabling IEEE 1394a functions Supports multi-speed concatenation fairness protocol Uses Annex standard interface with compliant Dedicated software functions support basic operations Additional software functions available extra options IEEE-1394a compliant Transaction Layer Serial Management (SBM) software functions prepared language easy with processor Debug feature introduces errors during transmission Optional System-On-Chip simulation support provides aworking physical layer emulates traffic other nodes FPGA-proven, offering competitive implementation results, e.g., 38,800 ASIC gates host frequency
Applications
System integration straightforward, core readily interfaces with AMBA compliant host processor control 1394-1995 1394a-2000 compliant physical level (PHY) device connection cable. 1394 facilitates convergence computers, peripherals, consumer products. Typical applications include camcorders, televisions, digital cameras, external hard drives, scanners, printers.
Block Diagram
August 2004
Functional Description
operations C1394A core divided into several blocks shown previous diagram.
Implementation Results
following typical performance utilization results using Lattice device.
Lattice Device LFEC20E-5 RegSysMEM External Speed Slices isters EBRs I/Os (throughput) >400 3648 4100 Mbits/sec.
Control Function Registers
Incorporates 32-bit host interface (AMBA APB) control registers. supports access internal FIFOs through which host receives transmits packets: GRF, General Receive FIFO, ATF, Asynchronous Transmit FIFO. host cannot transmit isochronous packets.
LUT-4s 6371
Support
core delivered warranted against defects three years from purchase. Thirty days phone email technical support included, starting with first interaction. Additional maintenance support options available.
DMDR Data Mover with Data Router
Supervises dataflow connected device organizes data into packets. Independently supplies receives data processor interface isochronous asynchronous packets. transmitting, gets packets from feeds this data into LinkCore. receiving, gets packets from LinkCore feeds them into GRF. DMDR configured receive type data traffic limited filtering feature. (This allows core check additional user fields data headers decide whether packet should GRF). Once host processor configures DMDR handle data transmissions independent that processor, notifying only when error detected. DMDR's design also makes straightforward application-specific modules that cooperate with DMDR, such digital camera interface.
Verification
core been verified through extensive simulation rigorous code coverage measurements. been FPGAproven, exercised with FireWire video camera demonstration system.
Deliverables
core includes everything required successful implementation: Post-synthesis EDIF netlist (firm core) optimized specific Lattice device. source code (soft core) also available. example chip implementation, which uses C1394A sample system shows build connect external logic tri-state buffers Sophisticated Testbench including external FIFOs, buffers, models interfaces, core Simulation script, vectors, expected results, comparison utility Synthesis (soft) place route (firm) script Comprehensive user documentation, including detailed specifications system integration guide
LinkCore
Responsible executing low-level transmissions time-critical operations. This includes calculation checking, observing generating protocol events, checking generating acknowledge signals.
Link2PHY
interface between LinkCore external Physical Layer (PHY). core satisfies Annex standard operate with physical layer device compliant with IEEE 1394-1995 1394a-2000 regulations.
Software
dedicated software included with core supports basic operation. Optional software available provide IEEE-1394a Transaction Layer Serial Management (SBM) function. C1394A software written readily ported processor.
CAST, Inc. Stonewall Court Woodcliff Lake, 07677 201-391-8300 201-391-8694 Copyright CAST, Inc. 2004, Rights Reserved. Contents subject change without notice. Trademarks property their respective owners.
http://www.latticesemi.com

IEEE-1394a Link Layer Controller Core Conforms implements functio

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