PALCE22V10 Family 24-Pin CMOS Versatile Device DISTINCTIVE C

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PALCE22V10 Family 24-Pin CMOS Versatile Device DISTINCTIVE C

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COM'L: H-5/7/10/15/25, Q-10/15/25 IND: H-10/15/20/25
PALCE22V10 Family
24-Pin CMOS Versatile Device
DISTINCTIVE CHARACTERISTICS
fast 5-ns propagation delay 142.8 fMAX (external) Low-power CMOS macrocells programmable registered combinatorial, active high active match application needs Varied product term distribution allows product terms output complex functions Peripheral Component Interconnect (PCI) compliant (-5/-7/-10) Global asynchronous reset synchronous preset initialization Power-up reset initialization register preload testability Extensive third-party software programmer support through FusionPLD partners 24-pin SKINNYDIP, 24-pin SOIC, 24-pin Flatpack 28-pin PLCC packages save space 5-ns 7.5-ns versions utilize split leadframes improved performance
GENERAL DESCRIPTION
PALCE22V10 provides user-programmable logic replacing conventional SSI/MSI gates flip-flops reduced chip count. device implements familiar Boolean logic transfer function, products. device programmable array driving fixed array. array programmed create custom product terms, while array sums selected terms outputs. product terms connected fixed array with varied distribution from to16 across outputs (see Block Diagram). products feeds output macrocell. Each macrocell programmed registered combinatorial, active high active low. output configuration determined bits controlling multiplexers each macrocell. AMD's FusionPLD program allows PALCE22V10 designs implemented using wide variety popular industry-standard design tools. working closely with FusionPLD partners, certifies that tools provide accurate, quality support. ensuring that thirdparty tools available, costs lowered because designer does have complete tools each device. FusionPLD program also greatly reduces design time since designer tool that already installed familiar.
BLOCK DIAGRAM
CLK/I0
Programmable Array 132)
RESET
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL
OUTPUT LOGIC MACRO CELL PRESET
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
I/O8
I/O9
16564D-1
Publication# 16564 Rev. Issue Date: February 1996
Amendment
2-217
CONNECTION DIAGRAMS View SKINNYDIP/SOIC/FLATPACK
CLK/I0 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
16564D-2
PLCC/LCC
CLK/I0 I/O9 I/O8
I/O7 I/O6 I/O5 GND/NC* I/O4 I/O3 I/O2
I/O0 I/O1
16564D-3
this must grounded guaranteed data sheet performance. grounded, timing degrade about 10%. Note: marked orientation.
DESIGNATIONS
Clock Input Input/Output Connect Supply Voltage Ground
2-218
PALCE22V10 Family
ORDERING INFORMATION Commercial Industrial Products
programmable logic products commercial industrial applications available with several ordering options. order number (Valid Combination) formed combination
FAMILY TYPE Programmable Array Logic TECHNOLOGY CMOS Electrically Erasable NUMBER ARRAY INPUTS OUTPUT TYPE Versatile NUMBER OUTPUTS POWER Quarter Power ICC) Half Power (90-140 ICC)
OPTIONAL PROCESSING Blank Standard Processing PROGRAMMING DESIGNATOR Blank Initial Algorithm First Revision Second Revision (Same Algorithm OPERATING CONDITIONS Commercial (0°C +75°C) Industrial (-40°C +85°C) PACKAGE TYPE 24-Pin Plastic SKINNYDIP (PD3024) 28-Pin Plastic Leaded Chip Carrier 028) 24-Pin Plastic Gull-Wing Small Outline Package 024) SPEED
Valid Combinations PALCE22V10-5 PALCE22V10H-7 PALCE22V10H-10 PALCE22V10Q-10 PALCE22V10H-15 Blank, PALCE22V10Q-15 PALCE22V10H-20 PALCE22V10H-25 Blank, PALCE22V10Q-25 Valid Combinations Valid Combinations lists configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
PALCE22V10H-5/7/10/15/25, Q-10/15/25 (Com'l) PALCE22V10H-10/15/20/25 (Ind)
2-219
FUNCTIONAL DESCRIPTION
PALCE22V10 allows systems engineer implement design on-chip, programming cells configure gates within device, according desired logic function. Complex interconnections between gates, which previously required timeconsuming layout, lifted from board placed silicon, where they easily modified during prototyping production. Product terms with connections opened assume logical HIGH state; product terms connected both true complement single input assume logical state. PALCE22V10 inputs macrocells. macrocell (Figure allows four potential output configurations; registered output combinatorial I/O, active high active (see Figure configuration choice made according user's design
specification corresponding programming configuration bits Multiplexer controls connected ground through programmable bit, selecting path through multiplexer. Erasing disconnects control line from driven high level, selecting path. device produced with cell link each input gate array, connections selectively removed applying appropriate voltages circuit. Utilizing easily-implemented programming algorithm, these products rapidly programmed customized pattern.
Variable Input/Output Ratio
PALCE22V10 twelve dedicated input lines, each macrocell output pin. Buffers device inputs have complementary outputs provide user-programmable input signal polarity. Unused input pins should tied GND.
Output Configuration Registered/Active Registered/Active High Combinatorial/Active Combinatorial/Active High I/On
Programmed Erased (charged)
16564D-4
Figure Output Logic Macrocell Diagram
2-220
PALCE22V10 Family
Registered Output Configuration
Each macrocell PALCE22V10 includes D-type flip-flop data storage synchronization. flipflop loaded LOW-to-HIGH transition clock input. registered configuration array feedback from flip-flop.
Combinatorial Configuration
macrocell configured combinatorial selecting multiplexer path that bypasses flip-flop combinatorial configuration feedback from pin.
Registered/Active
Combinatorial/Active
Registered/Active High
Combinatorial/Active High
16564D-5
Figure Macrocell Configuration Options
PALCE22V10 Family
2-221
Programmable Three-State Outputs
Each output three-state output buffer with threestate control. product term controls buffer, allowing enable disable function product device inputs output feedback. combinatorial output provides bidirectional pin, configured dedicated input buffer always disabled.
direct loading arbitrary states, making unnecessary cycle through long test vector sequences reach desired state. addition, transitions from illegal states verified loading illegal states observing proper recovery.
Security
After programming verification, PALCE22V10 design secured programming security bit. Once programmed, this defeats readback internal programmed pattern device programmer, securing proprietary designs from competitors. When security programmed, array will read every erased, preload will disabled. only erased conjunction with erasure entire pattern.
Programmable Output Polarity
polarity each macrocell output active high active low, either match output signal needs reduce product terms. Programmable polarity allows Boolean expressions written their most compact form (true inverted), output still desired polarity. also save "DeMorganizing" efforts. Selection controlled programmable output macrocell, affects both registered combinatorial outputs. Selection automatic, based design specification definitions. definition output equation have same polarity, output programmed active high
Programming Erasing
PALCE22V10 programmed standard logic programmers. also erased reset previously configured device back virgin state. Erasure automatically performed programming hardware. special erase operation required.
Preset/Reset
initialization, PALCE22V10 Preset Reset product terms. These terms connected registered outputs. When Synchronous Preset (SP) product term asserted high, output registers will loaded with HIGH next LOW-to-HIGH clock transition. When Asynchronous Reset (AR) product term asserted high, output registers will immediately loaded with independent clock. Note that preset reset control flip-flop, output pin. output level determined output polarity selected.
Quality Testability
PALCE22V10 offers very high level built-in quality. erasability device provides direct means verifying performance parameters. addition, this verifies complete programmability functionality device provide highest programming yields post-programming functional yields industry.
Technology
high-speed PALCE22V10 fabricated with AMD's advanced electrically erasable (EE) CMOS process. array connections formed with proven cells. Inputs outputs designed compatible with devices. This technology provides strong input clamp diodes, output slew-rate control, grounded substrate clear switching.
Power-Up Reset
flip-flops power-up logic predictable system initialization. Outputs PALCE22V10 will depend programmed output polarity. rise must monotonic reset delay time 1000 maximum.
Compliance
PALCE22V10H-5/7/10 fully compliant with Local Specification published Special Interest Group. PALCE22V10H-5/7/10's predictable timing ensures compliance with specifications independent design.
Register Preload
register PALCE22V10 preloaded from output pins facilitate functional testing complex state machine designs. This feature allows
2-222
PALCE22V10 Family
LOGIC DIAGRAM SKINNYDIP/SOIC/FLATPACK (PLCC/LCC) Pinouts
CLK/I
(28)
(27)
(26)
(25)
(24)
(23)
(21)
(20)
(19)
(10)
(18)
(11)
(17)
(12) (13)
(16)
(14)
16564D-6
PALCE22V10 Family
2-223
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Supply Current Test Conditions -3.2 -100 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, Max, (Note VOUT Max, (Note VOUT (Note Outputs Open, (IOUT mA), Outputs Open, (IOUT mA), Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-224
PALCE22V10H-5 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR tARW tARR tSPR Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Setup Time from Clock Hold Time Clock Output Skew Between Registered Outputs (Note Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 142.8 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. Skew measured with outputs switching same direction. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10H-5 (Com'l)
2-225
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Supply Current Test Conditions -3.2 -100 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, Max, (Note VOUT Max, (Note VOUT 25°C (Note Outputs Open, (IOUT mA), Outputs Open, (IOUT mA), Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-226
PALCE22V10H-7 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tSKEWR tARW tARR tSPR fMAX Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Setup Time from Clock Hold Time Clock Output Skew Between Registered Outputs (Note Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 142.8 PDIP PLCC Unit
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. Skew measured with outputs switching same direction. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10H-7 (Com'l)
2-227
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Dynamic) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, Max, (Note VOUT (Note VOUT (Note Outputs Open, (IOUT mA), Max,
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-228
PALCE22V10H-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR fMAX Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input Feedback Setup Time from Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 83.3 Unit
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10H-10 (Com'l)
2-229
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground +4.75 +5.25
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) Parameter Description Output HIGH Voltage Output Voltage Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current Test Conditions -3.2 -100 -100 -130 Unit
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, (Note VOUT (Note VOUT 25°C (Note Outputs Open (IOUT mA), (Note
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation. This parameter guaranteed worst case under test condition. Refer frequency graph typical characteristics.
2-230
PALCE22V10Q-10 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT Unit
25°C
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Clock Width Maximum Frequency (Note Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCO) (Note 1/(tWH tWL) Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10Q-10 (Com'l)
2-231
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current +75°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Commercial Devices Ambient Temperature (TA) Operating Free +75°C Supply Voltage (VCC) with Respect Ground (H/Q-15) +4.75 +5.25 Supply Voltage (VCC) with Respect Ground (H/Q-25) +4.5 +5.5
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL Parameter Description Output HIGH Voltage Test Conditions -3.2 -100 Unit
Output Voltage
Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, Max, (Note VOUT Max, (Note VOUT 25°C (Note Outputs Open (IOUT mA),
-100
-130
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-232
PALCE22V10H-15/25, Q-15/25 (Com'l)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note
Parameter Symbol tARW tARR tSPR Parameter Description Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width Maximum Frequency (Note HIGH External Feedback Internal Feedback (fCNT) 1/(tS tCO) 1/(tS tCF) (Note 58.8 33.3 35.7 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, evaluated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10H-15/25, Q-15/25 (Com'l)
2-233
ABSOLUTE MAXIMUM RATINGS
Storage Temperature -65°C +150°C Ambient Temperature with Power Applied -55°C +125°C Supply Voltage with Respect Ground -0.5 +7.0 Input Voltage -0.5 Output Voltage -0.5 Static Discharge Voltage 2001 Latchup Current -40°C +85°C)
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure absolute maximum ratings extended periods affect device reliability.
OPERATING RANGES
Industrial Devices Ambient Temperature (TA) Operating Free -40°C +85°C Supply Voltage (VCC) with Respect Ground +4.5 +5.5
Operating Ranges define those limits between which functionality device guaranteed.
CHARACTERISTICS over INDUSTRIAL operating ranges unless otherwise specified
Parameter Symbol IOZH IOZL (Static) (Dynamic) Parameter Description Output HIGH Voltage Test Conditions -3.2 -100 Unit
Output Voltage
Input HIGH Voltage Input Voltage Input HIGH Leakage Current Input Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current Output Short-Circuit Current Supply Current H-20/25 H-10/15 Supply Current
Guaranteed Input Logical HIGH Voltage Inputs (Note Guaranteed Input Logical Voltage Inputs (Note VCC, (Note (Note VOUT VCC, Max, (Note VOUT Max, (Note VOUT 25°C (Note Outputs Open (IOUT mA), Outputs Open (IOUT mA), Max,
-100
-130
Notes: These absolute values with respect device ground overshoots system tester noise included. leakage worst case IOZL IOZH). more than output should tested time. Duration short-circuit test should exceed second. VOUT been chosen avoid test problems caused tester ground degradation.
2-234
PALCE22V10H-10/15/20/25 (Ind)
CAPACITANCE (Note
Parameter Symbol COUT Parameter Description Input Capacitance Output Capacitance Test Conditions VOUT 25°C Unit
Note: These parameters 100% tested, evaluated initial characterization time design modified where capacitance affected.
SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note
Parameter Symbol Parameter Description tARW tARR tSPR Maximum Frequency (Note Input Feedback Combinatorial Output Setup Time from Input, Feedback Clock Hold Time Clock Output Asynchronous Reset Registered Output Asynchronous Reset Width Asynchronous Reset Recovery Time Synchronous Preset Recovery Time Clock Width HIGH External Feedback Internal Feedback (fCNT) Feedback 1/(tS tCO) 1/(tS tCF) (Note 1/(tWH tWL) 83.3 58.8 83.3 41.6 45.4 33.3 35.7 38.5 Unit
fMAX
Input Output Enable Using Product Term Control Input Output Disable Using Product Term Control
Notes: Switching Test Circuit test conditions. These parameters 100% tested, calculated initial characterization time design modified where frequency affected. calculated value guaranteed. found using following equation: 1/fMAX (internal feedback)
PALCE22V10H-10/15/20/25 (Ind)
2-235
SWITCHING WAVEFORMS
Input Feedback Input Feedback Combinatorial Output
16564D-7
Clock
Registered Output
16564D-8
Combinatorial Output
Registered Output
Input Clock
16564D-9
0.5V 0.5V
16564D-10
Output
Clock Width
Input Output Disable/Enable
Input Asserting Asynchronous Reset
tARW
Input Asserting Synchronous Preset Registered Output
tSPR
Registered Output
tARR
Clock
Clock
16564D-11
16564D-12
Asynchronous Reset
Synchronous Preset
Notes: Input pulse amplitude Input rise fall times typical.
2-236
PALCE22V10 Family
SWITCHING WAVEFORMS
WAVEFORM INPUTS Must Steady Change from Change from Don't Care, Change Permitted Does Apply OUTPUTS Will Steady Will Changing from Will Changing from Changing, State Unknown Center Line HighImpedance "Off" State
KS000010-PAL
SWITCHING TEST CIRCUIT
Output Test Point
16564D-13
Commercial Specification tPD, Closed Open Closed Open Closed except H-5/7: H-5/7:
Measured Output Value
PALCE22V10 Family
2-237
TYPICAL CHARACTERISTICS 25°C
22V10H-5 22V10H-7 22V10H-10
(mA)
22V10H-15 22V10H-25 22V10Q-10 22V10Q-25
16564D-14
Frequency (MHz)
Frequency
selected "typical" pattern utilized device resources. Half macrocells were programmed registered, other half were programmed combinatorial. Half available product terms were used each macrocell. vector, half outputs were switching. utilizing device, midpoint defined ICC. From this midpoint, designer scale graphs down estimate requirements particular design.
2-238
PALCE22V10 Family
ENDURANCE CHARACTERISTICS
PALCE22V10 manufactured using AMD's advanced Electrically Erasable process. This technology uses cell replace fuse link used bipolar parts. result, device erased reprogrammed-a feature which allows 100% testing factory.
Endurance Characteristics
Symbol Parameter Pattern Data Retention Time Reprogramming Cycles Test Conditions Storage Temperature Normal Programming Conditions Unit Years Cycles
Bus-Friendly Inputs
PALCE22V10H-15/25, Q-25 (Com'l) H-20 (Ind) inputs loop back input after second stage input buffer. This configuration reinforces state input pulls voltage away from
input threshold voltage. Unlike pull-up, this configuration cannot cause contention bus. illustration this configuration, input/output equivalent schematics.
PALCE22V10 Family
2-239
INPUT/OUTPUT EQUIVALENT SCHEMATICS SELECTED DEVICES*
Protection
Input
Preload Circuitry
Feedback Input
16564D-15
Output
Device PALCE22V10H-15 PALCE22V10H-20 PALCE22V10H-25 PALCE22V10Q-25 Letter
2-240
PALCE22V10 Family
ROBUSTNESS FEATURES
PALCE22V10X-X/5 devices have some unique features that make them extremely robust, especially when operating high-speed design environments. Pull-up resistors inputs pins cause unconnected pins default known state. Input clamping circuitry limits negative overshoot, eliminating
possibility false clocking caused subsequent ringing. special noise filter makes programming circuitry completely insensitive positive overshoot that pulse width less than about version. Selected devices also being retrofitted with these robustness features. chart below device listing.
INPUT/OUTPUT EQUIVALENT SCHEMATICS VERSION SELECTED DEVICES*
Protection Clamping
Programming Pins only
Programming Voltage Detection
Positive Overshoot Filter
Programming Circuitry
Typical Input
Provides Protection Clamping Preload Circuitry Feedback Input
16564D-16
Typical Output
Device PALCE22V10H-15 PALCE22V10H-25 PALCE22V10Q-25
Letter
Topside Marking: CMOS PLD's marked package following manner: PALCEXXXX Datecode numbers) characters)- -(Rev Letter) Letter separated spaces.
PALCE22V10 Family
2-241
POWER-UP RESET
power-up reset feature ensures that flip-flops will reset after device been powered output state will depend programmed pattern. This feature valuable simplifying state machine initialization. timing diagram parameter table shown below. synchronous operation power-up reset wide range ways
Parameter Symbol Parameter Description Power-up Reset Time Input Feedback Setup Time Clock Width
rise steady state, conditions required ensure valid power-up reset. These conditions are:
rise must monotonic. Following reset, clock input must driven
from HIGH until applicable input feedback setup times met.
1000 Switching Characteristics Unit
Power
Registered Active-Low Output
Clock
16564D-17
Power-Up Reset Waveform
2-242
PALCE22V10 Family
TYPICAL THERMAL CHARACTERISTICS PALCE22V10/4 (PALCE22V10H-15)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
PALCE22V10/5 (PALCE22V10H-10)
Measured 25°C ambient. These parameters tested.
Parameter Symbol Parameter Description Thermal impedance, junction case Thermal impedance, junction ambient Thermal impedance, junction ambient with flow lfpm lfpm lfpm lfpm SKINNYDIP PLCC Unit °C/W °C/W °C/W °C/W °C/W °C/W
Plastic Considerations data listed plastic reference only recommended calculating junction temperatures. heat-flow paths plastic-encapsulated devices complex, making measurement relative specific location package surface. Tests indicate this measurement reference point directly below die-attach area bottom center package. Furthermore, tests packages performed constant-temperature bath, keeping package surface constant temperature. Therefore, measurements only used similar environment.
PALCE22V10 Family
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PALCE22V10 Family 24-Pin CMOS Versatile Device DISTINCTIVE C

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