High performance networked applications IBM® Microelectronics

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PowerPC 440GP Embedded Processor:
High performance networked applications
IBM® Microelectronics
information these materials subject change without notice. information provided basis, without warranty kind.
Design Objectives Strategy
Develop high performance, highly integrated system chip, while utilizing ASIC methodology Provide base state-of-the-art reusable core future PowerPC 440-based designs Target integrated features networked applications Network infrastructure, network access devices, storage area networks, RAID controllers, Maintain aggressive price power characteristics traditional PowerPC designs Provide PowerPC Book architecture compliance
PowerPC Embedded Processor Roadmap
Production Availability 2000 2001
desi ased re-b logy chno itive sens
next gen.
Processor Cores
75MHz 405CR 405GP 401GF 50MHz 403GA/GB/ GC/GCX 25-80MHz 200-266MHz ASSP 80MHz 200-266MHz DMIPS
266-366MHz copper tech.
400-555MHz 1000 DMIPS
440GP
ASSP
400-500MHz copper tech.
200-266MHz
Blue Logic Superstructure Products
Future availability dates subject change without notice
440GP Block Diagram
64-bit PCI-X 32/64-bit 32/64-bit w/ECC On-chip Peripheral (OPB) 33-66MHz On-chip Peripheral (OPB) RAM/ROM peripheral controller External master cntlr. UART UART GPIO interface, 32-bit addr, 32bit data
PCI-X Bridge
DDR266 SDRAM Cntlr.
Bridge
133MHz
Processor Local (PLB)
128-bit
I-Cache JTAG
D-Cache
SRAM Cntlr.
SRAM
Cntlr.
Trace
Interrupt Cntlr.
10/100 Ethernet
PowerPC 440A4
440GP Architectural Features
PowerPC Book compliant enables flexible implementations provides enhancements specifically embedded applications retains PowerPC compatibility Application code written other PowerPC processors will unchanged 440GP initializes extracts info from devices uniform manner Cache modes normal, transient, locked Address translation enabled times
440GP Processor Core Features
Superscalar: instructions cycle, order execution stage pipeline Caches 32KB instruction 32KB data cache 64-way associative, byte line Dynamic branch prediction: entry BTAC, entry BHT, Gshare algorithm Interrupt controller supports external internal interrupts 36-bit real address 64-entry, unified, fully associative 4-entry instruction µTLB 8-entry data µTLB
128-bit Processor Local I-cache D-cache
I-cache Control
D-cache Control
Instruction Branch Unit Unit
Complex Integer Pipe Timers Power Management Interrupts Simple Integer Pipe Load Store Pipe
Debug/Trace
PowerPC 440A4 Core
128-bit CoreConnect Architecture
Processor Local Bus: separate simultaneous read write 128-bit data paths 36-bit address simultaneous address data phases 133MHz, maximum 4.2GB/ processor/bus ratios 2.5, 3.5, On-Chip Peripheral Bus: dynamic sizing 32-, 16-, 36-bit address 66MHz, maximum 266MB/
Proc Core SDRAM Core
PCI-X Core
Ethernet Core
SRAM
Controller
UART
External Ctrl
GPIO
SDRAM Memory Controller
Supports industry standard DIMMs JEDEC PC200/266 compliant Maximum addressability 32-bit 64-bit memory interface with optional 8-bit (SECDED) GB/s peak bandwidth Page mode accesses open pages) with configurable paging Programmable address mapping timing initiated self-refresh
Device Control Registers (21) Slave Address Decode SRAM Control Page Mgmt
Write Buffer (512 bytes)
Write Control SECDED Interface Layer Read Control
Request Queue
Read Buffer (256 bytes)
SECDED Refresh Initialize
PCI-X Interface
PCI-X
PCI-X V1.0 V2.2 split transactions PCI-X frequency 133MHz asynchronous with latch-to-latch transfers frequency 66MHz register addressable from on-chip processor device sides Boot from memory Message Signaled Interrupt support
PCI-X Control Registers (76)
Address Decode
Inbound Write bytes)
Inbound Read bytes) Request Queue Arbiter
Outbound Write bytes)
Outbound Read bytes) bytes)
External Controller
Four Channels scatter/gather address increment decrement 16-, 32-bit external data width Separate 32-bit address External master interface chip selects external peripherals Burst non-burst devices
Data Execution Unit Arbiter
Controller Channel Channel Control Count Register Scatter Gather Registers Register Destination Address Register Source Address Register Channel
OPB/PLB Buffer Control
Buffer (128 bytes)
Channel Channel Connections Interface Controller Interface
EBCO External SRAM External Peripherals
On-Chip Bandwidth Optimization
Performance processor: 720DMIPS 400MHz) SDRAM: 2.1GB/s PCI-X: 1.06GB/s PLB: 4.2GB/s 128bits, bottleneck 64bits, underutilized 256-bits OPB: 266MB/s 32-bits ethernet 10/100 Mb/s each Buffering queuing support these rates
64-bit
Transaction Time Increase
128-bit
256-bit
Percent Load
440GP Wired Communications
Processor: host PCI: network interface, interprocessor communication Dual Ethernet: interprocessor communication modem
SDRAM: Large storage routing tables External Bus: flash modem DSPs encryption/compression processors
440GP (Control Proc) Ethernet
Network
Slave 440GP
Slave 440GP
Slave 440GP
SDRAM (Routing Tables)
440GP Storage Applications
Processor: Disk Controller PCI-X: disk controller (440GP) Storage Area Network directly host bridge SCSI-3/4 drives Ethernet: system control
Host Processor PCI-X
Large SDRAM storage following: disk cache RAID External Bus: FPGA
SDRAM
440GP Ext.
Ethernet
SCSI Bridge
PowerPC 440GP Statistics
Frequency
Performance (Dhrystone 2.1) Power Dissipation (est. typical) Architecture
DMIPS 32-bit PowerPC Book compliant, application code compatible with PowerPC processors 32/32 64-way set-associative CBGA, size, pitch, signal I/Os 0.18 (0.11lm Leff) CMOS SA-27E copper, metal layers logic, SDRAM I/Os, other I/Os
size Caches Package Technology Voltage
Summary
"Beauty beholder performance measure."
Thank you!
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High performance networked applications IBM® Microelectronics

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