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74HC00 74HCT00 Quad 2-input NAND gate

Product specification Supersedes data of 1997 Aug 26 2003 Jun 30

INTEGRATED CIRCUITS
DATA SHEET
74HC00 74HCT00 Quad 2-input NAND gate
Product specification Supersedes data of 1997 Aug 26 2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
The 74HC00 / 74HCT00 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC00 / 74HCT00 provide the 2-input NAND function.
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC00N 74HCT00N 74HC00D 74HCT00D 74HC00DB 74HCT00DB 74HC00PW 74HCT00PW 74HC00BQ 74HCT00BQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1A 1B 1Y 2A 2B 2Y GND 3Y 3A 3B 4Y 4A 4B VCC DESCRIPTION data input data input data output data input data input data output ground (0 V) data output data input data input data output data input data input supply voltage Fig.1
handbook, halfpage
74HC00 74HCT00
TEMPERATURE RANGE -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C -40 to +125 °C
PINS 14 14 14 14 14 14 14 14 14 14
PACKAGE DIP14 DIP14 SO14 SO14 SSOP14 SSOP14 TSSOP14 TSSOP14 DHVQFN14 DHVQFN14
MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic
CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1
1A 1B 1Y 2A 2B 2Y GND
MNA210
14 VCC 13 4B 12 4A
Pin configuration DIP14, SO14 and (T)SSOP14.
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
handbook, halfpage
MNA211
GND(1)
MNA950
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.2 Pin configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
handbook, halfpage handbook, halfpage
MNA212
MNA246
Fig.4 Function diagram.
Fig.5 IEC logic symbol.
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
74HCT00 UNIT MIN. 4.5 0 0 -40 TYP. 5.0 - - +25 MAX. 5.5 VCC VCC +125 V V V °C
tr, tf
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
ICC ICC
quiescent supply current additional supply current per input
ICC ICC Note
quiescent supply current additional supply current per input
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
AC WAVEFORMS
74HC00 74HCT00
handbook, halfpage
VI VM GND tPHL VOH tPLH
nA, nB input
nY output VOL
VM tTHL tTLH
MNA218
Fig.6 Waveforms showing the input (nA, nB) to output (nY) propagation delays.
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
PACKAGE OUTLINES DIP14: plastic dual in-line package 14 leads (300 mil)
74HC00 74HCT00
SOT27-1
D seating plane
pin 1 index E
5 scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
SO14: plastic small outline package 14 leads body width 3.9 mm
SOT108-1
2.5 scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
inches 0.069
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
SSOP14: plastic shrink small outline package 14 leads body width 5.3 mm
SOT337-1
2.5 scale
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 0o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
TSSOP14: plastic thin shrink small outline package 14 leads body width 4.4 mm
SOT402-1
w M detail X
2.5 scale
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00 74HCT00
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package no leads SOT762-1 14 terminals body 2.5 x 3 x 0.85 mm
terminal 1 index area
detail X
terminal 1 index area e 2 L
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003 Jun 30
Philips Semiconductors
Product specification
Quad 2-input NAND gate
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC00 74HCT00
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product / Process Change Notification (CPCN).
Preliminary data Qualification
Product data
Production
2003 Jun 30
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508 / 03 / pp17
Date of release: 2003
Jun 30
Document order number: