74HC00; 74HCT00 Quad 2-input NAND gate Product specification Supe
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74HC00; 74HCT00 Quad 2-input NAND gate
Product specification Supersedes data 1997 2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES Complies with JEDEC standard 8-1A protection: EIA/JESD22-A114-A exceeds 2000 EIA/JESD22-A115-A exceeds Specified from +125 QUICK REFERENCE DATA Tamb DESCRIPTION
74HC00; 74HCT00
74HC00/74HCT00 high-speed Si-gate CMOS devices compatible with power Schottky (LSTTL). They specified compliance with JEDEC standard 74HC00/74HCT00 provide 2-input NAND function.
TYPICAL SYMBOL tPHL/tPLH Notes used determine dynamic power dissipation µW). VCC2 VCC2 where: input frequency MHz; output frequency MHz; output load capacitance supply voltage Volts; total load switching outputs; VCC2 outputs. 74HC00 condition VCC. 74HCT00 condition FUNCTION TABLE note INPUT Note HIGH voltage level; voltage level. OUTPUT PARAMETER propagation delay input capacitance power dissipation capacitance gate notes CONDITIONS 74HC00 74HCT00 UNIT
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC00N 74HCT00N 74HC00D 74HCT00D 74HC00DB 74HCT00DB 74HC00PW 74HCT00PW 74HC00BQ 74HCT00BQ PINNING SYMBOL DESCRIPTION data input data input data output data input data input data output ground data output data input data input data output data input data input supply voltage Fig.1
handbook, halfpage
74HC00; 74HCT00
TEMPERATURE RANGE +125 +125 +125 +125 +125 +125 +125 +125 +125 +125
PINS
PACKAGE DIP14 DIP14 SO14 SO14 SSOP14 SSOP14 TSSOP14 TSSOP14 DHVQFN14 DHVQFN14
MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic
CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1
MNA210
configuration DIP14, SO14 (T)SSOP14.
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
handbook, halfpage
handbook, halfpage
view
MNA211
GND(1)
MNA950
substrate attached this using conductive attach material. used supply input.
Fig.2 configuration DHVQFN14.
Fig.3 Logic diagram (one gate).
handbook, halfpage handbook, halfpage
MNA212
MNA246
Fig.4 Function diagram.
Fig.5 logic symbol.
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
RECOMMENDED OPERATING CONDITIONS 74HC00 SYMBOL Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise fall times CONDITIONS MIN. characteristics device TYP. MAX. +125
74HC00; 74HCT00
74HCT00 UNIT MIN. TYP. MAX. +125
1000
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 60134); voltages referenced (ground SYMBOL ICC, IGND Tstg Ptot Note DIP14 packages: above derate linearly with mW/K. SO14 packages: above derate linearly with mW/K. SSOP14 TSSOP14 packages: above derate linearly with mW/K. DHVQFN14 packages: above derate linearly with mW/K. PARAMETER supply voltage input diode current output diode current output source sink current current storage temperature power dissipation Tamb +125 note -0.5 -0.5 -0.5 CONDITIONS MIN. -0.5 MAX. +7.0 +150 UNIT
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
CHARACTERISTICS Type 74HC00 recommended operating conditions; voltages referenced (ground TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb note HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 -5.2 LOW-level output voltage input leakage current 3-state output current VIL; quiescent supply current 3.84 5.34 3.15 MIN.
74HC00; 74HCT00
TYP.
MAX.
UNIT
4.32 5.81 0.15 0.16
1.35 0.33 0.33 ±1.0 ±.5.0
GND;
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb +125 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 -5.2 LOW-level output voltage Note typical values measured Tamb input leakage current 3-state output current VIL; quiescent supply current ±1.0 ±10.0 3.15 1.35 MIN. TYP. MAX. UNIT
GND;
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
Type 74HCT00 recommended operating conditions; voltages referenced (ground TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb note HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 LOW-level output voltage input leakage current 3-state output current
74HC00; 74HCT00
MIN.
TYP.
MAX.
UNIT
4.32 0.15
0.33 ±1.0 ±5.0
3.84
VIL; GND; GND;
quiescent supply current additional supply current input
Tamb +125 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 LOW-level output voltage input leakage current 3-state output current ±1.0
VIL; GND; GND;
Note
quiescent supply current additional supply current input
typical values measured Tamb
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
CHARACTERISTICS Type 74HC00 TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb note tPHL/tPLH propagation delay Fig.6 Fig.6 Fig.6 tTHL/tTLH output transition time Tamb +125 tPHL/tPLH propagation delay Fig.6 Fig.6 Fig.6 tTHL/tTLH output transition time Note typical values measured Tamb Type 74HCT00 TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb note tPHL/tPLH tTHL/tTLH propagation delay output transition time Fig.6
74HC00; 74HCT00
MIN.
TYP.
MAX.
UNIT
MIN.
MAX.
UNIT
Tamb +125 tPHL/tPLH tTHL/tTLH Note typical values measured Tamb propagation delay output transition time Fig.6
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
WAVEFORMS
74HC00; 74HCT00
handbook, halfpage
tPHL tPLH
input
output
tTHL tTLH
MNA218
74HC00: 50%; VCC. 74HCT00:
Fig.6 Waveforms showing input (nA, output (nY) propagation delays.
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
PACKAGE OUTLINES DIP14: plastic dual in-line package; leads (300 mil)
74HC00; 74HCT00
SOT27-1
seating plane
index
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 0.17 min. 0.51 0.02 max. 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 0.39 0.33 0.254 0.01 max. 0.087
Note Plastic metal protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT27-1 REFERENCES 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
SO14: plastic small outline package; leads; body width
SOT108-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT max. 1.75 0.25 0.10 1.45 1.25 0.25 0.01 0.49 0.36 0.25 0.19 8.75 8.55 0.16 0.15 1.27 0.05 1.05 0.028 0.024 0.25 0.01 0.25 0.01 0.004 0.028 0.012
inches 0.069
0.010 0.057 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT108-1 REFERENCES 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
SSOP14: plastic shrink small outline package; leads; body width
SOT337-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 0.65 1.25 1.03 0.63 0.13
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT337-1 REFERENCES JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
TSSOP14: plastic thin shrink small outline package; leads; body width
SOT402-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.72 0.38
Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT402-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
74HC00; 74HCT00
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; leads; SOT762-1 terminals; body 0.85
terminal index area
detail
terminal index area
scale
DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 1.65 1.35 1.15 0.85 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT762-1 REFERENCES -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003
Philips Semiconductors
Product specification
Quad 2-input NAND gate
DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC00; 74HCT00
DEFINITION This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Preliminary data Qualification
Product data
Production
Notes Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status. DEFINITIONS Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification. DISCLAIMERS Life support applications These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
2003
Philips Semiconductors worldwide company
Contact information additional information please visit Fax: 24825 sales offices addresses send e-mail
Koninklijke Philips Electronics N.V. 2003
SCA75
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
613508/03/pp17
Date release: 2003
Document order number:
9397 11258
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